diff --git a/ip_cores/ec/src/rtl/ec_fp2_arithmetic.sv b/ip_cores/ec/src/rtl/ec_fp2_arithmetic.sv index 9a5dbce..1ae9b57 100644 --- a/ip_cores/ec/src/rtl/ec_fp2_arithmetic.sv +++ b/ip_cores/ec/src/rtl/ec_fp2_arithmetic.sv @@ -174,7 +174,7 @@ end enum {MUL0, MUL1, MUL2, MUL3} mul_state; logic [1:0] add_sub_val; always_comb begin - mul_if_fe2_i.rdy = (fp_mode_mul || mul_state == MUL3) && (~o_mul_fe_if.val || (o_mul_fe_if.val && o_mul_fe_if.rdy)); + i_mul_fe2_if.rdy = (fp_mode_mul || mul_state == MUL3) && (~o_mul_fe_if.val || (o_mul_fe_if.val && o_mul_fe_if.rdy)); i_mul_fe_if.rdy = fp_mode_mul ? ~o_mul_fe2_if.val || (o_mul_fe2_if.val && o_mul_fe2_if.rdy) : (i_mul_fe_if.ctl[CTL_BIT +: 2] == 0 || i_mul_fe_if.ctl[CTL_BIT +: 2] == 1) ? @@ -215,32 +215,32 @@ always_ff @ (posedge i_clk) begin if (~o_mul_fe_if.val || (o_mul_fe_if.val && o_mul_fe_if.rdy)) begin case (mul_state) MUL0: begin - o_mul_fe_if.copy_if({mul_if_fe2_i.dat[0 +: $bits(FE_TYPE)], - mul_if_fe2_i.dat[$bits(FE2_TYPE) +: $bits(FE_TYPE)]}, - mul_if_fe2_i.val, 1, 1, mul_if_fe2_i.err, mul_if_fe2_i.mod, mul_if_fe2_i.ctl); + o_mul_fe_if.copy_if({i_mul_fe2_if.dat[0 +: $bits(FE_TYPE)], + i_mul_fe2_if.dat[$bits(FE2_TYPE) +: $bits(FE_TYPE)]}, + i_mul_fe2_if.val, 1, 1, i_mul_fe2_if.err, i_mul_fe2_if.mod, i_mul_fe2_if.ctl); o_mul_fe_if.ctl[CTL_BIT +: 2] <= 0; - if (mul_if_fe2_i.val && ~fp_mode_mul) mul_state <= MUL1; + if (i_mul_fe2_if.val && ~fp_mode_mul) mul_state <= MUL1; end MUL1: begin - o_mul_fe_if.copy_if({mul_if_fe2_i.dat[$bits(FE_TYPE) +: $bits(FE_TYPE)], - mul_if_fe2_i.dat[$bits(FE2_TYPE) + $bits(FE_TYPE) +: $bits(FE_TYPE)]}, - mul_if_fe2_i.val, 1, 1, mul_if_fe2_i.err, mul_if_fe2_i.mod, mul_if_fe2_i.ctl); + o_mul_fe_if.copy_if({i_mul_fe2_if.dat[$bits(FE_TYPE) +: $bits(FE_TYPE)], + i_mul_fe2_if.dat[$bits(FE2_TYPE) + $bits(FE_TYPE) +: $bits(FE_TYPE)]}, + i_mul_fe2_if.val, 1, 1, i_mul_fe2_if.err, i_mul_fe2_if.mod, i_mul_fe2_if.ctl); o_mul_fe_if.ctl[CTL_BIT +: 2] <= 1; - if (mul_if_fe2_i.val) mul_state <= MUL2; + if (i_mul_fe2_if.val) mul_state <= MUL2; end MUL2: begin - o_mul_fe_if.copy_if({mul_if_fe2_i.dat[0 +: $bits(FE_TYPE)], - mul_if_fe2_i.dat[$bits(FE2_TYPE) + $bits(FE_TYPE) +: $bits(FE_TYPE)]}, - mul_if_fe2_i.val, 1, 1, mul_if_fe2_i.err, mul_if_fe2_i.mod, mul_if_fe2_i.ctl); + o_mul_fe_if.copy_if({i_mul_fe2_if.dat[0 +: $bits(FE_TYPE)], + i_mul_fe2_if.dat[$bits(FE2_TYPE) + $bits(FE_TYPE) +: $bits(FE_TYPE)]}, + i_mul_fe2_if.val, 1, 1, i_mul_fe2_if.err, i_mul_fe2_if.mod, i_mul_fe2_if.ctl); o_mul_fe_if.ctl[CTL_BIT +: 2] <= 2; - if (mul_if_fe2_i.val) mul_state <= MUL3; + if (i_mul_fe2_if.val) mul_state <= MUL3; end MUL3: begin - o_mul_fe_if.copy_if({mul_if_fe2_i.dat[$bits(FE_TYPE) +: $bits(FE_TYPE)], - mul_if_fe2_i.dat[$bits(FE2_TYPE) +: $bits(FE_TYPE)]}, - mul_if_fe2_i.val, 1, 1, mul_if_fe2_i.err, mul_if_fe2_i.mod, mul_if_fe2_i.ctl); + o_mul_fe_if.copy_if({i_mul_fe2_if.dat[$bits(FE_TYPE) +: $bits(FE_TYPE)], + i_mul_fe2_if.dat[$bits(FE2_TYPE) +: $bits(FE_TYPE)]}, + i_mul_fe2_if.val, 1, 1, i_mul_fe2_if.err, i_mul_fe2_if.mod, i_mul_fe2_if.ctl); o_mul_fe_if.ctl[CTL_BIT +: 2] <= 3; - if (mul_if_fe2_i.val) mul_state <= MUL0; + if (i_mul_fe2_if.val) mul_state <= MUL0; end endcase end diff --git a/ip_cores/ec/src/tb/ec_fp2_point_add_tb.sv b/ip_cores/ec/src/tb/ec_fp2_point_add_tb.sv index cc69262..a0ad89e 100644 --- a/ip_cores/ec/src/tb/ec_fp2_point_add_tb.sv +++ b/ip_cores/ec/src/tb/ec_fp2_point_add_tb.sv @@ -74,6 +74,7 @@ ec_fp2_point_add #( ec_fp2_point_add ( .i_clk ( clk ), .i_rst ( rst ), + .i_fp_mode ( 0 ), // Input points .i_p1 ( in_p1 ), .i_p2 ( in_p2 ), diff --git a/ip_cores/ec/src/tb/ec_fp2_point_dbl_tb.sv b/ip_cores/ec/src/tb/ec_fp2_point_dbl_tb.sv index bf07fd0..eabb791 100644 --- a/ip_cores/ec/src/tb/ec_fp2_point_dbl_tb.sv +++ b/ip_cores/ec/src/tb/ec_fp2_point_dbl_tb.sv @@ -73,6 +73,7 @@ ec_fp2_point_dbl #( ec_fp2_point_dbl ( .i_clk ( clk ), .i_rst ( rst ), + .i_fp_mode(0), // Input points .i_p ( in_p1 ), .i_val ( in_if.val ), diff --git a/ip_cores/ec/src/tb/ec_fp2_point_mult_tb.sv b/ip_cores/ec/src/tb/ec_fp2_point_mult_tb.sv index 36f01e7..e4b4c0a 100644 --- a/ip_cores/ec/src/tb/ec_fp2_point_mult_tb.sv +++ b/ip_cores/ec/src/tb/ec_fp2_point_mult_tb.sv @@ -100,6 +100,7 @@ ec_fp2_point_add #( ec_fp2_point_add ( .i_clk ( clk ), .i_rst ( rst ), + .i_fp_mode(0), // Input points .i_p1 ( add_i_if.dat[0 +: $bits(FP_TYPE)] ), .i_p2 ( add_i_if.dat[$bits(FP_TYPE) +: $bits(FP_TYPE)] ), @@ -125,6 +126,7 @@ ec_fp2_point_dbl #( ec_fp2_point_dbl ( .i_clk ( clk ), .i_rst ( rst ), + .i_fp_mode(0), .i_p ( dbl_i_if.dat), .i_val ( dbl_i_if.val ), .o_rdy ( dbl_i_if.rdy ), diff --git a/zcash_fpga/src/rtl/bls12_381/bls12_381_top.sv b/zcash_fpga/src/rtl/bls12_381/bls12_381_top.sv index 3895953..7354490 100644 --- a/zcash_fpga/src/rtl/bls12_381/bls12_381_top.sv +++ b/zcash_fpga/src/rtl/bls12_381/bls12_381_top.sv @@ -128,12 +128,12 @@ always_ff @ (posedge i_clk) begin fp2_pt_mult_out_if.rdy <= 1; binv_o_if.rdy <= 1; - + if (idx_in_if.val && idx_in_if.rdy) idx_in_if.val <= 0; if (interrupt_in_if.val && interrupt_in_if.rdy) interrupt_in_if.val <= 0; - + last_inst_cnt <= last_inst_cnt + 1; - + case(inst_state) NOOP_WAIT: begin last_inst_cnt <= last_inst_cnt; @@ -403,7 +403,7 @@ task task_scalar_inv(); binv_i_if.val <= 1; binv_i_if.dat <= curr_data.dat; pt_l <= curr_data.pt; - cnt <= cnt++; + cnt <= cnt + 1; end end 2: begin @@ -443,7 +443,7 @@ task task_point_mult(); 2: begin if (data_ram_read[READ_CYCLE]) begin data_ram_sys_if.a <= data_ram_sys_if.a + 1; - if (curr_data.pt == FP_AF || curr_data.pt == FP_JB) + if (curr_data.pt == FP_AF || curr_data.pt == FP_JB) fp_pt_mult_mode <= 1; else fp_pt_mult_mode <= 0; @@ -601,7 +601,7 @@ task task_send_interrupt(); inst_ram_read[0] <= 1; end end - end + end 3: begin if (inst_ram_read[READ_CYCLE]) begin inst_state <= curr_inst.code; @@ -631,7 +631,7 @@ axi_stream_fifo #( .DAT_BITS ( 16 + 3 ) ) interrupt_index_fifo ( - .i_clk ( i_clk ), + .i_clk ( i_clk ), .i_rst ( i_rst ), .i_axi ( idx_in_if ), .o_axi ( idx_out_if ), @@ -647,12 +647,12 @@ end always_ff @ (posedge i_clk) begin if (i_rst) begin - interrupt_rpl <= 0; + interrupt_rpl <= 0; interrupt_state <= WAIT_FIFO; interrupt_hdr_byt <= 0; idx_out_if.rdy <= 0; tx_if.reset_source(); - end else begin + end else begin case (interrupt_state) WAIT_FIFO: begin idx_out_if.rdy <= 1;