Top level test bench
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bsdevlin
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56ad30d051
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/*
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The zcash_fpga_top testbench.
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Copyright (C) 2019 Benjamin Devlin and Zcash Foundation
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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`timescale 1ps/1ps
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module zcash_fpga_top_tb();
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import zcash_fpga_pkg::*;
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import equihash_pkg::*;
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import common_pkg::*;
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logic clk_if, rst_if;
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logic clk_300, rst_300;
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logic clk_200, rst_200;
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localparam CLK200_PERIOD = 600;
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localparam CLK300_PERIOD = 400;
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localparam IF_CLK_PERIOD = 1000;
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parameter DAT_BYTS = 8;
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parameter IF_DAT_BYTS = 4;
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string my_file_path_s = get_file_dir(`__FILE__);
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if_axi_stream #(.DAT_BYTS(IF_DAT_BYTS)) tx_if(clk_if);
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if_axi_stream #(.DAT_BYTS(IF_DAT_BYTS)) tx_346_if(clk_if);
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if_axi_stream #(.DAT_BYTS(IF_DAT_BYTS)) rx_if(clk_if);
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logic start_346 = 0;
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logic done_346 = 0;
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initial begin
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rst_300 = 0;
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repeat(2) #(20*CLK300_PERIOD) rst_300 = ~rst_300;
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end
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initial begin
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clk_300 = 0;
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forever #CLK300_PERIOD clk_300 = ~clk_300;
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end
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initial begin
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rst_200 = 0;
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repeat(2) #(20*CLK200_PERIOD) rst_200 = ~rst_200;
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end
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initial begin
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clk_200 = 0;
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forever #CLK200_PERIOD clk_200 = ~clk_200;
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end
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initial begin
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rst_if = 0;
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repeat(2) #(20*IF_CLK_PERIOD) rst_if = ~rst_if;
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end
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initial begin
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clk_if = 0;
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forever #IF_CLK_PERIOD clk_if = ~clk_if;
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end
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// Need one for each test so we can multiplex the input
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always_comb begin
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tx_346_if.rdy = 0;
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tx_if.val = 0;
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if (start_346 && ~done_346) begin
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tx_346_if.rdy = tx_if.rdy;
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tx_if.val = tx_346_if.val;
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tx_if.sop = tx_346_if.sop;
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tx_if.eop = tx_346_if.eop;
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tx_if.ctl = tx_346_if.ctl;
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tx_if.mod = tx_346_if.mod;
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tx_if.err = tx_346_if.err;
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tx_if.dat = tx_346_if.dat;
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end
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end
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file_to_axi #(
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.BINARY ( 1 ),
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.DAT_BYTS ( IF_DAT_BYTS ),
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.FP ( 0 )
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)
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file_to_axi_block346 (
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.i_file ({my_file_path_s, "/../data/block_346_with_header.bin"}),
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.i_clk ( clk_if ),
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.i_rst ( rst_if ),
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.i_start ( start_346 ),
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.o_done ( done_346 ),
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.o_axi ( tx_346_if )
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);
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zcash_fpga_top #(
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.IF_DAT_BYTS ( IF_DAT_BYTS ),
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.CORE_DAT_BYTS ( DAT_BYTS )
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)
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DUT(
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// Clocks and resets
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.i_clk_200 ( clk_200 ),
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.i_rst_200 ( rst_200 ),
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.i_clk_300 ( clk_300 ),
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.i_rst_300 ( rst_300 ),
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.i_clk_if ( clk_if ),
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.i_rst_if ( rst_if ),
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.rx_if ( tx_if ),
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.tx_if ( rx_if )
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);
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// This is a tests the sample block 346 in the block chain with the header to verify the equihash solution
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// Also send a status request to check it is correct
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task test_block_346_equihash();
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begin
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header_t header;
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fpga_status_rpl_t fpga_status_rpl;
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verify_equihash_rpl_t verify_equihash_rpl;
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integer signed get_len1, get_len2;
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logic [common_pkg::MAX_SIM_BYTS*8-1:0] get_dat1, get_dat2;
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logic fail = 0;
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$display("Running test_block_346_equihash...");
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header.cmd = FPGA_STATUS;
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header.len = $bits(header_t)/8;
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fork
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begin
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start_346 = 1;
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while(!done_346) @(posedge clk_if);
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tx_if.put_stream(header, $bits(header)/8);
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end
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begin
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rx_if.get_stream(get_dat1, get_len1);
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rx_if.get_stream(get_dat2, get_len2);
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end
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join
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verify_equihash_rpl = get_dat2;
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fpga_status_rpl = get_dat1;
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fail |= get_len2 != $bits(verify_equihash_rpl_t)/8;
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fail |= verify_equihash_rpl.hdr.cmd != VERIFY_EQUIHASH_RPL;
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fail |= verify_equihash_rpl.hdr.len != $bits(verify_equihash_rpl_t)/8;
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fail |= verify_equihash_rpl.index != 1;
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fail |= verify_equihash_rpl.bm != 0;
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assert (~fail) else $fatal(1, "%m %t ERROR: test_block_346_equihash equihash rply was wrong:\n%p", $time, verify_equihash_rpl);
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fail |= get_len1 != $bits(fpga_status_rpl_t)/8;
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fail |= fpga_status_rpl.hdr.cmd != FPGA_STATUS_RPL;
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fail |= fpga_status_rpl.hdr.len != $bits(fpga_status_rpl_t)/8;
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fail |= fpga_status_rpl.hdr.len != get_len1;
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fail |= fpga_status_rpl.version != FPGA_VERSION;
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fail |= fpga_status_rpl.build_host != "test";
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fail |= fpga_status_rpl.build_date != "20180311";
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fail |= fpga_status_rpl.fpga_state.typ1_state == 1;
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assert (~fail) else $fatal(1, "%m %t ERROR: test_block_346_equihash status reply was wrong:\n%p", $time, fpga_status_rpl);
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$display("test_block_346_equihash PASSED");
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end
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endtask
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// Main testbench calls
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initial begin
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rx_if.rdy = 0;
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#20us; // Let internal memories reset
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test_block_346_equihash();
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#1us $finish();
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end
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endmodule
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