From 12fd25958b209666723ce0fbc0a21d1200b34933 Mon Sep 17 00:00:00 2001 From: bsdevlin Date: Fri, 5 Apr 2019 17:21:07 -0400 Subject: [PATCH] Updates to debug and python files --- apps/python/zcash_fpga.py | 29 ++++++++++++++++++++++ bittware_xupvvh/ip/clk_wiz_0/clk_wiz_0.xci | 18 +++++++------- ip_cores/common/src/rtl/common_if.sv | 6 +++-- ip_cores/util/src/rtl/debug_if.sv | 20 +++++++-------- 4 files changed, 52 insertions(+), 21 deletions(-) create mode 100644 apps/python/zcash_fpga.py diff --git a/apps/python/zcash_fpga.py b/apps/python/zcash_fpga.py new file mode 100644 index 0000000..4413eca --- /dev/null +++ b/apps/python/zcash_fpga.py @@ -0,0 +1,29 @@ +class zcash_fpga: + import serial + import codecs + def __init__(self, COM='COM4'): + self.s = self.serial.Serial(COM, 921600, timeout=1) + #Test getting FPGA status + self.get_status() + print("Connected...") + + # FPGA status + def get_status(self): + self.s.write(self.codecs.decode('0800000001000000', 'hex')) + # Parse reply + res = self.s.read(1024) + print(res) + + + def close(self): + self.s.close() + print("Closed...") + + +#Example usage: + +zf = zcash_fpga() + +zf.close() + + diff --git a/bittware_xupvvh/ip/clk_wiz_0/clk_wiz_0.xci b/bittware_xupvvh/ip/clk_wiz_0/clk_wiz_0.xci index 36ff8f8..3bd4dcb 100644 --- a/bittware_xupvvh/ip/clk_wiz_0/clk_wiz_0.xci +++ b/bittware_xupvvh/ip/clk_wiz_0/clk_wiz_0.xci @@ -188,9 +188,9 @@ 0 VCO clk_in_sel - clk_out100 - clk_out200 - clk_out300 + clk_100 + clk_200 + clk_300 clk_out4 clk_out5 clk_out6 @@ -288,9 +288,9 @@ 3 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - clk_out100___100.000______0.000______50.0______115.831_____87.180 - clk_out200___200.000______0.000______50.0______102.086_____87.180 - clk_out300___300.000______0.000______50.0_______94.862_____87.180 + _clk_100___100.000______0.000______50.0______115.831_____87.180 + _clk_200___200.000______0.000______50.0______102.086_____87.180 + _clk_300___300.000______0.000______50.0_______94.862_____87.180 no_CLK_OUT4_output no_CLK_OUT5_output no_CLK_OUT6_output @@ -472,11 +472,11 @@ Custom Custom clk_in_sel - clk_out100 + clk_100 false - clk_out200 + clk_200 false - clk_out300 + clk_300 false clk_out4 false diff --git a/ip_cores/common/src/rtl/common_if.sv b/ip_cores/common/src/rtl/common_if.sv index f2a214c..8d2cd97 100644 --- a/ip_cores/common/src/rtl/common_if.sv +++ b/ip_cores/common/src/rtl/common_if.sv @@ -126,9 +126,9 @@ interface if_axi_stream # ( endtask; // Task used in simulation to get data from a sink interface - task automatic get_stream(ref logic [common_pkg::MAX_SIM_BYTS*8-1:0] data, ref integer signed len); + task automatic get_stream(ref logic [common_pkg::MAX_SIM_BYTS*8-1:0] data, ref integer signed len, input integer bp = 0); logic sop_l = 0; - rdy = 1; + rdy = ($random % 100) >= bp; len = 0; data = 0; @(posedge i_clk); @@ -145,7 +145,9 @@ interface if_axi_stream # ( if (eop) break; end @(posedge i_clk); + rdy = ($random % 100) >= bp; end + rdy = 1; endtask endinterface diff --git a/ip_cores/util/src/rtl/debug_if.sv b/ip_cores/util/src/rtl/debug_if.sv index 4315494..69b66d8 100644 --- a/ip_cores/util/src/rtl/debug_if.sv +++ b/ip_cores/util/src/rtl/debug_if.sv @@ -20,7 +20,7 @@ module debug_if #( parameter DAT_BYTS, parameter DAT_BITS = DAT_BYTS*8, - parameter MOD_BITS = $clog2(DAT_BYTS), + parameter MOD_BITS = DAT_BYTS == 1 ? 1 :$clog2(DAT_BYTS), parameter CTL_BITS ) ( if_axi_stream i_if @@ -35,15 +35,15 @@ module debug_if #( (* mark_debug = "true" *) logic [DAT_BITS-1:0] dat; (* mark_debug = "true" *) logic [MOD_BITS-1:0] mod; -always_comb begin - rdy = i_if.rdy; - val = i_if.val; - err = i_if.err; - sop = i_if.sop; - eop = i_if.eop; - ctl = i_if.ctl; - dat = i_if.dat; - mod = i_if.mod; +always_ff @ (posedge i_if.i_clk) begin + rdy <= i_if.rdy; + val <= i_if.val; + err <= i_if.err; + sop <= i_if.sop; + eop <= i_if.eop; + ctl <= i_if.ctl; + dat <= i_if.dat; + mod <= i_if.mod; end endmodule \ No newline at end of file