Add memory templates for Xilinx
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bsdevlin
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// Xilinx True Dual Port RAM, No Change, Dual Clock
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// This code implements a parameterizable true dual port memory (both ports can read and write).
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// This is a no change RAM which retains the last read value on the output during writes
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// which is the most power efficient mode.
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// If a reset or enable is not necessary, it may be tied off or removed from the code.
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//module xilinx_true_dual_port_no_change_2_clock_ram #(
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module bram #(
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parameter RAM_WIDTH = 18, // Specify RAM data width
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parameter RAM_DEPTH = 1024, // Specify RAM depth (number of entries)
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parameter RAM_PERFORMANCE = "HIGH_PERFORMANCE", // Select "HIGH_PERFORMANCE" or "LOW_LATENCY"
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parameter INIT_FILE = "" // Specify name/location of RAM initialization file if using one (leave blank if not)
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) (
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input [clogb2(RAM_DEPTH-1)-1:0] addra, // Port A address bus, width determined from RAM_DEPTH
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input [clogb2(RAM_DEPTH-1)-1:0] addrb, // Port B address bus, width determined from RAM_DEPTH
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input [RAM_WIDTH-1:0] dina, // Port A RAM input data
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input [RAM_WIDTH-1:0] dinb, // Port B RAM input data
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input clka, // Port A clock
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input clkb, // Port B clock
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input wea, // Port A write enable
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input web, // Port B write enable
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input ena, // Port A RAM Enable, for additional power savings, disable port when not in use
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input enb, // Port B RAM Enable, for additional power savings, disable port when not in use
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input rsta, // Port A output reset (does not affect memory contents)
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input rstb, // Port B output reset (does not affect memory contents)
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input regcea, // Port A output register enable
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input regceb, // Port B output register enable
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output [RAM_WIDTH-1:0] douta, // Port A RAM output data
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output [RAM_WIDTH-1:0] doutb // Port B RAM output data
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);
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reg [RAM_WIDTH-1:0] BRAM [RAM_DEPTH-1:0];
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reg [RAM_WIDTH-1:0] ram_data_a = {RAM_WIDTH{1'b0}};
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reg [RAM_WIDTH-1:0] ram_data_b = {RAM_WIDTH{1'b0}};
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// The following code either initializes the memory values to a specified file or to all zeros to match hardware
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generate
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if (INIT_FILE != "") begin: use_init_file
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initial
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$readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH-1);
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end else begin: init_bram_to_zero
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integer ram_index;
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initial
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for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
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BRAM[ram_index] = {RAM_WIDTH{1'b0}};
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end
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endgenerate
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always @(posedge clka)
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if (ena)
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if (wea)
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BRAM[addra] <= dina;
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else
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ram_data_a <= BRAM[addra];
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always @(posedge clkb)
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if (enb)
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if (web)
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BRAM[addrb] <= dinb;
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else
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ram_data_b <= BRAM[addrb];
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// The following code generates HIGH_PERFORMANCE (use output register) or LOW_LATENCY (no output register)
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generate
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if (RAM_PERFORMANCE == "LOW_LATENCY") begin: no_output_register
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// The following is a 1 clock cycle read latency at the cost of a longer clock-to-out timing
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assign douta = ram_data_a;
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assign doutb = ram_data_b;
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end else begin: output_register
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// The following is a 2 clock cycle read latency with improve clock-to-out timing
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reg [RAM_WIDTH-1:0] douta_reg = {RAM_WIDTH{1'b0}};
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reg [RAM_WIDTH-1:0] doutb_reg = {RAM_WIDTH{1'b0}};
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always @(posedge clka)
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if (rsta)
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douta_reg <= {RAM_WIDTH{1'b0}};
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else if (regcea)
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douta_reg <= ram_data_a;
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always @(posedge clkb)
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if (rstb)
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doutb_reg <= {RAM_WIDTH{1'b0}};
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else if (regceb)
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doutb_reg <= ram_data_b;
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assign douta = douta_reg;
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assign doutb = doutb_reg;
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end
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endgenerate
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// The following function calculates the address width based on specified RAM depth
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function integer clogb2;
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input integer depth;
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for (clogb2=0; depth>0; clogb2=clogb2+1)
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depth = depth >> 1;
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endfunction
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endmodule
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// The following is an instantiation template for xilinx_true_dual_port_no_change_2_clock_ram
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/*
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// Xilinx True Dual Port RAM, No Change, Dual Clock
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xilinx_true_dual_port_no_change_2_clock_ram #(
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.RAM_WIDTH(18), // Specify RAM data width
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.RAM_DEPTH(1024), // Specify RAM depth (number of entries)
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.RAM_PERFORMANCE("HIGH_PERFORMANCE"), // Select "HIGH_PERFORMANCE" or "LOW_LATENCY"
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.INIT_FILE("") // Specify name/location of RAM initialization file if using one (leave blank if not)
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) your_instance_name (
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.addra(addra), // Port A address bus, width determined from RAM_DEPTH
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.addrb(addrb), // Port B address bus, width determined from RAM_DEPTH
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.dina(dina), // Port A RAM input data, width determined from RAM_WIDTH
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.dinb(dinb), // Port B RAM input data, width determined from RAM_WIDTH
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.clka(clka), // Port A clock
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.clkb(clkb), // Port B clock
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.wea(wea), // Port A write enable
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.web(web), // Port B write enable
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.ena(ena), // Port A RAM Enable, for additional power savings, disable port when not in use
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.enb(enb), // Port B RAM Enable, for additional power savings, disable port when not in use
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.rsta(rsta), // Port A output reset (does not affect memory contents)
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.rstb(rstb), // Port B output reset (does not affect memory contents)
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.regcea(regcea), // Port A output register enable
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.regceb(regceb), // Port B output register enable
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.douta(douta), // Port A RAM output data, width determined from RAM_WIDTH
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.doutb(doutb) // Port B RAM output data, width determined from RAM_WIDTH
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);
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*/
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@ -0,0 +1,166 @@
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// Xilinx UltraRAM True Dual Port Mode. This code implements
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// a parameterizable UltraRAM block with write/read on both ports in
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// No change behavior on both the ports . The behavior of this RAM is
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// when data is written, the output of RAM is unchanged w.r.t each port.
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// Only when write is inactive data corresponding to the address is
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// presented on the output port.
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//
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//module xilinx_ultraram_true_dual_port #(
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module uram #(
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parameter AWIDTH = 12, // Address Width
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parameter DWIDTH = 72, // Data Width
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parameter NBPIPE = 3 // Number of pipeline Registers
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) (
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input clk, // Clock
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// Port A
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input rsta, // Reset
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input wea, // Write Enable
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input regcea, // Output Register Enable
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input mem_ena, // Memory Enable
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input [DWIDTH-1:0] dina, // Data Input
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input [AWIDTH-1:0] addra, // Address Input
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output reg [DWIDTH-1:0] douta,// Data Output
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// Port B
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input rstb, // Reset
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input web, // Write Enable
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input regceb, // Output Register Enable
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input mem_enb, // Memory Enable
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input [DWIDTH-1:0] dinb, // Data Input
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input [AWIDTH-1:0] addrb, // Address Input
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output reg [DWIDTH-1:0] doutb // Data Output
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);
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(* ram_style = "ultra" *)
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reg [DWIDTH-1:0] mem[(1<<AWIDTH)-1:0]; // Memory Declaration
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reg [DWIDTH-1:0] memrega;
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reg [DWIDTH-1:0] mem_pipe_rega[NBPIPE-1:0]; // Pipelines for memory
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reg mem_en_pipe_rega[NBPIPE:0]; // Pipelines for memory enable
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reg [DWIDTH-1:0] memregb;
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reg [DWIDTH-1:0] mem_pipe_regb[NBPIPE-1:0]; // Pipelines for memory
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reg mem_en_pipe_regb[NBPIPE:0]; // Pipelines for memory enable
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integer i;
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// RAM : Read has one latency, Write has one latency as well.
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always @ (posedge clk)
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begin
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if(mem_ena)
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begin
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if(wea)
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mem[addra] <= dina;
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else
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memrega <= mem[addra];
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end
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end
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// The enable of the RAM goes through a pipeline to produce a
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// series of pipelined enable signals required to control the data
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// pipeline.
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always @ (posedge clk)
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begin
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mem_en_pipe_rega[0] <= mem_ena;
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for (i=0; i<NBPIPE; i=i+1)
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mem_en_pipe_rega[i+1] <= mem_en_pipe_rega[i];
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end
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// RAM output data goes through a pipeline.
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always @ (posedge clk)
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begin
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if (mem_en_pipe_rega[0])
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mem_pipe_rega[0] <= memrega;
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end
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always @ (posedge clk)
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begin
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for (i = 0; i < NBPIPE-1; i = i+1)
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if (mem_en_pipe_rega[i+1])
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mem_pipe_rega[i+1] <= mem_pipe_rega[i];
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end
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// Final output register gives user the option to add a reset and
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// an additional enable signal just for the data ouptut
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always @ (posedge clk)
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begin
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if (rsta)
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douta <= 0;
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else if (mem_en_pipe_rega[NBPIPE] && regcea)
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douta <= mem_pipe_rega[NBPIPE-1];
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end
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// RAM : Read has one latency, Write has one latency as well.
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always @ (posedge clk)
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begin
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if(mem_enb)
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begin
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if(web)
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mem[addrb] <= dinb;
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else
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memregb <= mem[addrb];
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end
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end
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// The enable of the RAM goes through a pipeline to produce a
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// series of pipelined enable signals required to control the data
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// pipeline.
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always @ (posedge clk)
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begin
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mem_en_pipe_regb[0] <= mem_enb;
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for (i=0; i<NBPIPE; i=i+1)
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mem_en_pipe_regb[i+1] <= mem_en_pipe_regb[i];
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end
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// RAM output data goes through a pipeline.
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always @ (posedge clk)
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begin
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if (mem_en_pipe_regb[0])
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mem_pipe_regb[0] <= memregb;
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end
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always @ (posedge clk)
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begin
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for (i = 0; i < NBPIPE-1; i = i+1)
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if (mem_en_pipe_regb[i+1])
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mem_pipe_regb[i+1] <= mem_pipe_regb[i];
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end
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// Final output register gives user the option to add a reset and
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// an additional enable signal just for the data ouptut
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always @ (posedge clk)
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begin
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if (rsta)
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doutb <= 0;
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else if (mem_en_pipe_regb[NBPIPE] && regceb)
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doutb <= mem_pipe_regb[NBPIPE-1];
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end
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endmodule
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/*
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// The following is an instantation template for
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// xilinx_ultraram_true_dual_port
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xilinx_ultraram_true_dual_port # (
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.AWIDTH(AWIDTH),
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.DWIDTH(DWIDTH),
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.NBPIPE(NBPIPE)
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)
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your_instance_name (
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clk(clk),
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rsta(rsta),
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wea(wea),
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regcea(regcea),
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mem_ena(mem_ena),
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dina(dina),
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addra(addra),
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douta(douta),
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rstb(rstb),
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web(web),
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regceb(regceb),
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mem_enb(mem_enb),
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dinb(dinb),
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addrb(addrb),
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doutb(doutb)
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);
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*/
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