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zcash-fpga
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updates to AWS files

This commit is contained in:
ben devlin 2019-04-21 11:32:58 -04:00
parent ebcbd00fa5
commit 246ec4c7d3
7 changed files with 80 additions and 61 deletions
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11
aws/zcash_fpga/design/zcash_aws_wrapper.sv
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@ -26,8 +26,13 @@ module zcash_aws_wrapper (
if_axi_stream.source tx_zcash_if
);
logic [7:0] tx_aws_if_keep, tx_zcash_if_keep;
logic [7:0] rx_zcash_if_keep, tx_zcash_if_keep;
logic [63:0] tx_aws_if_keep, rx_aws_if_keep;
always_comb begin
rx_zcash_if_keep = rx_zcash_if.get_keep_from_mod();
rx_aws_if_keep = rx_aws_if.get_keep_from_mod();
tx_aws_if.set_mod_from_keep( tx_aws_if_keep );
tx_zcash_if.set_mod_from_keep( tx_zcash_if_keep );
end
@ -39,7 +44,7 @@ axis_dwidth_converter_8_to_64 converter_8_to_64 (
.s_axis_tready(rx_zcash_if.rdy),
.s_axis_tdata(rx_zcash_if.dat),
.s_axis_tlast(rx_zcash_if.eop),
.s_axis_tkeep(rx_zcash_if.get_keep_from_mod()),
.s_axis_tkeep(rx_zcash_if_keep),
.m_axis_tvalid(tx_aws_if.val),
.m_axis_tready(tx_aws_if.rdy),
.m_axis_tdata(tx_aws_if.dat),
@ -54,7 +59,7 @@ axis_dwidth_converter_64_to_8 converter_64_to_8 (
.s_axis_tready(rx_aws_if.rdy),
.s_axis_tdata(rx_aws_if.dat),
.s_axis_tlast(rx_aws_if.eop),
.s_axis_tkeep(rx_aws_if.get_keep_from_mod()),
.s_axis_tkeep(rx_aws_if_keep),
.m_axis_tvalid(tx_zcash_if.val),
.m_axis_tready(tx_zcash_if.rdy),
.m_axis_tdata(tx_zcash_if.dat),

26
aws/zcash_fpga/design/cl_sde.sv → aws/zcash_fpga/design/zcash_cl_sde.sv
View File

@ -17,7 +17,7 @@
// CL Streaming
module cl_sde
module zcash_cl_sde
(
`include "cl_ports.vh"
@ -262,15 +262,19 @@ if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(1)) zcash_if_tx (clk_if);
if_axi_stream #(.DAT_BYTS(64), .CTL_BITS(1)) aws_if_rx (clk_if);
if_axi_stream #(.DAT_BYTS(64), .CTL_BITS(1)) aws_if_tx (clk_if);
logic [63:0] aws_if_rx_keep;
always_comb begin
aws_if_tx.dat = h2c_axis_data;
aws_if_tx.val = h2c_axis_valid && cfg_wire_zcash_enb;
aws_if_tx.eop = h2c_axis_last;
aws_if_tx.sop = 0;
aws_if_tx.err = 0;
aws_if_tx.ctl = 0;
aws_if_tx.set_mod_from_keep(h2c_axis_keep);
aws_if_rx.rdy = c2h_axis_ready;
aws_if_rx_keep = aws_if_rx.get_keep_from_mod();
end
zcash_aws_wrapper zcash_aws_wrapper (
@ -776,15 +780,15 @@ cl_sde_srm CL_SDE_SRM (
);
//Mux between RTL and BFM stream blocks
assign h2c_axis_ready = cfg_wire_zcash_enb ? aws_if_tx.rdy : cfg_sde_wire_loopback ? c2h_axis_ready : (use_stream_bfm)? bfm_h2c_axis_ready: srm_h2c_axis_ready;
//Mux between RTL and BFM stream blocks
assign h2c_axis_ready = cfg_wire_zcash_enb ? aws_if_tx.rdy : cfg_sde_wire_loopback ? c2h_axis_ready : (use_stream_bfm)? bfm_h2c_axis_ready: srm_h2c_axis_ready;
assign c2h_axis_valid = cfg_wire_zcash_enb ? aws_if_rx.val : cfg_sde_wire_loopback ? h2c_axis_valid : (use_stream_bfm)? bfm_c2h_axis_valid: srm_c2h_axis_valid;
assign c2h_axis_data = cfg_wire_zcash_enb ? aws_if_rx.dat : cfg_sde_wire_loopback ? h2c_axis_data : (use_stream_bfm)? bfm_c2h_axis_data: srm_c2h_axis_data;
assign c2h_axis_keep = cfg_wire_zcash_enb ? aws_if_rx.get_keep_from_mod() : cfg_sde_wire_loopback ? h2c_axis_keep : (use_stream_bfm)? bfm_c2h_axis_keep: srm_c2h_axis_keep;
assign c2h_axis_user = cfg_wire_zcash_enb ? 64'd0 : cfg_sde_wire_loopback ? h2c_axis_user : (use_stream_bfm)? bfm_c2h_axis_user: srm_c2h_axis_user;
assign c2h_axis_last = cfg_wire_zcash_enb ? aws_if_rx.eop : cfg_sde_wire_loopback ? h2c_axis_last : (use_stream_bfm)? bfm_c2h_axis_last: srm_c2h_axis_last;
assign c2h_axis_keep = cfg_wire_zcash_enb ? aws_if_rx_keep : cfg_sde_wire_loopback ? h2c_axis_keep : (use_stream_bfm)? bfm_c2h_axis_keep: srm_c2h_axis_keep;
assign c2h_axis_user = cfg_wire_zcash_enb ? 64'd0 : cfg_sde_wire_loopback ? h2c_axis_user : (use_stream_bfm)? bfm_c2h_axis_user: srm_c2h_axis_user;
assign c2h_axis_last = cfg_wire_zcash_enb ? aws_if_rx.eop : cfg_sde_wire_loopback ? h2c_axis_last : (use_stream_bfm)? bfm_c2h_axis_last: srm_c2h_axis_last;
//-------------------------------------
// OCL AXI-L Handling (CSRs)
@ -882,7 +886,7 @@ logic cfg_srm_dec;
logic [31:0] tst_cfg_rdata;
logic[31:0] cfg_ctl_reg[4:0] = '{default:'0};
logic[31:0] cfg_ctl_reg[3:0] = '{default:'0};
always @(posedge clk_main_a0)
if (!rst_main_n_sync_mid_slr) begin
@ -967,7 +971,7 @@ always @(posedge clk_main_a0)
rdata <= (cfg_srm_dec)? srm_cfg_rdata:
cfg_chk_dec ? chk_cfg_rdata :
cfg_tst_dec ? tst_cfg_rdata :
cfg_ctl_reg[araddr_q[4:2]];
cfg_ctl_reg[araddr_q[3:2]];
end
// assign rd_done = (rd_req && !cfg_srm_dec) || (rd_req_lvl && srm_cfg_ack);
@ -1000,7 +1004,7 @@ assign cfg_tst_wdata = wdata_q;
//5 general purpose control registers
always @(posedge clk_main_a0)
if (wr_req && (wr_addr[15:0] >= 16'h2000) && (wr_addr[15:0]<=16'h2ffc))
cfg_ctl_reg[wr_addr[4:2]] <= wdata_q;
cfg_ctl_reg[wr_addr[3:2]] <= wdata_q;
logic cfg_atg_en;
@ -1008,7 +1012,7 @@ always @(posedge clk_main_a0)
assign cfg_sde_wire_loopback = cfg_ctl_reg[0][1];
assign cfg_arid_inc_mode = cfg_ctl_reg[0][2];
assign cfg_atg_en = cfg_ctl_reg[0][3];
assign cfg_wire_zcash_enb = cfg_ctl_reg[0][4];
assign cfg_wire_zcash_enb = cfg_ctl_reg[2][0];
`ifdef CL_SDE_AXI_PROT_CHK

2
aws/zcash_fpga/verif/scripts/Makefile.vivado
View File

@ -25,5 +25,5 @@ compile:
run:
cd $(SIM_DIR) && xsim -R -log $(TEST).log $(PLUSARGS) -tclbatch $(SCRIPTS_DIR)/waves.tcl tb
cd $(SIM_DIR) && xsim -R -log $(TEST).log $(PLUSARGS) -tclbatch $(SCRIPTS_DIR)/waves.tcl tb

7
aws/zcash_fpga/verif/scripts/top.vivado.f
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@ -15,7 +15,7 @@
-define VIVADO_SIM
-define CARD_1=card
-define CL_NAME=cl_sde
-define CL_NAME=zcash_cl_sde
-define SIMULATION
-define NO_SDE_DEBUG_ILA
-define DISABLE_VJTAG_DEBUG
@ -108,10 +108,7 @@ ${CL_ROOT}/design/sde_desc.sv
${CL_ROOT}/design/sde.sv
${HDK_COMMON_DIR}/verif/models/base/gen_buf_t.sv
${HDK_COMMON_DIR}/verif/models/stream_bfm/stream_bfm.sv
${CL_ROOT}/design/cl_sde.sv
${CL_ROOT}/ip/axis_data_fifo_8/sim/axis_data_fifo_8.v
${CL_ROOT}/ip/axis_data_fifo_8/hdl/axis_data_fifo_v2_0_vl_rfs.v
${CL_ROOT}/design/zcash_cl_sde.sv
${CL_ROOT}/ip/axis_dwidth_converter_64_to_8/sim/axis_dwidth_converter_64_to_8.v
${CL_ROOT}/ip/axis_dwidth_converter_64_to_8/hdl/axis_dwidth_converter_v1_1_vl_rfs.v

19
aws/zcash_fpga/verif/scripts/waves.tcl
View File

@ -14,20 +14,21 @@
# limitations under the License.
set curr_wave [current_wave_config]
#if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wav#e window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
#}
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wav#e window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
add_wave /tb/card/fpga/CL/*
add_wave /tb/card/fpga/CL/CL_SDE_SRM/*
add_wave /tb/card/fpga/CL/zcash_if_rx/*
add_wave /tb/card/fpga/CL/zcash_if_tx/*
add_wave /tb/card/fpga/CL/aws_if_rx/*
add_wave /tb/card/fpga/CL/aws_if_tx/*
run 200 us
quit

63
aws/zcash_fpga/verif/tests/test_status_request.sv
View File

@ -32,6 +32,7 @@ bit desc_type = 0;
int pkt_length = 256; //packet length. Currently is constant, can be variable
gen_buf_t cur_pst_pkt; //Current packet we are posting
gen_buf_t rpl_pkt;
dma_buf_t tmp_buf; //DMA buffer used to post packets (a descriptors worth)
dma_buf_t dbg_buf;
@ -45,6 +46,8 @@ int cur_desc_size; //current descriptor size
int cur_desc_offset; //descriptor offset.
bit desc_eop; //Descriptor EOP bit (current descriptor is last of a packet)
zcash_fpga_pkg::fpga_status_rpl_t fpga_status_rpl;
initial
begin
#10; //Make sure these default override base test.
@ -80,37 +83,49 @@ begin
enable_c2h_auto_check = 1;
sde.c2h_configure();
tb.poke_ocl(.addr(64'h180), .data(32'h0000_0001));
fork : FORK_C2H_SB_THREAD
$display("ENABLING LOOPBACK");
end else begin
// Enble zcash block
enable_c2h_auto_check = 1;
sde.c2h_configure();
$display("ENABLING ZCASH BLOCK");
tb.poke_ocl(.addr(64'h2008), .data(32'h0000_0001));
end
fork : FORK_C2H_SB_THREAD
sde.process_c2h_wb_thread;
sde.post_c2h_desc_thread;
join_none
end
else
//Enable the H2C auto checking
enable_h2c_auto_check = 1;
join_none
//Post the packets (cfg_num_pkts)
for (int i=0; i<cfg_num_pkts; i++)
begin
//Create a new packet to post, and initialize the data. This is just a generic buffer that represents the packet.
cur_pst_pkt = new();
//cur_pst_pkt.init_inc((i<<28 | i<<24 | i<<20 | i<<16), pkt_length );
header.cmd = zcash_fpga_pkg::FPGA_STATUS;
header.len = $bits(header_t)/8;
pkt_length = header.len;
cur_pst_pkt = new();
for (int i = 0; i < header.len; i++) begin
cur_pst_pkt.data.push_back(header[i*8 +: 8]);
end
//If loopback, packet will get back to Host
if (cfg_srm_lb_mode) begin
$display("Loopback was enabled!");
exp_c2h_pkt_q.push_back(cur_pst_pkt);
if (cfg_srm_lb_mode) begin
exp_c2h_pkt_q.push_back(cur_pst_pkt);
end
else begin
//Status reply message
fpga_status_rpl = get_fpga_status_rpl("test", "20180311", 0);
rpl_pkt = new();
for (int i = 0; i < fpga_status_rpl.hdr.len; i++) begin
rpl_pkt.data.push_back(fpga_status_rpl[i*8 +: 8]);
end
exp_c2h_pkt_q.push_back(rpl_pkt);
end
else
//Push the packet onto the expect queue for end of sim checking
exp_h2c_pkt_q.push_back(cur_pst_pkt);
//Create descriptor(s) for the packet
desc_eop = 0;
@ -121,8 +136,8 @@ begin
cur_desc_offset = 7;
//Make descriptor size the page size for simplicity. This is not required, can change this and make variable
//cur_desc_size = sde.page_size;
cur_desc_size = 64;
cur_desc_size = sde.page_size;
//cur_desc_size = 8;
//Make sure desc offset/size is valid, if not reset to offset=0, size=page_size
if ((cur_desc_size + cur_desc_offset) > sde.page_size)
@ -177,19 +192,13 @@ begin
//Wait for all the packets to be received
fork
begin
if (cfg_srm_lb_mode)
wait (c2h_pkts_checked == cfg_num_pkts);
else
wait (h2c_pkts_checked == cfg_num_pkts);
end
begin
wait (c2h_pkts_checked == cfg_num_pkts);
end
begin
dly_clks(1000 * cfg_num_pkts);
if (cfg_srm_lb_mode)
$display($time,,,"test_simple_h2c: ***ERROR*** waiting for RX Stream packets timeout (loopback to is C2H), num_received=0x%x, expected=0x%x", c2h_pkts_checked, cfg_num_pkts);
else
$display($time,,,"test_simple_h2c: ***ERROR*** waiting for RX Stream packets timeout, num_received=0x%x, expected=0x%x", h2c_pkts_checked, cfg_num_pkts);
$finish;
$display($time,,,"test_simple_h2c: ***ERROR*** waiting for RX Stream packets timeout (loopback to is C2H), num_received=0x%x, expected=0x%x", c2h_pkts_checked, cfg_num_pkts);
$finish;
end
join_any
disable fork;

13
ip_cores/common/src/rtl/common_if.sv
View File

@ -38,11 +38,13 @@ interface if_axi_stream # (
logic [DAT_BITS-1:0] dat;
logic [MOD_BITS-1:0] mod;
modport sink (input val, err, sop, eop, ctl, dat, mod, i_clk, output rdy);
modport sink (input val, err, sop, eop, ctl, dat, mod, i_clk, output rdy,
import task get_keep_from_mod());
modport source (output val, err, sop, eop, ctl, dat, mod, input rdy, i_clk,
import task reset_source(),
import task copy_if(dat_, val_, sop_, eop_, err_, mod_, ctl_),
import task copy_if_comb(dat_, val_, sop_, eop_, err_, mod_, ctl_));
import task copy_if_comb(dat_, val_, sop_, eop_, err_, mod_, ctl_),
import task set_mod_from_keep(keep));
// Task to reset a source interface signals to all 0
task reset_source();
@ -81,11 +83,12 @@ interface if_axi_stream # (
function [DAT_BYTS-1:0] get_keep_from_mod();
get_keep_from_mod = 0;
get_keep_from_mod = {DAT_BYTS{1'b0}};
for (int i = 0; i < DAT_BYTS; i++) begin
if (mod == 0 || i <= mod)
if (mod == 0 || i < mod)
get_keep_from_mod[i] = 1;
end
return get_keep_from_mod;
endfunction
// Task used in simulation to drive data on a source interface
@ -238,4 +241,4 @@ interface if_ram # (
d <= 0;
endtask
endinterface
endinterface