Updates to top level
This commit is contained in:
bsdevlin
parent
86a8db4df3
commit
2bee4f7513
Binary file not shown.
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@ -22,6 +22,7 @@ module control_top
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import zcash_fpga_pkg::*, equihash_pkg::*;
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import zcash_fpga_pkg::*, equihash_pkg::*;
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#(
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#(
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parameter IN_DAT_BYTS,
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parameter IN_DAT_BYTS,
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parameter CORE_DAT_BYTS = 8, // Only tested at 8 byte data width
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parameter [63:0] BUILD_HOST = "test",
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parameter [63:0] BUILD_HOST = "test",
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parameter [63:0] BUILD_DATE = "20180311"
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parameter [63:0] BUILD_DATE = "20180311"
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)(
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)(
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@ -39,9 +40,6 @@ module control_top
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input i_equihash_mask_val
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input i_equihash_mask_val
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);
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);
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localparam CORE_DAT_BYTS = 8; // Only tested at 8 byte data width
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localparam IN_DAT_BITS = IN_DAT_BYTS*8;
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localparam IN_DAT_BITS = IN_DAT_BYTS*8;
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localparam CORE_DAT_BITS = CORE_DAT_BYTS*8;
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localparam CORE_DAT_BITS = CORE_DAT_BYTS*8;
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@ -58,8 +56,7 @@ if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BYTS(1)) rx_int1_if (i_clk_core);
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if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BYTS(1)) rx_typ0_if (i_clk_core);
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if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BYTS(1)) rx_typ0_if (i_clk_core);
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if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BYTS(1)) rx_typ1_if (i_clk_core);
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if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BYTS(1)) rx_typ1_if (i_clk_core);
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if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BYTS(1)) tx_typ0_if (i_clk_core);
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if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BYTS(1)) tx_arb_in_if [2] (i_clk_core);
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if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BYTS(1)) tx_typ1_if (i_clk_core);
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if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BYTS(1)) tx_int_if (i_clk_core);
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if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BYTS(1)) tx_int_if (i_clk_core);
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enum {TYP0_IDLE = 0,
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enum {TYP0_IDLE = 0,
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@ -79,6 +76,7 @@ verify_equihash_rpl_t verify_equihash_rpl;
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logic [7:0] typ0_wrd_cnt, typ1_wrd_cnt, reset_cnt;
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logic [7:0] typ0_wrd_cnt, typ1_wrd_cnt, reset_cnt;
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logic [63:0] equihash_index;
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logic [63:0] equihash_index;
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logic equihash_index_val, rx_typ1_if_rdy, verify_equihash_rpl_val;
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logic equihash_index_val, rx_typ1_if_rdy, verify_equihash_rpl_val;
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logic sop_l;
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fpga_state_t fpga_state;
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fpga_state_t fpga_state;
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always_comb begin
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always_comb begin
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@ -87,7 +85,7 @@ always_comb begin
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fpga_state.typ1_state = TYP1_IDLE;
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fpga_state.typ1_state = TYP1_IDLE;
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header = rx_int_if.dat;
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header = rx_int_if.dat;
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header0 = rx_typ0_if.dat;
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header0 = rx_typ0_if.dat;
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header1 = rx_typ0_if.dat;
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header1 = rx_typ1_if.dat;
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end
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end
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// Logic for processing msg_type == 0 messages
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// Logic for processing msg_type == 0 messages
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@ -96,7 +94,7 @@ always_ff @ (posedge i_clk_core) begin
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rx_typ0_if.rdy <= 0;
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rx_typ0_if.rdy <= 0;
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typ0_msg_state <= TYP0_IDLE;
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typ0_msg_state <= TYP0_IDLE;
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header0_l <= 0;
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header0_l <= 0;
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tx_typ0_if.reset_source();
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tx_arb_in_if[0].reset_source();
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fpga_status_rpl <= 0;
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fpga_status_rpl <= 0;
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fpga_reset_rpl <= 0;
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fpga_reset_rpl <= 0;
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typ0_wrd_cnt <= 0;
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typ0_wrd_cnt <= 0;
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@ -132,16 +130,16 @@ always_ff @ (posedge i_clk_core) begin
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end
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end
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TYP0_SEND_STATUS: begin
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TYP0_SEND_STATUS: begin
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rx_typ0_if.rdy <= 0;
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rx_typ0_if.rdy <= 0;
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if (~tx_typ0_if.val || (tx_typ0_if.rdy && tx_typ0_if.val)) begin
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if (~tx_arb_in_if[0].val || (tx_arb_in_if[0].rdy && tx_arb_in_if[0].val)) begin
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tx_typ0_if.dat <= fpga_status_rpl;
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tx_arb_in_if[0].dat <= fpga_status_rpl;
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tx_typ0_if.val <= 1;
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tx_arb_in_if[0].val <= 1;
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tx_typ0_if.sop <= typ0_wrd_cnt == $bits(fpga_status_rpl_t)/8;
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tx_arb_in_if[0].sop <= typ0_wrd_cnt == $bits(fpga_status_rpl_t)/8;
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tx_typ0_if.eop <= typ0_wrd_cnt <= CORE_DAT_BYTS;
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tx_arb_in_if[0].eop <= typ0_wrd_cnt <= CORE_DAT_BYTS;
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tx_typ0_if.mod <= typ0_wrd_cnt < CORE_DAT_BYTS ? typ0_wrd_cnt : 0;
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tx_arb_in_if[0].mod <= typ0_wrd_cnt < CORE_DAT_BYTS ? typ0_wrd_cnt : 0;
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typ0_wrd_cnt <= (typ0_wrd_cnt > CORE_DAT_BYTS) ? (typ0_wrd_cnt - CORE_DAT_BYTS) : 0;
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typ0_wrd_cnt <= (typ0_wrd_cnt > CORE_DAT_BYTS) ? (typ0_wrd_cnt - CORE_DAT_BYTS) : 0;
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fpga_status_rpl <= fpga_status_rpl >> CORE_DAT_BITS;
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fpga_status_rpl <= fpga_status_rpl >> CORE_DAT_BITS;
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if (typ0_wrd_cnt == 0) begin
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if (typ0_wrd_cnt == 0) begin
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tx_typ0_if.val <= 0;
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tx_arb_in_if[0].val <= 0;
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typ0_msg_state <= TYP0_IDLE;
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typ0_msg_state <= TYP0_IDLE;
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end
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end
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end
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end
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@ -154,16 +152,16 @@ always_ff @ (posedge i_clk_core) begin
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reset_cnt <= reset_cnt - 1;
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reset_cnt <= reset_cnt - 1;
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if (~o_usr_rst) begin
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if (~o_usr_rst) begin
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if (~tx_typ0_if.val || (tx_typ0_if.rdy && tx_typ0_if.val)) begin
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if (~tx_arb_in_if[0].val || (tx_arb_in_if[0].rdy && tx_arb_in_if[0].val)) begin
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tx_typ0_if.dat <= fpga_reset_rpl;
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tx_arb_in_if[0].dat <= fpga_reset_rpl;
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tx_typ0_if.val <= 1;
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tx_arb_in_if[0].val <= 1;
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tx_typ0_if.sop <= typ0_wrd_cnt == $bits(fpga_reset_rpl_t)/8;
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tx_arb_in_if[0].sop <= typ0_wrd_cnt == $bits(fpga_reset_rpl_t)/8;
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tx_typ0_if.eop <= typ0_wrd_cnt <= CORE_DAT_BYTS;
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tx_arb_in_if[0].eop <= typ0_wrd_cnt <= CORE_DAT_BYTS;
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tx_typ0_if.mod <= typ0_wrd_cnt < CORE_DAT_BYTS ? typ0_wrd_cnt : 0;
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tx_arb_in_if[0].mod <= typ0_wrd_cnt < CORE_DAT_BYTS ? typ0_wrd_cnt : 0;
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typ0_wrd_cnt <= (typ0_wrd_cnt > CORE_DAT_BYTS) ? (typ0_wrd_cnt - CORE_DAT_BYTS) : 0;
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typ0_wrd_cnt <= (typ0_wrd_cnt > CORE_DAT_BYTS) ? (typ0_wrd_cnt - CORE_DAT_BYTS) : 0;
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fpga_reset_rpl <= fpga_reset_rpl >> CORE_DAT_BITS;
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fpga_reset_rpl <= fpga_reset_rpl >> CORE_DAT_BITS;
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if (typ0_wrd_cnt == 0) begin
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if (typ0_wrd_cnt == 0) begin
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tx_typ0_if.val <= 0;
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tx_arb_in_if[0].val <= 0;
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typ0_msg_state <= TYP0_IDLE;
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typ0_msg_state <= TYP0_IDLE;
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end
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end
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end
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end
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@ -192,18 +190,22 @@ always_ff @ (posedge i_clk_core) begin
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rx_typ1_if_rdy <= 0;
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rx_typ1_if_rdy <= 0;
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typ1_msg_state <= TYP1_IDLE;
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typ1_msg_state <= TYP1_IDLE;
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header1_l <= 0;
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header1_l <= 0;
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tx_typ1_if.reset_source();
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tx_arb_in_if[1].reset_source();
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o_equihash_axi.reset_source();
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o_equihash_axi.reset_source();
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verify_equihash_rpl <= 0;
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verify_equihash_rpl <= 0;
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typ1_wrd_cnt <= 0;
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typ1_wrd_cnt <= 0;
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equihash_index <= 0;
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equihash_index <= 0;
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verify_equihash_rpl_val <= 0;
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verify_equihash_rpl_val <= 0;
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equihash_index_val <= 0;
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sop_l <= 0;
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end else begin
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end else begin
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rx_typ1_if.rdy <= 1;
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rx_typ1_if.rdy <= 1;
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case (typ1_msg_state)
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case (typ1_msg_state)
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TYP1_IDLE: begin
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TYP1_IDLE: begin
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verify_equihash_rpl_val <= 0;
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verify_equihash_rpl_val <= 0;
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equihash_index_val <= 0;
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sop_l <= 0;
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if (rx_typ1_if.val && rx_typ1_if.rdy) begin
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if (rx_typ1_if.val && rx_typ1_if.rdy) begin
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header1_l <= header1;
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header1_l <= header1;
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rx_typ1_if_rdy <= 0;
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rx_typ1_if_rdy <= 0;
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@ -224,33 +226,41 @@ always_ff @ (posedge i_clk_core) begin
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rx_typ1_if_rdy <= 0;
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rx_typ1_if_rdy <= 0;
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if (~equihash_index_val) begin
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if (~equihash_index_val) begin
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if (rx_typ1_if.rdy && rx_typ1_if.val)
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if (rx_typ1_if.rdy && rx_typ1_if.val) begin
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equihash_index <= equihash_index_val;
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equihash_index <= rx_typ1_if.dat;
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equihash_index_val <= 1;
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end
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end else begin
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end else begin
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// First load block data (this might be bypassed if loading from memory)
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// First load block data (this might be bypassed if loading from memory)
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if (~o_equihash_axi.val || (o_equihash_axi.rdy && o_equihash_axi.val)) begin
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if (~o_equihash_axi.val || (o_equihash_axi.rdy && o_equihash_axi.val)) begin
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o_equihash_axi.copy_if(rx_typ1_if.to_struct());
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o_equihash_axi.copy_if(rx_typ1_if.to_struct());
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// First cycle has .sop set
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o_equihash_axi.sop <= ~sop_l;
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if (o_equihash_axi.val) begin
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sop_l <= 1;
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o_equihash_axi.sop <= 0;
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end
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end
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end
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end
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end
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// Wait for reply with result
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// Wait for reply with result
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if (i_equihash_mask_val) begin
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if (i_equihash_mask_val && ~verify_equihash_rpl_val) begin
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verify_equihash_rpl <= get_verify_equihash_rpl(i_equihash_mask, equihash_index);
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verify_equihash_rpl <= get_verify_equihash_rpl(i_equihash_mask, equihash_index);
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verify_equihash_rpl_val <= 1;
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verify_equihash_rpl_val <= 1;
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end
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end
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// Send result
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// Send result
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if (verify_equihash_rpl_val) begin
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if (verify_equihash_rpl_val) begin
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if (~tx_typ1_if.val || (tx_typ1_if.rdy && tx_typ1_if.val)) begin
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if (~tx_arb_in_if[1].val || (tx_arb_in_if[1].rdy && tx_arb_in_if[1].val)) begin
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tx_typ1_if.dat <= verify_equihash_rpl;
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tx_arb_in_if[1].dat <= verify_equihash_rpl;
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tx_typ1_if.val <= 1;
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tx_arb_in_if[1].val <= 1;
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tx_typ1_if.sop <= typ1_wrd_cnt == $bits(verify_equihash_rpl_t)/8;
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tx_arb_in_if[1].sop <= typ1_wrd_cnt == $bits(verify_equihash_rpl_t)/8;
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tx_typ1_if.eop <= typ1_wrd_cnt <= CORE_DAT_BYTS;
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tx_arb_in_if[1].eop <= typ1_wrd_cnt <= CORE_DAT_BYTS;
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tx_typ1_if.mod <= typ1_wrd_cnt < CORE_DAT_BYTS ? typ1_wrd_cnt : 0;
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tx_arb_in_if[1].mod <= typ1_wrd_cnt < CORE_DAT_BYTS ? typ1_wrd_cnt : 0;
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typ1_wrd_cnt <= (typ1_wrd_cnt > CORE_DAT_BYTS) ? (typ1_wrd_cnt - CORE_DAT_BYTS) : 0;
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typ1_wrd_cnt <= (typ1_wrd_cnt > CORE_DAT_BYTS) ? (typ1_wrd_cnt - CORE_DAT_BYTS) : 0;
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verify_equihash_rpl <= verify_equihash_rpl >> CORE_DAT_BITS;
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verify_equihash_rpl <= verify_equihash_rpl >> CORE_DAT_BITS;
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if (typ1_wrd_cnt == 0) begin
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if (typ1_wrd_cnt == 0) begin
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tx_typ1_if.val <= 0;
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tx_arb_in_if[1].val <= 0;
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typ1_msg_state <= TYP1_IDLE;
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typ1_msg_state <= TYP1_IDLE;
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end
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end
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end
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end
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@ -268,14 +278,14 @@ end
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// Logic to mux the packet depending on its command type
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// Logic to mux the packet depending on its command type
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logic msg_type, msg_type_l;
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logic msg_type, msg_type_l;
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always_comb begin
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always_comb begin
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rx_int0_if.copy_if(rx_int_if.to_struct());
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rx_int0_if.copy_if_comb(rx_int_if.to_struct());
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rx_int1_if.copy_if(rx_int_if.to_struct());
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rx_int1_if.copy_if_comb(rx_int_if.to_struct());
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rx_int0_if.val = 0;
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rx_int0_if.val = 0;
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rx_int1_if.val = 0;
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rx_int1_if.val = 0;
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rx_int_if.rdy = 0;
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rx_int_if.rdy = 0;
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if (rx_int_if.sop && rx_int_if.val && rx_int_if.rdy) begin
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if (rx_int_if.sop && rx_int_if.val) begin
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if(header.cmd[8 +: 8] == 8'd0) begin
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if(header.cmd[8 +: 8] == 8'd0) begin
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msg_type = 0;
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msg_type = 0;
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rx_int0_if.val = rx_int_if.val;
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rx_int0_if.val = rx_int_if.val;
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@ -288,7 +298,7 @@ always_comb begin
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end else begin
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end else begin
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rx_int0_if.val = rx_int_if.val && (msg_type_l == 0);
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rx_int0_if.val = rx_int_if.val && (msg_type_l == 0);
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rx_int1_if.val = rx_int_if.val && (msg_type_l == 1);
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rx_int1_if.val = rx_int_if.val && (msg_type_l == 1);
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rx_int_if.rdy = msg_type_l == 0 ? rx_int0_if.rdy : rx_int1_if.rdy;
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rx_int_if.rdy = (msg_type_l == 0) ? rx_int0_if.rdy : rx_int1_if.rdy;
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msg_type = msg_type_l;
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msg_type = msg_type_l;
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end
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end
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end
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end
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@ -352,7 +362,7 @@ packet_arb_tx (
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.i_clk ( i_clk_core ),
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.i_clk ( i_clk_core ),
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.i_rst ( i_rst_core || o_usr_rst ),
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.i_rst ( i_rst_core || o_usr_rst ),
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.i_axi ({tx_typ1_if, tx_typ0_if}),
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.i_axi ( tx_arb_in_if ),
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.o_axi ( tx_int_if )
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.o_axi ( tx_int_if )
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);
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);
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@ -52,9 +52,9 @@ logic [N-1:0] sol_hash_xor, equihash_sol_string, equihash_sol
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logic [$clog2(SOL_LIST_LEN)-1:0] sol_cnt_out, sol_cnt_in; // This tracks how many solutions we have XORed
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logic [$clog2(SOL_LIST_LEN)-1:0] sol_cnt_out, sol_cnt_in; // This tracks how many solutions we have XORed
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logic [$clog2(2*DAT_BITS)-1:0] sol_pos; // This tracks the pos in our DAT_BITS RAM output
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logic [$clog2(2*DAT_BITS)-1:0] sol_pos; // This tracks the pos in our DAT_BITS RAM output
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logic [64*8-1:0] parameters;
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logic [64*8-1:0] parameters;
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//TODO tmep
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if_axi_stream #(.DAT_BYTS(BLAKE2B_DIGEST_BYTS), .CTL_BYTS($clog2(INDICIES_PER_HASH))) blake2b_out_hash(i_clk);
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if_axi_stream #(.DAT_BYTS(BLAKE2B_DIGEST_BYTS), .CTL_BYTS(4)) blake2b_out_hash(i_clk);
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if_axi_stream #(.DAT_BYTS(EQUIHASH_GEN_BYTS), .CTL_BYTS($clog2(INDICIES_PER_HASH))) blake2b_in_hash(i_clk);
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if_axi_stream #(.DAT_BYTS(EQUIHASH_GEN_BYTS), .CTL_BYTS(4)) blake2b_in_hash(i_clk);
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if_axi_stream #(.DAT_BYTS(DAT_BYTS)) difficulty_if_in(i_clk);
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if_axi_stream #(.DAT_BYTS(DAT_BYTS)) difficulty_if_in(i_clk);
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@ -106,7 +106,7 @@ always_ff @ (posedge i_clk) begin
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ram_wr_state <= STATE_WR_IDLE;
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ram_wr_state <= STATE_WR_IDLE;
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end else begin
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end else begin
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// Defaults
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// Defaults
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equihash_sol_bram_if_a.we <= 1;
|
equihash_sol_bram_if_a.we <= i_axi.val;
|
||||||
equihash_sol_bram_if_a.en <= 1;
|
equihash_sol_bram_if_a.en <= 1;
|
||||||
equihash_sol_bram_if_a.d <= i_axi.dat;
|
equihash_sol_bram_if_a.d <= i_axi.dat;
|
||||||
|
|
||||||
|
|
@ -178,8 +178,12 @@ always_ff @ (posedge i_clk) begin
|
||||||
equihash_order_if.val <= 0;
|
equihash_order_if.val <= 0;
|
||||||
|
|
||||||
equihash_sol_bram_read <= equihash_sol_bram_read << 1;
|
equihash_sol_bram_read <= equihash_sol_bram_read << 1;
|
||||||
if (equihash_sol_bram_read[0])
|
if (equihash_sol_bram_read[0]) begin
|
||||||
equihash_sol_bram_if_b_l <= equihash_sol_bram_if_b.q;
|
equihash_sol_bram_if_b_l <= equihash_sol_bram_if_b.q;
|
||||||
|
// If nothign else changes sol_pos, we need to shfit it here too
|
||||||
|
//if ((equihash_sol_bram_if_a.a*DAT_BYTS) < ((equihash_sol_bram_if_b.a+1)*DAT_BYTS + $bits(cblockheader_t)/DAT_BITS))
|
||||||
|
sol_pos <= sol_pos - DAT_BITS;
|
||||||
|
end
|
||||||
|
|
||||||
case(ram_rd_state)
|
case(ram_rd_state)
|
||||||
STATE_RD_IDLE: begin
|
STATE_RD_IDLE: begin
|
||||||
|
|
@ -211,10 +215,10 @@ always_ff @ (posedge i_clk) begin
|
||||||
equihash_gen_in.nonce <= cblockheader.nonce;
|
equihash_gen_in.nonce <= cblockheader.nonce;
|
||||||
equihash_gen_in.index <= (equihash_sol_index)/INDICIES_PER_HASH;
|
equihash_gen_in.index <= (equihash_sol_index)/INDICIES_PER_HASH;
|
||||||
blake2b_in_hash.ctl <= (equihash_sol_index) % INDICIES_PER_HASH;
|
blake2b_in_hash.ctl <= (equihash_sol_index) % INDICIES_PER_HASH;
|
||||||
|
blake2b_in_hash.ctl[8 +: 24] <= equihash_sol_index;
|
||||||
|
|
||||||
// Stay 2 clocks behind the RAM write
|
// Stay 2 clocks behind the RAM write
|
||||||
if ((equihash_sol_bram_if_a.a*DAT_BYTS + DAT_BYTS) >= (equihash_sol_bram_if_b.a + $bits(cblockheader_t)/DAT_BITS) ||
|
if ((equihash_sol_bram_if_a.a*DAT_BYTS) >= ((equihash_sol_bram_if_b.a+1)*DAT_BYTS + $bits(cblockheader_t)/DAT_BITS) ||
|
||||||
ram_wr_state == STATE_WR_WAIT) begin
|
ram_wr_state == STATE_WR_WAIT) begin
|
||||||
// Check if we need to load next memory address
|
// Check if we need to load next memory address
|
||||||
if ((sol_pos + 3*SOL_BITS >= 2*DAT_BITS) && ~|equihash_sol_bram_read) begin
|
if ((sol_pos + 3*SOL_BITS >= 2*DAT_BITS) && ~|equihash_sol_bram_read) begin
|
||||||
|
|
@ -237,10 +241,17 @@ always_ff @ (posedge i_clk) begin
|
||||||
equihash_order_if.eop <= (sol_cnt_in == SOL_LIST_LEN - 1);
|
equihash_order_if.eop <= (sol_cnt_in == SOL_LIST_LEN - 1);
|
||||||
|
|
||||||
// If our input is about to shift we need to adjust pointer by DAT_BITS
|
// If our input is about to shift we need to adjust pointer by DAT_BITS
|
||||||
sol_pos <= sol_pos + SOL_BITS - (equihash_sol_bram_read[0] ? DAT_BITS : 0);
|
//sol_pos <= sol_pos + SOL_BITS - (equihash_sol_bram_read[0] ? DAT_BITS : 0);
|
||||||
if (sol_cnt_in == SOL_LIST_LEN - 1)
|
|
||||||
|
sol_pos <= sol_pos + SOL_BITS - (sol_pos + 2*SOL_BITS >= 2*DAT_BITS ? DAT_BITS : 0);
|
||||||
|
|
||||||
|
if (sol_cnt_in == SOL_LIST_LEN - 1) begin
|
||||||
ram_rd_state <= STATE_RD_WAIT;
|
ram_rd_state <= STATE_RD_WAIT;
|
||||||
end
|
end
|
||||||
|
end else begin
|
||||||
|
// Hold some values steady
|
||||||
|
// equihash_sol_bram_read <= equihash_sol_bram_read;
|
||||||
|
end
|
||||||
end
|
end
|
||||||
STATE_RD_WAIT: begin
|
STATE_RD_WAIT: begin
|
||||||
if (chk_state == STATE_CHK_DONE) begin
|
if (chk_state == STATE_CHK_DONE) begin
|
||||||
|
|
@ -314,13 +325,16 @@ always_ff @ (posedge i_clk) begin
|
||||||
|
|
||||||
// We also check the order is correct
|
// We also check the order is correct
|
||||||
o_mask.BAD_ZERO_ORDER <= bad_order_check(sol_hash_xor, sol_cnt_out) | o_mask.BAD_ZERO_ORDER;
|
o_mask.BAD_ZERO_ORDER <= bad_order_check(sol_hash_xor, sol_cnt_out) | o_mask.BAD_ZERO_ORDER;
|
||||||
end
|
|
||||||
|
|
||||||
if (sol_cnt_out == SOL_LIST_LEN - 1) begin
|
if (sol_cnt_out == SOL_LIST_LEN - 1) begin
|
||||||
chk_state <= STATE_CHK_WAIT;
|
chk_state <= STATE_CHK_WAIT;
|
||||||
end
|
end
|
||||||
|
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
end
|
||||||
STATE_CHK_WAIT: begin
|
STATE_CHK_WAIT: begin
|
||||||
o_mask.XOR_NON_ZERO <= |sol_hash_xor;
|
o_mask.XOR_NON_ZERO <= |sol_hash_xor;
|
||||||
xor_check_done <= 1;
|
xor_check_done <= 1;
|
||||||
|
|
@ -352,7 +366,7 @@ always_comb begin
|
||||||
|
|
||||||
// We have to select what part of Blake2b output to sleect
|
// We have to select what part of Blake2b output to sleect
|
||||||
// and then re-order the bytes so the XOR zeros grow from the left
|
// and then re-order the bytes so the XOR zeros grow from the left
|
||||||
equihash_sol_string = blake2b_out_hash.dat[N*blake2b_out_hash.ctl +: N];
|
equihash_sol_string = blake2b_out_hash.dat[N*blake2b_out_hash.ctl[0] +: N];
|
||||||
for (int i = 0; i < N/8; i++)
|
for (int i = 0; i < N/8; i++)
|
||||||
equihash_sol_string_flip[i*8 +: 8] = equihash_sol_string[N - 8 -i*8 +: 8];
|
equihash_sol_string_flip[i*8 +: 8] = equihash_sol_string[N - 8 -i*8 +: 8];
|
||||||
|
|
||||||
|
|
@ -415,7 +429,7 @@ localparam [EQUIHASH_GEN_BYTS*8-1:0] EQUIHASH_GEN_BYTS_BM = {
|
||||||
blake2b_pipe_top #(
|
blake2b_pipe_top #(
|
||||||
.MSG_LEN ( EQUIHASH_GEN_BYTS ),
|
.MSG_LEN ( EQUIHASH_GEN_BYTS ),
|
||||||
.MSG_VAR_BM ( EQUIHASH_GEN_BYTS_BM ),
|
.MSG_VAR_BM ( EQUIHASH_GEN_BYTS_BM ),
|
||||||
.CTL_BITS ( $clog2(INDICIES_PER_HASH) )
|
.CTL_BITS ( 32 )
|
||||||
)
|
)
|
||||||
blake2b_pipe_top_i (
|
blake2b_pipe_top_i (
|
||||||
.i_clk ( i_clk ),
|
.i_clk ( i_clk ),
|
||||||
|
|
|
||||||
|
|
@ -21,41 +21,66 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
module zcash_fpga_top
|
module zcash_fpga_top
|
||||||
import zcash_verif_pkg::*;
|
import zcash_fpga_pkg::*, equihash_pkg::*;
|
||||||
#(
|
#(
|
||||||
parameter DAT_BYTS = 8
|
parameter IF_DAT_BYTS = 2,
|
||||||
|
parameter CORE_DAT_BYTS = 8 // Only tested at 8 byte data width
|
||||||
)(
|
)(
|
||||||
// Clocks and resets
|
// Clocks and resets
|
||||||
|
input i_clk_200, i_rst_200,
|
||||||
|
input i_clk_300, i_rst_300,
|
||||||
|
input i_clk_if, i_rst_if,
|
||||||
|
|
||||||
input i_clk_100, i_rst_100,
|
// Interface input and output
|
||||||
|
|
||||||
// Interface inputs and outputs
|
|
||||||
// UART
|
// UART
|
||||||
if_axi_stream.sink uart_if_rx,
|
if_axi_stream.sink rx_if,
|
||||||
if_axi_stream.source uart_if_tx,
|
if_axi_stream.source tx_if
|
||||||
// Ethernet
|
|
||||||
if_axi_stream.sink eth_if_rx,
|
|
||||||
if_axi_stream.source eth_if_tx,
|
|
||||||
// PCIe
|
|
||||||
if_axi_stream.sink pcie_if_rx,
|
|
||||||
if_axi_stream.source pcie_if_tx
|
|
||||||
);
|
);
|
||||||
|
|
||||||
|
logic usr_rst, core_clk, core_rst;
|
||||||
|
if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS)) equihash_axi(core_clk);
|
||||||
|
|
||||||
|
equihash_bm_t equihash_mask;
|
||||||
|
logic equihash_mask_val;
|
||||||
|
|
||||||
|
always_comb begin
|
||||||
|
core_clk = i_clk_200;
|
||||||
|
core_rst = i_rst_200;
|
||||||
|
end
|
||||||
|
|
||||||
|
// This block takes in the interface signals and interfaces with other blocks
|
||||||
|
control_top #(
|
||||||
|
.CORE_DAT_BYTS ( CORE_DAT_BYTS ),
|
||||||
|
.IN_DAT_BYTS ( IF_DAT_BYTS )
|
||||||
|
)
|
||||||
|
control_top (
|
||||||
|
.i_clk_core ( core_clk ),
|
||||||
|
.i_rst_core ( core_rst ),
|
||||||
|
.i_clk_if ( i_clk_if ),
|
||||||
|
.i_rst_if ( i_rst_if ),
|
||||||
|
.o_usr_rst ( usr_rst ),
|
||||||
|
.rx_if ( rx_if ),
|
||||||
|
.tx_if ( tx_if ),
|
||||||
|
.o_equihash_axi ( equihash_axi ),
|
||||||
|
.i_equihash_mask ( equihash_mask ),
|
||||||
|
.i_equihash_mask_val ( equihash_mask_val )
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
// This block is used to verify a equihash solution
|
// This block is used to verify a equihash solution
|
||||||
zcash_verif_equihash #(
|
equihash_verif_top #(
|
||||||
.DAT_BYTS(DAT_BYTS)
|
.DAT_BYTS( CORE_DAT_BYTS )
|
||||||
)
|
)
|
||||||
equihash_verif_top (
|
equihash_verif_top (
|
||||||
.i_clk ( i_clk ),
|
.i_clk ( core_clk ),
|
||||||
.i_rst ( i_rst ),
|
.i_rst ( core_rst || usr_rst ),
|
||||||
|
|
||||||
.i_clk_300 ( i_clk_300 ),
|
.i_clk_300 ( i_clk_300 ),
|
||||||
.i_rst_300 ( i_rst_300 ), // Faster clock
|
.i_rst_300 ( i_rst_300 || usr_rst ), // Faster clock
|
||||||
|
|
||||||
.i_axi ( equihash_verif_if ),
|
.i_axi ( equihash_axi ),
|
||||||
.o_mask ( equihash_verif_mask ),
|
.o_mask ( equihash_mask ),
|
||||||
.o_mask_val ( equihash_verif_mask_val )
|
.o_mask_val ( equihash_mask_val )
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
@ -140,8 +140,8 @@ task test_eh_verify_message();
|
||||||
begin
|
begin
|
||||||
verify_equihash_t msg;
|
verify_equihash_t msg;
|
||||||
verify_equihash_rpl_t verify_equihash_rpl;
|
verify_equihash_rpl_t verify_equihash_rpl;
|
||||||
integer signed get_len, in_len;
|
integer signed get_len, in_len, eh_len;
|
||||||
logic [common_pkg::MAX_SIM_BYTS*8-1:0] get_dat;
|
logic [common_pkg::MAX_SIM_BYTS*8-1:0] get_dat, get_dat_eh;
|
||||||
logic fail = 0;
|
logic fail = 0;
|
||||||
$display("Running test_eh_verify_message...");
|
$display("Running test_eh_verify_message...");
|
||||||
msg.hdr.cmd = VERIFY_EQUIHASH;
|
msg.hdr.cmd = VERIFY_EQUIHASH;
|
||||||
|
|
@ -150,17 +150,23 @@ begin
|
||||||
|
|
||||||
fork
|
fork
|
||||||
uart_tx_if.put_stream(msg, $bits(msg)/8);
|
uart_tx_if.put_stream(msg, $bits(msg)/8);
|
||||||
uart_rx_if.get_stream(get_dat, get_len);
|
|
||||||
begin
|
begin
|
||||||
while (!usr_rst) @(posedge core_clk);
|
equihash_axi.get_stream(get_dat_eh, eh_len);
|
||||||
while (usr_rst) @(posedge core_clk);
|
equihash_mask_val = 1;
|
||||||
|
equihash_mask = 0;
|
||||||
end
|
end
|
||||||
|
uart_rx_if.get_stream(get_dat, get_len);
|
||||||
join
|
join
|
||||||
|
|
||||||
|
equihash_mask_val = 0;
|
||||||
|
|
||||||
verify_equihash_rpl = get_dat;
|
verify_equihash_rpl = get_dat;
|
||||||
|
|
||||||
|
fail |= eh_len != $bits(cblockheader_sol_t)/8;
|
||||||
fail |= verify_equihash_rpl.hdr.cmd != VERIFY_EQUIHASH_RPL;
|
fail |= verify_equihash_rpl.hdr.cmd != VERIFY_EQUIHASH_RPL;
|
||||||
fail |= verify_equihash_rpl.hdr.len != $bits(fpga_status_rpl_t)/8;
|
fail |= verify_equihash_rpl.hdr.len != $bits(verify_equihash_rpl_t)/8;
|
||||||
fail |= verify_equihash_rpl.index != 1;
|
fail |= verify_equihash_rpl.index != 1;
|
||||||
|
fail |= verify_equihash_rpl.bm != 0;
|
||||||
|
|
||||||
assert (~fail) else $fatal(1, "%m %t ERROR: test_eh_verify_message was wrong:\n%p", $time, verify_equihash_rpl);
|
assert (~fail) else $fatal(1, "%m %t ERROR: test_eh_verify_message was wrong:\n%p", $time, verify_equihash_rpl);
|
||||||
|
|
||||||
|
|
@ -170,7 +176,7 @@ endtask
|
||||||
|
|
||||||
// Main testbench calls
|
// Main testbench calls
|
||||||
initial begin
|
initial begin
|
||||||
equihash_axi.rdy = 1;
|
equihash_axi.rdy = 0;
|
||||||
equihash_mask_val = 0;
|
equihash_mask_val = 0;
|
||||||
equihash_mask = 0;
|
equihash_mask = 0;
|
||||||
uart_tx_if.val = 0;
|
uart_tx_if.val = 0;
|
||||||
|
|
@ -180,8 +186,9 @@ initial begin
|
||||||
test_reset_message();
|
test_reset_message();
|
||||||
test_status_message();
|
test_status_message();
|
||||||
test_eh_verify_message();
|
test_eh_verify_message();
|
||||||
|
test_status_message();
|
||||||
|
|
||||||
#10us $finish();
|
#1us $finish();
|
||||||
|
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -136,7 +136,7 @@ begin
|
||||||
|
|
||||||
while(!done_346 || !mask_val) @(posedge clk);
|
while(!done_346 || !mask_val) @(posedge clk);
|
||||||
|
|
||||||
assert (~(|mask)) else $fatal(1, "%m %t ERROR: test_block_346 mask was non-zero:\n%p", $time, mask);
|
assert (|mask == 0) else $fatal(1, "%m %t ERROR: test_block_346 mask was non-zero:\n%p", $time, mask);
|
||||||
$display("test_block_346 PASSED");
|
$display("test_block_346 PASSED");
|
||||||
|
|
||||||
end
|
end
|
||||||
|
|
@ -145,12 +145,20 @@ endtask
|
||||||
// This is a tests the sample block 346 in the block chain but with deliberate errors
|
// This is a tests the sample block 346 in the block chain but with deliberate errors
|
||||||
task test_block_346_error();
|
task test_block_346_error();
|
||||||
begin
|
begin
|
||||||
|
logic fail = 1;
|
||||||
$display("Running test_block_346_error...");
|
$display("Running test_block_346_error...");
|
||||||
start_346_error = 1;
|
start_346_error = 1;
|
||||||
|
|
||||||
|
|
||||||
while(!done_346_error || !mask_val) @(posedge clk);
|
while(!done_346_error || !mask_val) @(posedge clk);
|
||||||
|
|
||||||
assert (&mask) else $fatal(1, "%m %t ERROR: test_block_346_error mask was zero but should of failed:\n%p", $time, mask);
|
fail &= mask.DUPLICATE_FND;
|
||||||
|
fail &= mask.BAD_ZERO_ORDER;
|
||||||
|
fail &= mask.BAD_IDX_ORDER;
|
||||||
|
fail &= mask.XOR_NON_ZERO;
|
||||||
|
fail &= mask.DIFFICULTY_FAIL;
|
||||||
|
|
||||||
|
assert (fail) else $fatal(1, "%m %t ERROR: test_block_346_error mask was zero but should of failed:\n%p", $time, mask);
|
||||||
$display("test_block_346_error PASSED");
|
$display("test_block_346_error PASSED");
|
||||||
|
|
||||||
end
|
end
|
||||||
|
|
|
||||||
|
|
@ -1,15 +1,52 @@
|
||||||
create_clock -period 5.000 -name i_clk -waveform {0.000 2.500} [get_ports -filter { NAME =~ "*i_clk*" && DIRECTION == "IN" }]
|
create_clock -period 5.000 -name i_clk_200 -waveform {0.000 2.500} [get_ports -filter { NAME =~ "*i_clk_200*" && DIRECTION == "IN" }]
|
||||||
create_clock -period 2.500 -name i_clk_300 -waveform {0.000 1.250} [get_ports -filter { NAME =~ "i_clk_300" && DIRECTION == "IN" }]
|
create_clock -period 3.333 -name i_clk_300 -waveform {0.000 1.666} [get_ports -filter { NAME =~ "i_clk_300" && DIRECTION == "IN" }]
|
||||||
|
create_clock -period 10.000 -name i_clk_if -waveform {0.000 5.000} [get_ports -filter { NAME =~ "i_clk_if" && DIRECTION == "IN" }]
|
||||||
|
|
||||||
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_in/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_in/synchronizer_wr_ptr/* }]] 1.667
|
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] 2.500
|
||||||
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_in/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_in/synchronizer_wr_ptr/* }]] 1.667
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] 2.500
|
||||||
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_in/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_in/synchronizer_rd_ptr/* }]] 2.500
|
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] 5.000
|
||||||
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_in/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_in/synchronizer_rd_ptr/* }]] 2.500
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] 5.000
|
||||||
set_bus_skew -from [get_pins -filter { NAME =~ "*ram*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_in/* }]] -to [get_pins -filter { NAME =~ "*o_dat_b*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_in/* }]] 2.500
|
set_bus_skew -from [get_pins -filter { NAME =~ "*ram*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/* }]] -to [get_pins -filter { NAME =~ "*o_dat_b*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/* }]] 5.000
|
||||||
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*ram*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_in/* }]] -to [get_pins -filter { NAME =~ "*o_dat_b*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_in/* }]] 2.500
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*ram*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/* }]] -to [get_pins -filter { NAME =~ "*o_dat_b*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/* }]] 5.000
|
||||||
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_out/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_out/synchronizer_wr_ptr/* }]] 2.500
|
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/synchronizer_wr_ptr/* }]] 2.500
|
||||||
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_out/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_out/synchronizer_wr_ptr/* }]] 2.500
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/synchronizer_wr_ptr/* }]] 2.500
|
||||||
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_out/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_out/synchronizer_rd_ptr/* }]] 1.667
|
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/synchronizer_rd_ptr/* }]] 1.667
|
||||||
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_out/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_out/synchronizer_rd_ptr/* }]] 1.667
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/synchronizer_rd_ptr/* }]] 1.667
|
||||||
set_bus_skew -from [get_pins -filter { NAME =~ "*ram*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_out/* }]] -to [get_pins -filter { NAME =~ "*o_dat_b*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_out/* }]] 1.667
|
set_bus_skew -from [get_pins -filter { NAME =~ "*ram*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/* }]] -to [get_pins -filter { NAME =~ "*o_dat_b*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/* }]] 1.667
|
||||||
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*ram*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_out/* }]] -to [get_pins -filter { NAME =~ "*o_dat_b*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ dup_check_fifo_out/* }]] 1.667
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*ram*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/* }]] -to [get_pins -filter { NAME =~ "*o_dat_b*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/* }]] 1.667
|
||||||
|
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/synchronizer_wr_ptr/* }]] 1.667
|
||||||
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/synchronizer_wr_ptr/* }]] 1.667
|
||||||
|
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/synchronizer_rd_ptr/* }]] 2.500
|
||||||
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/synchronizer_rd_ptr/* }]] 2.500
|
||||||
|
set_bus_skew -from [get_pins -filter { NAME =~ "*ram*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/* }]] -to [get_pins -filter { NAME =~ "*o_dat_b*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/* }]] 2.500
|
||||||
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*ram*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/* }]] -to [get_pins -filter { NAME =~ "*o_dat_b*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/* }]] 2.500
|
||||||
|
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] 2.500
|
||||||
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] 2.500
|
||||||
|
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] 5.000
|
||||||
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] 5.000
|
||||||
|
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] 2.500
|
||||||
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] 2.500
|
||||||
|
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] 5.000
|
||||||
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] 5.000
|
||||||
|
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] 2.500
|
||||||
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] 2.500
|
||||||
|
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] 5.000
|
||||||
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] 5.000
|
||||||
|
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_tx/cdc_fifo/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_tx/cdc_fifo/synchronizer_wr_ptr/* }]] 5.000
|
||||||
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_tx/cdc_fifo/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_tx/cdc_fifo/synchronizer_wr_ptr/* }]] 5.000
|
||||||
|
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_tx/cdc_fifo/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_tx/cdc_fifo/synchronizer_rd_ptr/* }]] 2.500
|
||||||
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_tx/cdc_fifo/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ control_top/cdc_fifo_tx/cdc_fifo/synchronizer_rd_ptr/* }]] 2.500
|
||||||
|
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/synchronizer_wr_ptr/* }]] 1.667
|
||||||
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/synchronizer_wr_ptr/* }]] 1.667
|
||||||
|
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/synchronizer_rd_ptr/* }]] 2.500
|
||||||
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/synchronizer_rd_ptr/* }]] 2.500
|
||||||
|
set_bus_skew -from [get_pins -filter { NAME =~ "*ram*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/* }]] -to [get_pins -filter { NAME =~ "*o_dat_b*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/* }]] 2.500
|
||||||
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*ram*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/* }]] -to [get_pins -filter { NAME =~ "*o_dat_b*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_in/* }]] 2.500
|
||||||
|
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/synchronizer_wr_ptr/* }]] 2.500
|
||||||
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/synchronizer_wr_ptr/* }]] 2.500
|
||||||
|
set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/synchronizer_rd_ptr/* }]] 1.667
|
||||||
|
set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/synchronizer_rd_ptr/* }]] 1.667
|
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set_bus_skew -from [get_pins -filter { NAME =~ "*ram*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/* }]] -to [get_pins -filter { NAME =~ "*o_dat_b*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/* }]] 1.667
|
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set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*ram*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/* }]] -to [get_pins -filter { NAME =~ "*o_dat_b*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ equihash_verif_top/dup_check_fifo_out/* }]] 1.667
|
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set_multicycle_path -hold -from [get_pins control_top/o_usr_rst_reg/C] 5
|
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|
set_multicycle_path -setup -from [get_pins control_top/o_usr_rst_reg/C] 5
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue