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zcash-fpga
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Bug fix and added pipeline stages

This commit is contained in:
bsdevlin 2019-04-15 13:28:13 -04:00
parent bc4861fc9f
commit 34ec3f3b88
4 changed files with 86 additions and 34 deletions
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36
ip_cores/common/src/rtl/pipeline_if.sv
View File

@ -16,13 +16,15 @@
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
module pipeline_if #(
parameter DAT_BYTS = 8,
parameter CTL_BITS = 8,
parameter NUM_STAGES = 1
) (
input rst,
if_axi_stream.sink i_if,
if_axi_stream.source o_if
input i_rst,
if_axi_stream i_if,
if_axi_stream o_if
);
genvar g0;
@ -32,11 +34,31 @@ generate
always_comb o_if.copy_if_comb(i_if.dat, i_if.val, i_if.sop, i_if.eop, i_if.err, i_if.mod, i_if.ctl);
end else begin
if_axi_stream #(.DAT_BYTS(i_if.DAT_BYTS), .CTL_BITS(i_if.CTL_BITS)) if_stage [NUM_STAGES-1] (i_if.clk);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) if_stage [NUM_STAGES-1:0] (i_if.i_clk) ;
for (g0 = 0; g0 < NUM_STAGES; g0++) begin : GEN_STAGE
pipeline_if_single pipeline_if_single (.i_if(g0 == 0 ? i_if : if_stage[g0-1]), .o_of(g0 == NUM_STAGES-1 ? o_if : if_stage[g0]));
if (g0 == 0)
pipeline_if_single #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS))
pipeline_if_single (
.i_rst ( i_rst ),
.i_if(i_if ),
.o_if(if_stage[g0])
);
else if (g0 == NUM_STAGES-1)
pipeline_if_single #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS))
pipeline_if_single (
.i_rst ( i_rst ),
.i_if(if_stage[g0-1]),
.o_if( o_if )
);
else
pipeline_if_single #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS))
pipeline_if_single (
.i_rst ( i_rst ),
.i_if(if_stage[g0-1]),
.o_if(if_stage[g0])
);
end
end

21
ip_cores/common/src/rtl/pipeline_if_single.sv
View File

@ -16,18 +16,25 @@
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
module pipeline_if_single (
input rst,
module pipeline_if_single #(
parameter DAT_BYTS = 8,
parameter CTL_BITS = 8
)(
input i_rst,
if_axi_stream.sink i_if,
if_axi_stream.source o_if
);
// Need pipeline stage to store temp data
if_axi_stream #(.DAT_BYTS(i_if.DAT_BYTS), .CTL_BITS(i_if.CTL_BITS)) if_r (i_if.clk);
always_ff @ (i_if.clk) begin
if (rst) begin
// Need pipeline stage to store temp data
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) if_r (i_if.i_clk);
always_ff @ (i_if.i_clk) begin
if (i_rst) begin
o_if.reset_source();
if_r.reset_source();
if_r.rdy <= 0;

18
zcash_fpga/src/rtl/secp256k1/secp256k1_top.sv
View File

@ -9,11 +9,6 @@ module secp256k1_top import secp256k1_pkg::*; #(
if_axi_stream.source if_cmd_tx
);
debug_if #(.DAT_BYTS (if_cmd_rx.DAT_BYTS), .CTL_BITS (1)) rx_debug (.i_if(if_cmd_rx));
debug_if #(.DAT_BYTS (if_cmd_tx.DAT_BYTS), .CTL_BITS (1)) tx_debug (.i_if(if_cmd_tx));
localparam DAT_BYTS = 8;
localparam DAT_BITS = DAT_BYTS*8;
import zcash_fpga_pkg::*;
@ -53,6 +48,7 @@ header_t header, header_l;
secp256k1_ver_t secp256k1_ver;
// Other temporary values
logic [255:0] r, r_plus_n, u2;
logic r_plus_n_gt;
logic [63:0] index;
logic u2_val;
@ -69,6 +65,7 @@ end
always_ff @ (posedge i_clk) begin
r_plus_n <= r + secp256k1_pkg::n;
r_plus_n_gt <= r_plus_n >= secp256k1_pkg::p_eq;
end
always_ff @ (posedge i_clk) begin
@ -108,7 +105,7 @@ always_ff @ (posedge i_clk) begin
timeout <= 0;
end else begin
timeout <= timeout + 1;
mult_out_if[2].rdy <= 1;
@ -352,15 +349,14 @@ always_ff @ (posedge i_clk) begin
end
1: begin
if (mult_out_if[2].rdy && mult_out_if[2].val) begin
r <= r_plus_n;
if (mult_out_if[2].dat == pt_mult0_in_p2.x) begin
cnt <= 3;
end else if (r + secp256k1_pkg::n >= secp256k1_pkg::p_eq) begin
end else if (r_plus_n_gt) begin
cnt <= 3;
secp256k1_ver.FAILED_SIG_VER <= 1;
end else begin
// Need to do one more check
mult_in_if[2].dat <= {r, pt_mult0_in_p2.z};
mult_in_if[2].dat <= {r_plus_n, pt_mult0_in_p2.z};
mult_in_if[2].ctl[7:6] <= 0; // mod p
mult_in_if[2].val <= 1;
cnt <= 2;
@ -477,7 +473,7 @@ resource_share_mod (
.i_rst ( i_rst ),
.i_axi ( mod_in_if[1:0] ),
.o_res ( mod_in_if[2] ),
.i_res ( mod_out_if[2] ),
.i_res ( mod_out_if[2] ),
.o_axi ( mod_out_if[1:0] )
);
@ -491,7 +487,7 @@ resource_share_mult (
.i_rst ( i_rst ),
.i_axi ( mult_in_if[2:0] ),
.o_res ( mult_in_if[3] ),
.i_res ( mult_out_if[3] ),
.i_res ( mult_out_if[3] ),
.o_axi ( mult_out_if[2:0] )
);

45
zcash_fpga/src/rtl/top/zcash_fpga_top.sv
View File

@ -93,7 +93,7 @@ width_change_cdc_fifo #(
.FIFO_ABITS ( 6 ),
.USE_BRAM ( 1 ),
.CDC_ASYNC ( "NO" )
)
)
cdc_fifo_rx (
.i_clk_a ( i_clk_if ),
.i_rst_a ( i_rst_if ),
@ -111,7 +111,7 @@ width_change_cdc_fifo #(
.FIFO_ABITS ( 6 ),
.USE_BRAM ( 1 ),
.CDC_ASYNC ( "NO" )
)
)
cdc_fifo_tx (
.i_clk_a ( i_clk_if ),
.i_rst_a ( i_rst_if ),
@ -143,7 +143,7 @@ cdc_fifo_if #(
.SIZE ( 16 ),
.USE_BRAM ( 0 ),
.RAM_PERFORMANCE ("HIGH_PERFORMANCE")
)
)
cdc_fifo_equihash_rx (
.i_clk_a ( i_clk_if ),
.i_rst_a ( usr_rst || i_rst_if ),
@ -154,12 +154,12 @@ cdc_fifo_equihash_rx (
.o_b ( equihash_axi_s ),
.o_emp_b ()
);
cdc_fifo #(
.SIZE ( 16 ),
.DAT_BITS ( $bits(equihash_bm_t) ),
.USE_BRAM ( 0 )
)
)
cdc_fifo_equihash_tx (
.i_clk_a ( i_clk_100 ),
.i_rst_a ( rst_100 || ENB_VERIFY_EQUIHASH == 0 ),
@ -196,7 +196,7 @@ cdc_fifo_if #(
.SIZE ( 16 ),
.USE_BRAM ( 0 ),
.RAM_PERFORMANCE ("HIGH_PERFORMANCE")
)
)
cdc_fifo_secp256k1_rx (
.i_clk_a ( i_clk_if ),
.i_rst_a ( usr_rst || i_rst_if ),
@ -212,7 +212,7 @@ cdc_fifo_if #(
.SIZE ( 16 ),
.USE_BRAM ( 0 ),
.RAM_PERFORMANCE ("HIGH_PERFORMANCE")
)
)
cdc_fifo_secp256k1_tx (
.i_clk_a ( i_clk_200 ),
.i_rst_a ( rst_200 || ENB_VERIFY_SECP256K1_SIG == 0 ),
@ -224,11 +224,38 @@ cdc_fifo_secp256k1_tx (
.o_emp_b ()
);
// We add pipelining so this block can be on a different SLR
if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BITS(CORE_CTL_BITS)) secp256k1_out_if_s_r(i_clk_200);
if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BITS(CORE_CTL_BITS)) secp256k1_in_if_s_r(i_clk_200);
pipeline_if #(
.DAT_BYTS( CORE_DAT_BYTS ),
.CTL_BITS( CORE_CTL_BITS ),
.NUM_STAGES (2)
)
secp256k1_pipeline_if0 (
.i_rst ( rst_200 ),
.i_if ( secp256k1_out_if_s ),
.o_if ( secp256k1_out_if_s_r )
);
pipeline_if #(
.DAT_BYTS( CORE_DAT_BYTS ),
.CTL_BITS( CORE_CTL_BITS ),
.NUM_STAGES (2)
)
secp256k1_pipeline_if1 (
.i_rst ( rst_200 ),
.i_if ( secp256k1_in_if_s_r ),
.o_if ( secp256k1_in_if_s )
);
secp256k1_top secp256k1_top (
.i_clk ( i_clk_200 ),
.i_rst ( rst_200 || ENB_VERIFY_SECP256K1_SIG == 0 ),
.if_cmd_rx ( secp256k1_out_if_s ),
.if_cmd_tx ( secp256k1_in_if_s )
.if_cmd_rx ( secp256k1_out_if_s_r ),
.if_cmd_tx ( secp256k1_in_if_s_r )
);