Bug fix: Update to reduction multiplier to properly handle back
pressure.
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5f74545e77
commit
38b8284194
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@ -52,8 +52,8 @@ logic [DAT_BITS-1:0] dat;
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logic val;
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logic rdy;
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if_axi_stream #(.DAT_BYTS(DAT_BITS/8)) fifo_in_if(i_clk);
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if_axi_stream #(.DAT_BYTS(DAT_BITS/8)) fifo_out_if(i_clk);
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if_axi_stream #(.DAT_BITS(2*K + 2), .CTL_BITS(CTL_BITS)) fifo_in_if(i_clk);
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if_axi_stream #(.DAT_BITS(2*K + 2), .CTL_BITS(CTL_BITS)) fifo_out_if(i_clk);
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logic fifo_out_full;
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// Stage 1 multiplication
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@ -67,6 +67,9 @@ always_ff @ (posedge i_clk) begin
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o_mult_if_0.reset_source();
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fifo_in_if.reset_source();
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end else begin
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if (fifo_in_if.rdy) fifo_in_if.val <= 0;
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if (o_mult_if_0.rdy) o_mult_if_0.val <= 0;
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if (o_rdy) begin
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o_mult_if_0.sop <= 1;
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o_mult_if_0.eop <= 1;
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@ -75,6 +78,7 @@ always_ff @ (posedge i_clk) begin
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o_mult_if_0.dat[0 +: DAT_BITS] <= i_dat >> (2*K - 2);
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o_mult_if_0.dat[DAT_BITS +: DAT_BITS] <= U;
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fifo_in_if.dat <= i_dat % (1 << (2*K + 2));
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fifo_in_if.ctl <= i_ctl;
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fifo_in_if.val <= i_val;
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end
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end
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@ -89,6 +93,8 @@ always_ff @ (posedge i_clk) begin
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if (i_rst) begin
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o_mult_if_1.reset_source();
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end else begin
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if (o_mult_if_1.rdy) o_mult_if_1.val <= 0;
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if (i_mult_if_0.rdy) begin
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o_mult_if_1.sop <= 1;
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o_mult_if_1.eop <= 1;
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@ -103,6 +109,8 @@ end
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// Stage 3 subtraction to final result
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always_comb begin
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i_mult_if_1.rdy = (rdy && val) || ~val;
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end
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always_comb begin
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fifo_out_if.rdy = i_mult_if_1.val && i_mult_if_1.rdy;
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end
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@ -110,6 +118,8 @@ always_ff @ (posedge i_clk) begin
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if (i_rst) begin
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val <= 0;
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end else begin
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if (i_mult_if_1.rdy) val <= 0;
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if (i_mult_if_1.rdy) begin
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val <= i_mult_if_1.val;
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ctl <= i_mult_if_1.ctl;
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@ -128,6 +138,9 @@ always_ff @ (posedge i_clk) begin
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o_val <= 0;
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o_err <= 0;
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end else begin
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if (i_rdy) o_val <= 0;
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if (~o_val || (o_val && i_rdy)) begin
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o_val <= val;
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o_ctl <= ctl;
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@ -142,7 +155,8 @@ end
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// Fifo to store inputs (as we need to do final subtraction)
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axi_stream_fifo #(
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.SIZE ( 32 ),
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.DAT_BITS ( DAT_BITS )
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.DAT_BITS ( 2*K + 2 ),
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.CTL_BITS ( CTL_BITS )
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)
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axi_stream_fifo (
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.i_clk ( i_clk ),
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