From 445a712f60c3c11cea20403b226c3b09b02ae408 Mon Sep 17 00:00:00 2001
From: bsdevlin <bsdevlin@Burt>
Date: Thu, 11 Apr 2019 23:34:33 -0400
Subject: [PATCH] bug fix and updates

---
 apps/python/zcash_fpga.py                     | 26 +++++++++----------
 bittware_xupvvh/src/rtl/uart_wrapper.sv       |  3 ---
 .../src/rtl/secp256k1/secp256k1_point_dbl.sv  |  9 ++++---
 zcash_fpga/src/rtl/secp256k1/secp256k1_top.sv |  4 +--
 4 files changed, 20 insertions(+), 22 deletions(-)

diff --git a/apps/python/zcash_fpga.py b/apps/python/zcash_fpga.py
index 706f1e3..c73b34a 100644
--- a/apps/python/zcash_fpga.py
+++ b/apps/python/zcash_fpga.py
@@ -4,6 +4,7 @@ class zcash_fpga:
     import serial
     import codecs
     import struct
+    import struct
 
     def byt_to_ver(a):
         return 'v{}.{}.{}'.format(a[2], a[1], a[0])
@@ -12,14 +13,17 @@ class zcash_fpga:
         return a[::-1].decode("utf-8")
 
     def byt_to_hex(a):
-        return a.hex()
+        return '0x' + a.hex()
+
+    def byt_to_int(a):
+        return int.from_bytes(a, byteorder='little')
 
     fpga_msg_type_dict = {'FPGA_IGNORE_RPL':int('80000002', 16),
                           'FPGA_STATUS_RPL':int('80000001', 16),
                           'RESET_FPGA_RPL':int('80000000', 16),
                           'VERIFY_SECP256K1_SIG_RPL':int('80000101', 16)}
 
-    fpga_msg_dict = {fpga_msg_type_dict['VERIFY_SECP256K1_SIG_RPL']:{'name':'VERIFY_SECP256K1_SIG_RPL', 'feilds':[(8, 'index', byt_to_hex), (1, 'bm', byt_to_hex), (2, 'cycle_cnt', byt_to_hex)]},
+    fpga_msg_dict = {fpga_msg_type_dict['VERIFY_SECP256K1_SIG_RPL']:{'name':'VERIFY_SECP256K1_SIG_RPL', 'feilds':[(8, 'index', byt_to_int), (1, 'bm', byt_to_hex), (2, 'cycle_cnt', byt_to_int)]},
                      fpga_msg_type_dict['FPGA_IGNORE_RPL']:{'name':'FPGA_IGNORE_RPL', 'feilds':[(8, 'ignored_header', byt_to_hex)]},
                      fpga_msg_type_dict['FPGA_STATUS_RPL']:{'name':'FPGA_STATUS_RPL', 'feilds':[(4, 'version', byt_to_ver), (8, 'build_date', byt_to_str), (8, 'buid_host', byt_to_str), (8, 'cmd_cap', byt_to_hex)]},
                      fpga_msg_type_dict['RESET_FPGA_RPL']:{'name':'RESET_FPGA_RPL', 'feilds':[]}}
@@ -27,8 +31,6 @@ class zcash_fpga:
 
     def __init__(self, COM='COM4'):
         self.s = self.serial.Serial(COM, 921600, timeout=1)
-        #Clear any pending messages
-        self.get_reply()
         #Test getting FPGA status
         self.get_status()
         print("Connected...")
@@ -51,7 +53,6 @@ class zcash_fpga:
         msg_list = self.parse_reply(res)
         if msg_list and len(msg_list) > 0:
             for msg in msg_list:
-                print (msg)
                 self.print_reply(msg)
             return msg_list
         else:
@@ -60,15 +61,14 @@ class zcash_fpga:
 
     def secp256k1_verify_sig(self, index, hsh, r, s, Qx, Qy):
         cmd = '00000101000000B0'
-        cmd = format(index, 'x').ljust(16, '0') + cmd
-        cmd = format(s, 'x').ljust(64, '0') + cmd
-        cmd = format(r, 'x').ljust(64, '0') + cmd
-        cmd = format(hsh, 'x').ljust(64, '0') + cmd
-        cmd = format(Qx, 'x').ljust(64, '0') + cmd
-        cmd = format(Qy, 'x').ljust(64, '0') + cmd
+        cmd = format(index, 'x').rjust(16, '0') + cmd
+        cmd = format(s, 'x').rjust(64, '0') + cmd
+        cmd = format(r, 'x').rjust(64, '0') + cmd
+        cmd = format(hsh, 'x').rjust(64, '0') + cmd
+        cmd = format(Qx, 'x').rjust(64, '0') + cmd
+        cmd = format(Qy, 'x').rjust(64, '0') + cmd
         #Need to swap cmd byte order
         cmd = "".join(reversed([cmd[i:i+2] for i in range(0, len(cmd), 2)]))
-
         self.s.write(self.codecs.decode(cmd, 'hex'))
         res = self.get_reply()[0] # Just look at the first reply
         if res is not None and (self.struct.unpack('<I', res[4:8])[0] != self.fpga_msg_type_dict['VERIFY_SECP256K1_SIG_RPL']):
@@ -115,7 +115,7 @@ def example_secp256k1_sig():
     
     zf.reset_fpga() # Reset incase something went wrong last run
 
-    index = 1234
+    index = 1
     hsh = 34597931798561447004034205848155169322219865803759328163562698792725658370004
     r = 550117237093786687120086685263208063857013211911888854762107796665370524299
     s = 100440748044460701692736849796872767381221821858945401325418288486792652245963
diff --git a/bittware_xupvvh/src/rtl/uart_wrapper.sv b/bittware_xupvvh/src/rtl/uart_wrapper.sv
index c65df06..597b577 100644
--- a/bittware_xupvvh/src/rtl/uart_wrapper.sv
+++ b/bittware_xupvvh/src/rtl/uart_wrapper.sv
@@ -40,9 +40,6 @@ logic uart_axi_awready, uart_axi_awvalid, uart_axi_arvalid, uart_axi_arready, ua
 
 logic [15:0] tx_byt_cnt, tx_byt_len, rx_byt_cnt, rx_byt_len;
 
-debug_if #(.DAT_BYTS (1), .CTL_BITS (1)) txuart_debug_if (.i_if(tx_if));
-debug_if #(.DAT_BYTS (1), .CTL_BITS (1)) rxuart_debug_if (.i_if(rx_if));
-
 always_ff @ (posedge i_clk) begin
   if (i_rst) begin
     uart_axi_wdata <= 0;
diff --git a/zcash_fpga/src/rtl/secp256k1/secp256k1_point_dbl.sv b/zcash_fpga/src/rtl/secp256k1/secp256k1_point_dbl.sv
index 03688eb..0a6cf00 100644
--- a/zcash_fpga/src/rtl/secp256k1/secp256k1_point_dbl.sv
+++ b/zcash_fpga/src/rtl/secp256k1/secp256k1_point_dbl.sv
@@ -33,12 +33,15 @@ module secp256k1_point_dbl
   output logic   o_err,
   // Interface to 256bit multiplier (mod p)
   if_axi_stream.source o_mult_if,
-  if_axi_stream.source i_mult_if,
+  if_axi_stream.sink i_mult_if,
   // Interface to only mod reduction block
   if_axi_stream.source o_mod_if,
-  if_axi_stream.source i_mod_if
+  if_axi_stream.sink i_mod_if
 );
 
+debug_if #(.DAT_BYTS (2*256/8), .CTL_BITS (16)) o_mult_debug (.i_if(o_mult_if));
+debug_if #(.DAT_BYTS (256/8), .CTL_BITS (16)) i_mult_debug (.i_if(i_mult_if));
+
 /*
  * These are the equations that need to be computed, they are issued as variables
  * become valid. We have a bitmask to track what equation results are valid which
@@ -60,7 +63,7 @@ module secp256k1_point_dbl
  * 13.   (o_p.z) = 2*(i_p.y) mod p
  * 14.   (o_p.z) = o_p.y * i_p.z mod p [eq14]
  */
-logic [14:0] eq_val, eq_wait;
+(* mark_debug = "true" *) logic [14:0] eq_val, eq_wait;
 
 // Temporary variables
 logic [255:0] A, B, C, D, E;
diff --git a/zcash_fpga/src/rtl/secp256k1/secp256k1_top.sv b/zcash_fpga/src/rtl/secp256k1/secp256k1_top.sv
index cb96f53..3cfc682 100644
--- a/zcash_fpga/src/rtl/secp256k1/secp256k1_top.sv
+++ b/zcash_fpga/src/rtl/secp256k1/secp256k1_top.sv
@@ -13,8 +13,6 @@ localparam DAT_BYTS = 8;
 localparam DAT_BITS = DAT_BYTS*8;
 import zcash_fpga_pkg::*;
 
-debug_if #(.DAT_BYTS (8), .CTL_BITS (1)) tx_debug_if (.i_if(if_cmd_rx));
-debug_if #(.DAT_BYTS (8), .CTL_BITS (1)) rx_debug_if (.i_if(if_cmd_tx));
 
 // 256 bit inverse calculation
 if_axi_stream #(.DAT_BYTS(256/8)) bin_inv_in_if(i_clk);
@@ -45,7 +43,7 @@ typedef enum {IDLE = 0,
               IGNORE = 8,
               FINISHED = 9} secp256k1_state_t;
 
-(* mark_debug = "true" *)  secp256k1_state_t secp256k1_state;
+secp256k1_state_t secp256k1_state;
 header_t header, header_l;
 secp256k1_ver_t secp256k1_ver;
 // Other temporary values