From 4b772fed16fe89e04c30fb6c0a7094428b0636b7 Mon Sep 17 00:00:00 2001 From: bsdevlin Date: Wed, 26 Jun 2019 18:43:44 +0800 Subject: [PATCH] Fix multi driven net --- .../src/rtl/secp256k1/secp256k1_point_mult.sv | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/zcash_fpga/src/rtl/secp256k1/secp256k1_point_mult.sv b/zcash_fpga/src/rtl/secp256k1/secp256k1_point_mult.sv index 40592bc..905062c 100644 --- a/zcash_fpga/src/rtl/secp256k1/secp256k1_point_mult.sv +++ b/zcash_fpga/src/rtl/secp256k1/secp256k1_point_mult.sv @@ -316,8 +316,19 @@ end always_ff @ (posedge i_clk) begin if (i_rst) begin - add_out_if[2].reset_source(); - sub_out_if[2].reset_source(); + add_out_if[2].val <= 0; + add_out_if[2].sop <= 0; + add_out_if[2].eop <= 0; + add_out_if[2].ctl <= 0; + add_out_if[2].mod <= 0; + add_out_if[2].err <= 0; + + sub_out_if[2].val <= 0; + sub_out_if[2].sop <= 0; + sub_out_if[2].eop <= 0; + sub_out_if[2].ctl <= 0; + sub_out_if[2].mod <= 0; + sub_out_if[2].err <= 0; end else begin if (~add_out_if[2].val || (add_out_if[2].val && add_out_if[2].rdy)) begin add_out_if[2].val <= add_in_if[2].val; @@ -327,7 +338,6 @@ always_ff @ (posedge i_clk) begin add_out_if[2].eop <= 1; end if (~sub_out_if[2].val || (sub_out_if[2].val && sub_out_if[2].rdy)) begin - sub_in_if[2].rdy <= sub_out_if[2].rdy; sub_out_if[2].val <= sub_in_if[2].val; sub_out_if[2].dat <= fe_sub(sub_in_if[2].dat[0 +: 256], sub_in_if[2].dat[256 +: 256]); sub_out_if[2].ctl <= sub_in_if[2].ctl;