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Bug fix for multiplier and top level secp256k1 final testbenches working

This commit is contained in:
bsdevlin 2019-03-26 13:39:30 -04:00
parent 65e3723d21
commit 537acd9ce2
8 changed files with 206 additions and 119 deletions
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26
ip_cores/common/src/rtl/common_if.sv
View File

@ -180,6 +180,32 @@ interface if_axi_mm # (
rd_dat_val <= 0;
wait_rq <= 0;
endtask
task automatic put_data(input logic [D_BITS-1:0] data, [A_BITS-1:0] addr_in);
reset_source();
@(posedge i_clk);
wr = 1;
wr_dat = data;
addr = addr_in;
@(posedge i_clk); // Go to next clock edge
while (wait_rq) @(posedge i_clk); // If not rdy then wait here
reset_source();
endtask
task automatic get_data(ref logic [D_BITS-1:0] data, input logic [A_BITS-1:0] addr_in);
reset_source();
@(posedge i_clk);
rd = 1;
addr = addr_in;
@(posedge i_clk); // Go to next clock edge
if (!wait_rq) rd = 0;
while (!rd_dat_val) begin
if (!wait_rq) rd = 0;
@(posedge i_clk);
end
data = rd_dat;
reset_source();
endtask
endinterface

4
ip_cores/util/src/rtl/barret_mod.sv
View File

@ -132,8 +132,8 @@ generate
if (MULTIPLIER == "ACCUM_MULT") begin: MULTIPLIER_GEN
accum_mult # (
.BITS_A ( OUT_BITS +8 ),
.LEVEL_A ( 12 ),
.LEVEL_B ( 8 )
.LEVEL_A ( 6 ),
.LEVEL_B ( 4 )
)
accum_mult (
.i_clk ( i_clk ),

110
ip_cores/util/src/rtl/karatsuba_ofman_mult.sv
View File

@ -43,31 +43,35 @@ localparam HBITS = BITS/2;
logic [BITS-1:0] m0, m1, m2, dat_a, dat_b;
logic [BITS*2-1:0] q;
logic [HBITS-1:0] a0, a1;
logic sign, sign_, sign_1;
logic val, val_, val_1;
logic [CTL_BITS-1:0] ctl, ctl_, ctl_1;
logic sign_;
logic [HBITS-1:0] a0_, a1_;
logic [BITS-1:0] m0_, m1_, m2_;
logic [LEVEL*3-1:0] val, sign;
logic [LEVEL*3-1:0][CTL_BITS-1:0] ctl;
always_comb begin
o_val = val[LEVEL*3-1];
o_ctl = ctl[LEVEL*3-1];
if (LEVEL == 1)
o_rdy = ~o_val || (o_val && i_rdy);
else
o_rdy = i_rdy;
end
always_ff @ (posedge i_clk) begin
if (i_rst) begin
o_val <= 0;
val_1 <= 0;
val_ <= 0;
val <= 0;
end else begin
if(~o_val || (o_val && i_rdy)) begin
o_val <= val_1;
val_1 <= val_;
val_ <= val;
if(o_rdy) begin
val <= {val, i_val};
end
end
end
always_ff @ (posedge i_clk) begin
if(~o_val || (o_val && i_rdy)) begin
if(o_rdy) begin
o_dat <= q;
o_ctl <= ctl_1;
ctl_1 <= ctl_;
ctl <= {ctl, i_ctl};
a0_ <= a0;
a1_ <= a1;
m0_ <= m0;
@ -75,7 +79,7 @@ always_ff @ (posedge i_clk) begin
m2_ <= m2;
dat_a <= i_dat_a;
dat_b <= i_dat_b;
ctl_ <= ctl;
sign <= {sign, sign_};
end
end
@ -83,40 +87,20 @@ generate
always_comb begin
a0 = i_dat_a[0 +: HBITS] > i_dat_a[HBITS +: HBITS] ? i_dat_a[0 +: HBITS] - i_dat_a[HBITS +: HBITS] : i_dat_a[HBITS +: HBITS] - i_dat_a[0 +: HBITS];
a1 = i_dat_b[HBITS +: HBITS] > i_dat_b[0 +: HBITS] ? i_dat_b[HBITS +: HBITS] - i_dat_b[0 +: HBITS] : i_dat_b[0 +: HBITS] - i_dat_b[HBITS +: HBITS];
sign_ = ((i_dat_a[0 +: HBITS] < i_dat_a[HBITS +: HBITS]) ^
(i_dat_b[HBITS +: HBITS] < i_dat_b[0 +: HBITS]));
q = (m0_ << BITS) + ((m0_ + m2_ + (sign == 1 ? -m1_ : m1_)) << HBITS) + m2_;
sign_ = ((dat_a[0 +: HBITS] < dat_a[HBITS +: HBITS]) ^
(dat_b[HBITS +: HBITS] < dat_b[0 +: HBITS]));
q = (m0_ << BITS) + ((m0_ + m2_ + (sign[3*(LEVEL-1)] == 1 ? -m1_ : m1_)) << HBITS) + m2_;
end
if (LEVEL == 1) begin: GEN_REC
always_comb begin
m0 = dat_a[HBITS +: HBITS] * dat_b[HBITS +: HBITS];
m2 = dat_a[0 +: HBITS] * dat_b[0 +: HBITS];
m1 = (a0_ * a1_);
o_rdy = i_rdy;
val = i_val;
ctl = i_ctl;
end
always_ff @ (posedge i_clk) begin
if(~o_val || (o_val && i_rdy)) begin
sign <= sign_1;
sign_1 <= sign_;
end
end
end else begin
// pipeline the other non-mult values x clock cycles and add them after multipliers
logic [LEVEL*3-1:0] sign_r;
always_comb begin
sign = sign_r[LEVEL*3-2];
end
always_ff @ (posedge i_clk) begin
if(~o_val || (o_val && i_rdy)) begin
sign_r <= {sign_r, sign_};
end
end
karatsuba_ofman_mult # (
.BITS ( HBITS ),
@ -124,55 +108,55 @@ generate
.LEVEL ( LEVEL-1 )
)
karatsuba_ofman_mult_m0 (
.i_clk ( i_clk ),
.i_rst ( i_rst ),
.i_clk ( i_clk ),
.i_rst ( i_rst ),
.i_dat_a ( dat_a[HBITS +: HBITS] ),
.i_dat_b ( dat_b[HBITS +: HBITS] ),
.i_val ( i_val ),
.o_val ( val ),
.i_ctl ( i_ctl ),
.o_ctl ( ctl ),
.i_rdy ( i_rdy ),
.o_rdy ( o_rdy ),
.o_dat ( m0 )
.i_val ( val[0] ),
.o_val ( ),
.i_ctl ( ctl[0] ),
.o_ctl ( ),
.i_rdy ( o_rdy ),
.o_rdy ( ),
.o_dat ( m0 )
);
karatsuba_ofman_mult # (
.BITS ( HBITS ),
.CTL_BITS ( 1 ),
.CTL_BITS ( CTL_BITS ),
.LEVEL ( LEVEL-1 )
)
karatsuba_ofman_mult_m2 (
.i_clk ( i_clk ),
.i_rst ( i_rst ),
.i_clk ( i_clk ),
.i_rst ( i_rst ),
.i_dat_a ( dat_a[0 +: HBITS] ),
.i_dat_b ( dat_b[0 +: HBITS] ),
.i_val ( i_val ),
.i_val ( val[0] ),
.o_val (),
.i_ctl ( 1'd0 ),
.i_ctl ( ctl[0] ),
.o_ctl (),
.i_rdy ( i_rdy ),
.i_rdy ( o_rdy ),
.o_rdy (),
.o_dat ( m2 )
.o_dat ( m2 )
);
karatsuba_ofman_mult # (
.BITS ( HBITS ),
.CTL_BITS ( 1 ),
.CTL_BITS ( CTL_BITS ),
.LEVEL ( LEVEL-1 )
)
karatsuba_ofman_mult_m1 (
.i_clk ( i_clk ),
.i_rst ( i_rst ),
.i_dat_a ( a0_ ),
.i_dat_b ( a1_ ),
.i_val ( i_val ),
.i_clk ( i_clk ),
.i_rst ( i_rst ),
.i_dat_a ( a0_ ),
.i_dat_b ( a1_ ),
.i_val ( val[0] ),
.o_val (),
.i_ctl ( 1'd0 ),
.i_ctl ( ctl[0] ),
.o_ctl (),
.i_rdy ( i_rdy ),
.i_rdy ( o_rdy ),
.o_rdy (),
.o_dat ( m1 )
.o_dat ( m1 )
);

2
ip_cores/util/src/tb/karatsuba_ofman_mult_tb.sv
View File

@ -49,7 +49,7 @@ always_ff @ (posedge clk)
if (out_if.val && out_if.err)
$error(1, "%m %t ERROR: output .err asserted", $time);
localparam LEVEL = 2;
localparam LEVEL = 1;
karatsuba_ofman_mult # (
.BITS ( 256 ),
.CTL_BITS ( 8 ),

137
zcash_fpga/src/rtl/secp256k1/secp256k1_top.sv
View File

@ -1,6 +1,7 @@
module secp256k1_top #(
parameter DAT_BYTS = 8,
parameter DAT_BITS = DAT_BYTS*8
parameter DAT_BITS = DAT_BYTS*8,
parameter DO_AFFINE_CHECK = 0
)(
input i_clk,
input i_rst,
@ -42,7 +43,8 @@ typedef enum {IDLE,
CALC_S_INV,
CALC_U1_U2,
CALC_X,
CALC_X_JACOB,
CALC_X_AFFINE,
CHECK_IN_JB,
UPDATE_RAM_VARIABLES,
IGNORE,
FINISHED} secp256k1_state_t;
@ -51,9 +53,9 @@ secp256k1_state_t secp256k1_state;
header_t header, header_l;
secp256k1_ver_t secp256k1_ver;
// Other temporary values - could use RAM insead?
logic [255:0] e, r, w, u1, u2;
logic [255:0] r, u2;
logic [63:0] index;
logic w_val, u1_val, u2_val;
logic u2_val;
localparam MAX_BYT_MSG = 64; // Max bytes in a reply message
@ -75,14 +77,9 @@ always_ff @ (posedge i_clk) begin
if_cmd_rx.rdy <= 0;
cnt <= 0;
register_file_a.reset_source();
w <= 0;
w_val <= 0;
r <= 0;
u1 <= 0;
u1_val <= 0;
u2 <= 0;
u2_val <= 0;
e <= 0;
bin_inv_in_if.reset_source();
bin_inv_out_if.rdy <= 0;
secp256k1_ver <= 0;
@ -122,6 +119,7 @@ always_ff @ (posedge i_clk) begin
if (pt_mult0_in_val && pt_mult0_in_rdy)
pt_mult0_in_val <= 0;
if (pt_mult1_in_val && pt_mult1_in_rdy)
pt_mult1_in_val <= 0;
@ -130,17 +128,23 @@ always_ff @ (posedge i_clk) begin
if (pt_mult0_in_p2_val && pt_mult0_in_rdy)
pt_mult0_in_p2_val <= 0;
if (mult_in_if[2].val && mult_in_if[2].rdy)
mult_in_if[2].val <= 0;
case(secp256k1_state)
{IDLE}: begin
inv_p <= secp256k1_pkg::n;
w_val <= 0;
u1_val <= 0;
u2_val <= 0;
secp256k1_ver <= 0;
if_cmd_rx.rdy <= 1;
header_l <= header;
cnt <= 0;
pt_mult1_in_p.z <= 1;
pt_mult1_in_p.x <= secp256k1_pkg::Gx;
pt_mult1_in_p.y <= secp256k1_pkg::Gy;
if (if_cmd_rx.val && if_cmd_rx.rdy) begin
case(header.cmd)
{VERIFY_SECP256K1_SIG}: begin
@ -178,7 +182,7 @@ always_ff @ (posedge i_clk) begin
case(cnt) inside
[0:3]: begin
register_file_a.a <= SIG_VER_S + (cnt % 4);
register_file_a.a <= SIG_VER_S/8 + (cnt);
register_file_a.d <= if_cmd_rx.dat;
// Can start calculating the inverse here
bin_inv_in_if.dat[(cnt % 4)*64 +: 64] <= if_cmd_rx.dat;
@ -187,23 +191,23 @@ always_ff @ (posedge i_clk) begin
end
end
[4:7]: begin
register_file_a.a <= SIG_VER_R + (cnt % 4);
register_file_a.a <= SIG_VER_R/8 + (cnt - 4);
r[(cnt % 4)*64 +: 64] <= if_cmd_rx.dat; // TODO remove
register_file_a.d <= if_cmd_rx.dat;
mult_in_if[2].dat[(cnt % 4)*64 +: 64] <= if_cmd_rx.dat;
end
[8:11]: begin
e[(cnt % 4)*64 +: 64] <= if_cmd_rx.dat;
register_file_a.a <= SIG_VER_HASH + (cnt % 4);
pt_mult0_in_k[(cnt % 4)*64 +: 64] <= if_cmd_rx.dat;
register_file_a.a <= SIG_VER_HASH/8 + (cnt - 8);
register_file_a.d <= if_cmd_rx.dat;
end
[12:19]: begin
register_file_a.a <= SIG_VER_Q + (cnt % 8);
pt_mult1_in_p.z <= 1;
if (cnt % 8 < 4) begin
pt_mult1_in_p.x[(cnt % 4)*64 +: 64] <= if_cmd_rx.dat;
register_file_a.a <= SIG_VER_Q/8 + (cnt - 12);
pt_mult0_in_p.z <= 1;
if ((cnt-12) < 4) begin
pt_mult0_in_p.x[(cnt % 4)*64 +: 64] <= if_cmd_rx.dat;
end else begin
pt_mult1_in_p.y[(cnt % 4)*64 +: 64] <= if_cmd_rx.dat;
pt_mult0_in_p.y[(cnt % 4)*64 +: 64] <= if_cmd_rx.dat;
end
register_file_a.d <= if_cmd_rx.dat;
end
@ -215,8 +219,7 @@ always_ff @ (posedge i_clk) begin
if (mult_in_if[2].dat >= secp256k1_pkg::n) secp256k1_ver.OUT_OF_RANGE_R <= 1;
if (bin_inv_out_if.val && bin_inv_out_if.rdy) begin
bin_inv_out_if.rdy <= 0;
w <= bin_inv_out_if.dat;
w_val <= 1;
bin_inv_in_if.dat <= bin_inv_out_if.dat;
// Start calculating U2
mult_in_if[2].ctl <= 1; // mod n
mult_in_if[2].dat[256 +: 256] <= bin_inv_out_if.dat;
@ -232,7 +235,7 @@ always_ff @ (posedge i_clk) begin
cnt[1:0] <= 2'b01;
mult_in_if[2].val <= 0;
// Calculate U1
mult_in_if[2].dat[0 +: 256] <= e;
mult_in_if[2].dat[0 +: 256] <= pt_mult0_in_k;
mult_in_if[2].val <= 1;
if (cnt[1:0] == 2'b01) begin
mult_in_if[2].val <= 0;
@ -242,18 +245,13 @@ always_ff @ (posedge i_clk) begin
// TODO load into RAM
if (mult_out_if[2].val && mult_out_if[2].rdy) begin
case(cnt[1])
case(cnt[2])
{1'd0}: begin
pt_mult0_in_k <= mult_out_if[2].dat;
// TODO write this to RAM
u1 <= mult_out_if[2].dat;
pt_mult0_in_k <= mult_out_if[2].dat;
pt_mult0_in_p.z <= 1;
pt_mult0_in_p.x <= secp256k1_pkg::Gx;
pt_mult0_in_p.y <= secp256k1_pkg::Gy;
pt_mult0_in_val <= 1;
u1_val <= 1;
cnt[1] <= 1;
cnt[2] <= 1;
end
{1'd1}: begin
pt_mult1_in_k <= mult_out_if[2].dat;
@ -297,14 +295,21 @@ always_ff @ (posedge i_clk) begin
cnt <= 0;
// Just store our value temp
pt_mult0_in_p2 <= pt_mult0_out_p;
secp256k1_state <= CALC_X_JACOB;
mult_in_if[2].val <= 1;
mult_in_if[2].dat <= {pt_mult0_out_p.z, pt_mult0_out_p.z};
mult_in_if[2].ctl <= 0; // mod p
if (DO_AFFINE_CHECK) begin
secp256k1_state <= CALC_X_AFFINE;
mult_in_if[2].val <= 1;
mult_in_if[2].dat <= {pt_mult0_out_p.z, pt_mult0_out_p.z};
mult_in_if[2].ctl <= 0; // mod p
end else begin
secp256k1_state <= CHECK_IN_JB;
mult_in_if[2].val <= 1;
mult_in_if[2].dat <= {pt_mult0_out_p.z, pt_mult0_out_p.z};
mult_in_if[2].ctl <= 0; // mod p
end
// Here we either do a final inverstion to get the original .x value or we can do special checks
end
end
{CALC_X_JACOB}: begin
{CALC_X_AFFINE}: begin
case(cnt)
0: begin
if (mult_out_if[2].rdy && mult_out_if[2].val) begin
@ -345,6 +350,49 @@ always_ff @ (posedge i_clk) begin
secp256k1_state <= FINISHED;
end
endcase
end
// This state does the verification checks avoiding the final inversion
{CHECK_IN_JB}: begin
case(cnt)
0: begin
if (mult_out_if[2].rdy && mult_out_if[2].val) begin
pt_mult0_in_p2.z <= mult_out_if[2].dat;
mult_in_if[2].val <= 1;
mult_in_if[2].dat <= {r, mult_out_if[2].dat};
mult_in_if[2].ctl <= 0; // mod p
cnt <= 1;
end
end
1: begin
if (mult_out_if[2].rdy && mult_out_if[2].val) begin
r <= r + secp256k1_pkg::n;
if (mult_out_if[2].dat == pt_mult0_in_p2.x) begin
cnt <= 3;
end else if (r + secp256k1_pkg::n >= secp256k1_pkg::p_eq) begin
cnt <= 3;
secp256k1_ver.FAILED_SIG_VER <= 1;
end else begin
// Need to do one more check
mult_in_if[2].dat <= {r, pt_mult0_in_p2.z};
mult_in_if[2].ctl <= 0; // mod p
mult_in_if[2].val <= 1;
cnt <= 2;
end
end
end
2: begin
if (mult_out_if[2].rdy && mult_out_if[2].val) begin
if(mult_out_if[2].dat != pt_mult0_in_p2.x)
secp256k1_ver.FAILED_SIG_VER <= 1;
cnt <= 3;
end
end
3: begin
cnt <= $bits(verify_secp256k1_sig_rpl_t)/8;
msg <= verify_secp256k1_sig_rpl(secp256k1_ver, index);
secp256k1_state <= FINISHED;
end
endcase
end
{UPDATE_RAM_VARIABLES}: begin
// Here we write all our calculated variables to RAM
@ -362,21 +410,32 @@ always_ff @ (posedge i_clk) begin
end
endcase
// We use this to write to the RAM as results are valid
end
end
logic if_axi_mm_rd_;
always_comb begin
register_file_b.a = if_axi_mm.addr/8;
end
always_ff @ (posedge i_clk) begin
if (i_rst) begin
if_axi_mm.reset_sink();
register_file_b.reset_source();
register_file_b.en <= 1;
register_file_b.re <= 1;
register_file_b.we <= 0;
register_file_b.d <= 0;
if_axi_mm_rd_ <= 0;
end else begin
if_axi_mm_rd_ <= if_axi_mm_rd;
if_axi_mm.rd_dat_val <= 0;
register_file_b.en <= 1;
register_file_b.re <= 1;
register_file_b.a <= if_axi_mm.addr/8;
if_axi_mm_rd <= if_axi_mm.rd;
if (if_axi_mm_rd) begin
if (if_axi_mm_rd_) begin
if_axi_mm.rd_dat_val <= 1;
if_axi_mm.rd_dat <= register_file_b.q;
end
@ -458,7 +517,7 @@ packet_arb # (
.CTL_BITS ( 8 ),
.NUM_IN ( 3 ),
.OVR_WRT_BIT ( ARB_BIT ),
.PIPELINE ( 1 )
.PIPELINE ( 0 )
)
packet_arb_mult (
.i_clk ( i_clk ),

2
zcash_fpga/src/rtl/top/zcash_fpga_pkg.sv
View File

@ -98,8 +98,8 @@ package zcash_fpga_pkg;
logic [255:0] Qy;
logic [255:0] Qx;
logic [255:0] hash;
logic [255:0] s;
logic [255:0] r;
logic [255:0] s;
logic [63:0] index;
header_t hdr;
} verify_secp256k1_sig_t;

20
zcash_fpga/src/tb/secp256k1_point_mult_tb.sv
View File

@ -134,15 +134,14 @@ secp256k1_mod (
);
// Test a point
task test(input logic [255:0] k, jb_point_t p_exp);
task test(input logic [255:0] k, jb_point_t p_exp, p_in = secp256k1_pkg::G_p);
begin
integer signed get_len;
logic [common_pkg::MAX_SIM_BYTS*8-1:0] expected, get_dat;
logic [255:0] in_a, in_b;
integer start_time, finish_time;
jb_point_t p_in, p_out;
jb_point_t p_out;
$display("Running test_0...");
p_in = secp256k1_pkg::G_p;
k_in = k;
start_time = $time;
fork
@ -152,7 +151,6 @@ begin
finish_time = $time;
p_out = get_dat;
if (p_exp != p_out) begin
$display("Expected:");
print_jb_point(p_exp);
@ -170,7 +168,7 @@ initial begin
out_if.rdy = 0;
in_if.val = 0;
#(40*CLK_PERIOD);
/*
test(1, {x:256'h79be667ef9dcbbac55a06295ce870b07029bfcdb2dce28d959f2815b16f81798,
y:256'h483ada7726a3c4655da4fbfc0e1108a8fd17b448a68554199c47d08ffb10d4b8,
z:256'h1});
@ -186,11 +184,19 @@ initial begin
test(4, {x:256'h9bae2d5bac61e6ea5de635bca754b2564b7d78c45277cad67e45c4cbbea6e706,
y:256'h34fb8147eed1c0fbe29ead4d6c472eb4ef7b2191fde09e494b2a9845fe3f605e,
z:256'hc327b5d2636b32f27b051e4742b1bbd5324432c1000bfedca4368a29f6654152});
test(1514155, {x:256'h759267d17957f567381462db6e240b75c9f6016091a7427cfbef33c398964a9d,
y:256'hd81ce7034647587a9b0ea5b52ac08c91f5cfae30f4eba2ade7fa68856fc0d691,
z:256'h7c9d27fb2de7927c982792630a0c86f411f2de60e8df44c5e9caff976658009c});
*/
test(256'hbad45c59dcd6d81c6a96b46a678cb893c53decc8e57465bd84efa78676ccc64a,
{x:256'he7e2b526cd2822c69ea688586501db564f28430319cdeb95cb38feb2c77fdfc3,
y:256'h6dda26c3c991cfab33a12ed7b56a0afa17d375d8fa5cabe2d1d143bb21cab887,
z:256'h2f8a851f9aec0f095a31472456a91cca12dd21da865e5a83e5d1b1085835c36c},
{x:256'h808a2c66c5b90fa1477d7820fc57a8b7574cdcb8bd829bdfcf98aa9c41fde3b4, // Not multiplying by generator
y:256'heed249ffde6e46d784cb53b4df8c9662313c1ce8012da56cb061f12e55a32249,
z:256'h1});
#1us $finish();
end
endmodule

24
zcash_fpga/src/tb/secp256k1_top_tb.sv
View File

@ -21,7 +21,7 @@ import common_pkg::*;
import secp256k1_pkg::*;
import zcash_fpga_pkg::*;
localparam CLK_PERIOD = 1000;
localparam CLK_PERIOD = 5000;
logic clk, rst;
@ -61,6 +61,7 @@ begin
integer signed get_len;
logic [common_pkg::MAX_SIM_BYTS*8-1:0] expected, get_dat;
integer start_time, finish_time;
logic [63:0] mm_data;
logic fail = 0;
verify_secp256k1_sig_t verify_secp256k1_sig;
verify_secp256k1_sig_rpl_t verify_secp256k1_sig_rpl;
@ -88,6 +89,12 @@ begin
fail |= (verify_secp256k1_sig_rpl.bm != 0);
fail |= (verify_secp256k1_sig_rpl.index != k);
assert (~fail) else $fatal(1, "%m %t ERROR: test failed :\n%p", $time, verify_secp256k1_sig_rpl);
// Also try reading some RAM values
mm_if.get_data(mm_data, SIG_VER_HASH);
fail |= mm_data != hash[0 +: 64];
assert (~fail) else $fatal(1, "%m %t ERROR: mm_if data read back wrong hash", $time);
$display("test #%d PASSED in %d clocks", integer'(k), (finish_time-start_time)/CLK_PERIOD);
end
@ -100,12 +107,17 @@ initial begin
mm_if.reset_source();
#(40*CLK_PERIOD);
test(1, 256'h4c7dbc46486ad9569442d69b558db99a2612c4f003e6631b593942f531e67fd4,
256'h808a2c66c5b90fa1477d7820fc57a8b7574cdcb8bd829bdfcf98aa9c41fde3b4,
256'h7d4a15dda75c683f002305c2d6ebeebf6c6590f48e128497f118f43250f9924f,
256'hdbe7be814625d52029f94f956147df9347b56e6b5f1cb70bf5d6069ecd8405dd,
256'h3feab712653c82df859affc1c287a5353cbe7ca59b83d6d55d97fc04f243c19f);
test(1, 256'h4c7dbc46486ad9569442d69b558db99a2612c4f003e6631b593942f531e67fd4, // message hash
256'h1375af664ef2b74079687956fd9042e4e547d57c4438f1fc439cbfcb4c9ba8b, // r
256'hde0f72e442f7b5e8e7d53274bf8f97f0674f4f63af582554dbecbb4aa9d5cbcb, // s
256'h808a2c66c5b90fa1477d7820fc57a8b7574cdcb8bd829bdfcf98aa9c41fde3b4, //Qx
256'heed249ffde6e46d784cb53b4df8c9662313c1ce8012da56cb061f12e55a32249); //Qy
test(2, 256'haca448f8093e33286c7d284569feae5f65ae7fa2ea5ce9c46acaad408da61e1f, // message hash
256'hbce4a3be622e3f919f97b03b45e3f32ccdf3dd6bcce40657d8f9fc973ae7b29, // r
256'h6abcd5e40fcee8bca6b506228a2dcae67daa5d743e684c4d3fb1cb77e43b48fe, // s
256'hb661c143ffbbad5acfe16d427767cdc57fb2e4c019a4753ba68cd02c29e4a153, //Qx
256'h6e1fb00fdb9ddd39b55596bfb559bc395f220ae51e46dbe4e4df92d1a5599726); //Qy
#1us $finish();
end