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Updates to barret and multiplier

This commit is contained in:
bsdevlin 2019-03-25 14:55:42 -04:00
parent f95ffeab0c
commit 58fd5658c5
4 changed files with 74 additions and 28 deletions
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35
ip_cores/util/src/rtl/barret_mod.sv
View File

@ -21,19 +21,24 @@
module barret_mod #(
parameter OUT_BITS = 256,
parameter CTL_BITS = 8,
parameter IN_BITS = 512,
parameter [OUT_BITS-1:0] P = 256'hFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFE_BAAEDCE6_AF48A03B_BFD25E8C_D0364141,
parameter K = $clog2(P),
parameter MULTIPLIER = "ACCUM_MULT" // [ACCUM_MULT || KARATSUBA]
parameter MULTIPLIER = "EXTERNAL" // [ACCUM_MULT || KARATSUBA || EXTERNAL]
)(
input i_clk,
input i_rst,
input [IN_BITS-1:0] i_dat,
input i_val,
input [CTL_BITS-1:0] i_ctl,
output logic [CTL_BITS-1:0] o_ctl,
output logic o_rdy,
output logic [OUT_BITS-1:0] o_dat,
output logic o_val,
input i_rdy
input i_rdy,
if_axi_stream.source o_mult_if,
if_axi_stream.sink i_mult_if
);
localparam MAX_IN_BITS = 2*K;
@ -62,6 +67,7 @@ always_ff @ (posedge i_clk) begin
c4 <= 0;
mult_in_if.reset_source();
mult_out_if.rdy <= 1;
o_ctl <= 0;
end else begin
mult_out_if.rdy <= 1;
case (state)
@ -73,6 +79,7 @@ always_ff @ (posedge i_clk) begin
o_rdy <= 0;
state <= WAIT_MULT;
mult_in_if.val <= 1;
o_ctl <= i_ctl;
mult_in_if.dat[0 +: OUT_BITS+1] <= i_dat >> (K-1);
mult_in_if.dat[OUT_BITS+1 +: OUT_BITS+1] <= U;
prev_state <= S0;
@ -125,8 +132,8 @@ generate
if (MULTIPLIER == "ACCUM_MULT") begin: MULTIPLIER_GEN
accum_mult # (
.BITS_A ( OUT_BITS +8 ),
.LEVEL_A ( 6 ), // 32 bit multiply
.LEVEL_B ( 4 )
.LEVEL_A ( 12 ),
.LEVEL_B ( 8 )
)
accum_mult (
.i_clk ( i_clk ),
@ -166,6 +173,26 @@ generate
val <= {val, mult_in_if.val};
end
end
end else if (MULTIPLIER == "EXTERNAL") begin
always_comb begin
o_mult_if.val = mult_in_if.val;
o_mult_if.dat = mult_in_if.dat;
o_mult_if.sop = mult_in_if.sop;
o_mult_if.eop = mult_in_if.eop;
o_mult_if.err = mult_in_if.err;
o_mult_if.mod = mult_in_if.mod;
o_mult_if.ctl = mult_in_if.ctl;
mult_in_if.rdy = o_mult_if.rdy;
mult_out_if.val = i_mult_if.val;
mult_out_if.dat = i_mult_if.dat;
mult_out_if.sop = i_mult_if.sop;
mult_out_if.eop = i_mult_if.eop;
mult_out_if.err = i_mult_if.err;
mult_out_if.mod = i_mult_if.mod;
mult_out_if.ctl = i_mult_if.ctl;
i_mult_if.rdy = mult_out_if.rdy;
end
end else
$fatal(1, "%m ERROR: Unknown multiplier type [%s] in barret_mod.sv", MULTIPLIER);
endgenerate

37
ip_cores/util/src/rtl/karatsuba_ofman_mult.sv
View File

@ -26,6 +26,7 @@ module karatsuba_ofman_mult # (
parameter LEVEL = 1
) (
input i_clk,
input i_rst,
input [BITS-1:0] i_dat_a,
input [BITS-1:0] i_dat_b,
input i_val,
@ -49,24 +50,33 @@ logic [HBITS-1:0] a0_, a1_;
logic [BITS-1:0] m0_, m1_, m2_;
always_ff @ (posedge i_clk) begin
dat_a <= i_dat_a;
dat_b <= i_dat_b;
o_dat <= q;
if (i_rst) begin
o_val <= 0;
val_1 <= 0;
val_ <= 0;
end else begin
if(~o_val || (o_val && i_rdy)) begin
o_val <= val_1;
o_ctl <= ctl_1;
val_ <= val;
val_1 <= val_;
ctl_ <= ctl;
ctl_1 <= ctl_;
val_ <= val;
end
end
end
always_ff @ (posedge i_clk) begin
if(~o_val || (o_val && i_rdy)) begin
o_dat <= q;
o_ctl <= ctl_1;
ctl_1 <= ctl_;
a0_ <= a0;
a1_ <= a1;
m0_ <= m0;
m1_ <= m1;
m2_ <= m2;
dat_a <= i_dat_a;
dat_b <= i_dat_b;
ctl_ <= ctl;
end
end
generate
@ -89,9 +99,11 @@ generate
ctl = i_ctl;
end
always_ff @ (posedge i_clk) begin
if(~o_val || (o_val && i_rdy)) begin
sign <= sign_1;
sign_1 <= sign_;
end
end
end else begin
// pipeline the other non-mult values x clock cycles and add them after multipliers
@ -101,8 +113,10 @@ generate
end
always_ff @ (posedge i_clk) begin
if(~o_val || (o_val && i_rdy)) begin
sign_r <= {sign_r, sign_};
end
end
karatsuba_ofman_mult # (
.BITS ( HBITS ),
@ -111,6 +125,7 @@ generate
)
karatsuba_ofman_mult_m0 (
.i_clk ( i_clk ),
.i_rst ( i_rst ),
.i_dat_a ( dat_a[HBITS +: HBITS] ),
.i_dat_b ( dat_b[HBITS +: HBITS] ),
.i_val ( i_val ),
@ -129,6 +144,7 @@ generate
)
karatsuba_ofman_mult_m2 (
.i_clk ( i_clk ),
.i_rst ( i_rst ),
.i_dat_a ( dat_a[0 +: HBITS] ),
.i_dat_b ( dat_b[0 +: HBITS] ),
.i_val ( i_val ),
@ -147,6 +163,7 @@ generate
)
karatsuba_ofman_mult_m1 (
.i_clk ( i_clk ),
.i_rst ( i_rst ),
.i_dat_a ( a0_ ),
.i_dat_b ( a1_ ),
.i_val ( i_val ),

5
ip_cores/util/src/rtl/packet_arb.sv
View File

@ -23,6 +23,7 @@ module packet_arb # (
parameter DAT_BYTS,
parameter CTL_BITS,
parameter NUM_IN,
parameter OVR_WRT_BIT = CTL_BITS - $clog2(NUM_IN), // What bits in ctl are overwritten with channel id
parameter PIPELINE = 1
) (
input i_clk, i_rst,
@ -58,7 +59,7 @@ generate
dat[g] = i_axi[g].dat;
mod[g] = i_axi[g].mod;
ctl[g] = i_axi[g].ctl;
ctl[g][CTL_BITS-1 -: $clog2(NUM_IN)] = g;
ctl[g][OVR_WRT_BIT +: $clog2(NUM_IN)] = g;
end
end else begin
@ -83,7 +84,7 @@ generate
dat[g] <= i_axi[g].dat;
mod[g] <= i_axi[g].mod;
ctl[g] <= i_axi[g].ctl;
ctl[g][CTL_BITS-1 -: $clog2(NUM_IN)] <= g;
ctl[g][OVR_WRT_BIT +: $clog2(NUM_IN)] <= g;
end
end
end

1
ip_cores/util/src/tb/karatsuba_ofman_mult_tb.sv
View File

@ -57,6 +57,7 @@ karatsuba_ofman_mult # (
)
karatsuba_ofman_mult (
.i_clk ( clk ),
.i_rst ( rst ),
.i_dat_a( in_if.dat[0 +: 256] ),
.i_dat_b( in_if.dat[256 +: 256] ),
.i_val ( in_if.val ),