From 5c513ef8a7d4fbf2ae8b1f9f108467479b7c0810 Mon Sep 17 00:00:00 2001 From: bsdevlin Date: Wed, 15 May 2019 05:24:23 -0400 Subject: [PATCH] update files for AWS --- .../build/scripts/aws_build_dcp_from_cl.bat | 3 + .../scripts/create_dcp_from_cl_windows.tcl | 349 ++++++++++++++++++ aws/zcash_fpga/build/scripts/encrypt.tcl | 14 +- .../build/scripts/synth_zcash_cl_sde.tcl | 146 ++++++++ aws/zcash_fpga/design/zcash_cl_sde.sv | 2 +- 5 files changed, 507 insertions(+), 7 deletions(-) create mode 100644 aws/zcash_fpga/build/scripts/aws_build_dcp_from_cl.bat create mode 100644 aws/zcash_fpga/build/scripts/create_dcp_from_cl_windows.tcl create mode 100644 aws/zcash_fpga/build/scripts/synth_zcash_cl_sde.tcl diff --git a/aws/zcash_fpga/build/scripts/aws_build_dcp_from_cl.bat b/aws/zcash_fpga/build/scripts/aws_build_dcp_from_cl.bat new file mode 100644 index 0000000..b16b105 --- /dev/null +++ b/aws/zcash_fpga/build/scripts/aws_build_dcp_from_cl.bat @@ -0,0 +1,3 @@ +setx VIVADO C:\Xilinx\Vivado\2018.3\bin\vivado.bat + +%VIVADO% -mode batch -nojournal -log vivado.log -source create_dcp_from_cl_windows.tcl -tclargs 19_04_22-123549 DEFAULT 1.4.8 0x04261818 0xF002 0x1D0F 0x1D51 0xFEDC A0 B1 C0 2 0 \ No newline at end of file diff --git a/aws/zcash_fpga/build/scripts/create_dcp_from_cl_windows.tcl b/aws/zcash_fpga/build/scripts/create_dcp_from_cl_windows.tcl new file mode 100644 index 0000000..586e944 --- /dev/null +++ b/aws/zcash_fpga/build/scripts/create_dcp_from_cl_windows.tcl @@ -0,0 +1,349 @@ +# Amazon FPGA Hardware Development Kit +# +# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. + +package require tar + +## Do not edit $TOP +set TOP top_sp + +## Replace with the name of your module +set CL_MODULE zcash_cl_sde + +################################################# +## Command-line Arguments +################################################# +set timestamp [lindex $argv 0] +set strategy [lindex $argv 1] +set hdk_version [lindex $argv 2] +set shell_version [lindex $argv 3] +set device_id [lindex $argv 4] +set vendor_id [lindex $argv 5] +set subsystem_id [lindex $argv 6] +set subsystem_vendor_id [lindex $argv 7] +set clock_recipe_a [lindex $argv 8] +set clock_recipe_b [lindex $argv 9] +set clock_recipe_c [lindex $argv 10] +set uram_option [lindex $argv 11] +set notify_via_sns [lindex $argv 12] + +################################################## +## Flow control variables +################################################## +set cl.synth 1 +set implement 1 + +################################################# +## Generate CL_routed.dcp (Done by User) +################################################# +puts "AWS FPGA Scripts"; +puts "Creating Design Checkpoint from Custom Logic source code"; +puts "HDK Version: $hdk_version"; +puts "Shell Version: $shell_version"; +puts "Vivado Script Name: $argv0"; +puts "Strategy: $strategy"; +puts "PCI Device ID $device_id"; +puts "PCI Vendor ID $vendor_id"; +puts "PCI Subsystem ID $subsystem_id"; +puts "PCI Subsystem Vendor ID $subsystem_vendor_id"; +puts "Clock Recipe A: $clock_recipe_a"; +puts "Clock Recipe B: $clock_recipe_b"; +puts "Clock Recipe C: $clock_recipe_c"; +puts "URAM option: $uram_option"; +puts "Notify when done: $notify_via_sns"; + + +set CL_DIR {C:\Users\bsdevlin\git\aws-fpga\hdk\cl\developer_designs\zcash_fpga} +set HDK_SHELL_DIR {C:\Users\bsdevlin\git\aws-fpga\hdk\common\shell_v04261818} +set HDK_SHELL_DESIGN_DIR {C:\Users\bsdevlin\git\aws-fpga\hdk\common\shell_v04261818\design} +set ZCASH_DIR {C:\Users\bsdevlin\git\zcash-fpga} + +################################################## +### Output Directories used by step_user.tcl +################################################## +set implDir $CL_DIR/build/checkpoints +set rptDir $CL_DIR/build/reports +set cacheDir $HDK_SHELL_DESIGN_DIR/cache/ddr4_phy + +puts "All reports and intermediate results will be time stamped with $timestamp"; + +set_msg_config -id {Chipscope 16-3} -suppress +set_msg_config -string {AXI_QUAD_SPI} -suppress + +# Suppress Warnings +# These are to avoid warning messages that may not be real issues. A developer +# may comment them out if they wish to see more information from warning +# messages. +set_msg_config -id {Common 17-55} -suppress +set_msg_config -id {Designutils 20-1567} -suppress +set_msg_config -id {IP_Flow 19-2162} -suppress +set_msg_config -id {Project 1-498} -suppress +set_msg_config -id {Route 35-328} -suppress +set_msg_config -id {Vivado 12-508} -suppress +set_msg_config -id {Constraints 18-4866} -suppress +set_msg_config -id {filemgmt 56-12} -suppress +set_msg_config -id {Constraints 18-4644} -suppress +set_msg_config -id {Coretcl 2-64} -suppress +set_msg_config -id {Vivado 12-4739} -suppress +set_msg_config -id {Vivado 12-5201} -suppress +set_msg_config -id {DRC CKLD-1} -suppress +set_msg_config -id {IP_Flow 19-2248} -suppress +set_msg_config -id {Opt 31-155} -suppress +set_msg_config -id {Synth 8-115} -suppress +set_msg_config -id {Synth 8-3936} -suppress +set_msg_config -id {Vivado 12-1023} -suppress +set_msg_config -id {Constraints 18-550} -suppress +set_msg_config -id {Synth 8-3295} -suppress +set_msg_config -id {Synth 8-3321} -suppress +set_msg_config -id {Synth 8-3331} -suppress +set_msg_config -id {Synth 8-3332} -suppress +set_msg_config -id {Synth 8-350} -suppress +set_msg_config -id {Synth 8-3848} -suppress +set_msg_config -id {Synth 8-3917} -suppress +set_msg_config -id {Synth 8-6014} -suppress +set_msg_config -id {Vivado 12-1580} -suppress +set_msg_config -id {Constraints 18-619} -suppress +set_msg_config -id {DRC CKLD-2} -suppress +set_msg_config -id {DRC REQP-1853} -suppress +set_msg_config -id {Timing 38-436} -suppress + +puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling the encrypt.tcl."; + +# Check that an email address has been set, else unset notify_via_sns + +if {[string compare $notify_via_sns "1"] == 0} { + if {![info exists env(EMAIL)]} { + puts "AWS FPGA: ([clock format [clock seconds] -format %T]) EMAIL variable empty! Completition notification will *not* be sent!"; + set notify_via_sns 0; + } else { + puts "AWS FPGA: ([clock format [clock seconds] -format %T]) EMAIL address for completion notification set to $env(EMAIL)."; + } +} + +################################################## +### Strategy options +################################################## +switch $strategy { + "BASIC" { + puts "BASIC strategy." + source $HDK_SHELL_DIR\\build\\scripts\\strategy_BASIC.tcl + } + "EXPLORE" { + puts "EXPLORE strategy." + source $HDK_SHELL_DIR\\build\\scripts\\strategy_EXPLORE.tcl + } + "TIMING" { + puts "TIMING strategy." + source $HDK_SHELL_DIR\build\scripts\strategy_TIMING.tcl + } + "CONGESTION" { + puts "CONGESTION strategy." + source $HDK_SHELL_DIR/build/scripts/strategy_CONGESTION.tcl + } + "DEFAULT" { + puts "DEFAULT strategy." + source $HDK_SHELL_DIR\\build\\scripts\\strategy_DEFAULT.tcl + } + default { + puts "$strategy is NOT a valid strategy. Defaulting to strategy DEFAULT." + source $HDK_SHELL_DIR/build/scripts/strategy_DEFAULT.tcl + } +} + +#Encrypt source code +source encrypt.tcl + +#Set the Device Type +source $HDK_SHELL_DIR/build/scripts/device_type.tcl + +#Procedure for running various implementation steps (impl_step) +source $HDK_SHELL_DIR/build/scripts/step_user.tcl -notrace + +######################################## +## Generate clocks based on Recipe +######################################## + +puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe."; + +source $HDK_SHELL_DIR/build/scripts/aws_gen_clk_constraints.tcl + +################################################################# +##### Do not remove this setting. Need to workaround bug in Vivado +################################################################## +set_param hd.clockRoutingWireReduction false + +################################################## +### CL XPR OOC Synthesis +################################################## +if {${cl.synth}} { + source -notrace ./synth_${CL_MODULE}.tcl +} + +################################################## +### Implementation +################################################## +if {$implement} { + + ######################## + # Link Design + ######################## + if {$link} { + ####Create in-memory prjoect and setup IP cache location + create_project -part [DEVICE_TYPE] -in_memory + set_property IP_REPO_PATHS $cacheDir [current_project] + puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Combining Shell and CL design checkpoints"; + add_files $HDK_SHELL_DIR/build/checkpoints/from_aws/SH_CL_BB_routed.dcp + add_files $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp + set_property SCOPED_TO_CELLS {WRAPPER_INST/CL} [get_files $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp] + + #Read the constraints, note *DO NOT* read cl_clocks_aws (clocks originating from AWS shell) + read_xdc [ list \ + $CL_DIR/build/constraints/cl_pnr_user.xdc + ] + set_property PROCESSING_ORDER late [get_files cl_pnr_user.xdc] + + puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running link_design"; + link_design -top $TOP -part [DEVICE_TYPE] -reconfig_partitions {WRAPPER_INST/SH WRAPPER_INST/CL} + + puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - PLATFORM.IMPL==[get_property PLATFORM.IMPL [current_design]]"; + ################################################## + # Apply Clock Properties for Clock Table Recipes + ################################################## + puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Sourcing aws_clock_properties.tcl to apply properties to clocks. "; + + # Apply properties to clocks + source $HDK_SHELL_DIR/build/scripts/aws_clock_properties.tcl + + # Write post-link checkpoint + puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Writing post-link_design checkpoint ${timestamp}.post_link.dcp"; + write_checkpoint -force $CL_DIR/build/checkpoints/${timestamp}.post_link.dcp + } + + ######################## + # CL Optimize + ######################## + if {$opt} { + puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running optimization"; + impl_step opt_design $TOP $opt_options $opt_directive $opt_preHookTcl $opt_postHookTcl + if {$psip} { + impl_step opt_design $TOP "-merge_equivalent_drivers -sweep" + } + } + + ######################## + # CL Place + ######################## + if {$place} { + puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running placement"; + if {$psip} { + append place_options " -fanout_opt" + } + impl_step place_design $TOP $place_options $place_directive $place_preHookTcl $place_postHookTcl + } + + ############################## + # CL Post-Place Optimization + ############################## + if {$phys_opt} { + puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running post-place optimization"; + impl_step phys_opt_design $TOP $phys_options $phys_directive $phys_preHookTcl $phys_postHookTcl + } + + ######################## + # CL Route + ######################## + if {$route} { + puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Routing design"; + impl_step route_design $TOP $route_options $route_directive $route_preHookTcl $route_postHookTcl + } + + ############################## + # CL Post-Route Optimization + ############################## + set SLACK [get_property SLACK [get_timing_paths]] + #Post-route phys_opt will not be run if slack is positive or greater than -200ps. + if {$route_phys_opt && $SLACK > -0.400 && $SLACK < 0} { + puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running post-route optimization"; + impl_step route_phys_opt_design $TOP $post_phys_options $post_phys_directive $post_phys_preHookTcl $post_phys_postHookTcl + } + + ############################## + # Final Implmentation Steps + ############################## + # Report final timing + report_timing_summary -file $CL_DIR/build/reports/${timestamp}.SH_CL_final_timing_summary.rpt + + # This is what will deliver to AWS + puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Writing final DCP to to_aws directory."; + + write_checkpoint -force $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed.dcp + + # Generate debug probes file + write_debug_probes -force -no_partial_ltxfile -file $CL_DIR/build/checkpoints/${timestamp}.debug_probes.ltx + + close_project +} + +# ################################################ +# Create Manifest and Tarball for delivery +# ################################################ + +# Create a zipped tar file, that would be used for createFpgaImage EC2 API + +puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Compress files for sending to AWS. " + +# Create manifest file +set manifest_file [open "$CL_DIR/build/checkpoints/to_aws/${timestamp}.manifest.txt" w] +set hash [lindex [split [exec sha256sum $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed.dcp] ] 0] +set TOOL_VERSION $::env(VIVADO_TOOL_VERSION) +set vivado_version [string range [version -short] 0 5] +puts "vivado_version is $vivado_version\n" + +puts $manifest_file "manifest_format_version=2\n" +puts $manifest_file "pci_vendor_id=$vendor_id\n" +puts $manifest_file "pci_device_id=$device_id\n" +puts $manifest_file "pci_subsystem_id=$subsystem_id\n" +puts $manifest_file "pci_subsystem_vendor_id=$subsystem_vendor_id\n" +puts $manifest_file "dcp_hash=$hash\n" +puts $manifest_file "shell_version=$shell_version\n" +puts $manifest_file "tool_version=v$vivado_version\n" +puts $manifest_file "dcp_file_name=${timestamp}.SH_CL_routed.dcp\n" +puts $manifest_file "hdk_version=$hdk_version\n" +puts $manifest_file "date=$timestamp\n" +puts $manifest_file "clock_recipe_a=$clock_recipe_a\n" +puts $manifest_file "clock_recipe_b=$clock_recipe_b\n" +puts $manifest_file "clock_recipe_c=$clock_recipe_c\n" + +close $manifest_file + +# Delete old tar file with same name +if { [file exists $CL_DIR/build/checkpoints/to_aws/${timestamp}.Developer_CL.tar] } { + puts "Deleting old tar file with same name."; + file delete -force $CL_DIR/build/checkpoints/to_aws/${timestamp}.Developer_CL.tar +} + +# Tar checkpoint to aws +cd $CL_DIR/build/checkpoints +tar::create to_aws/${timestamp}.Developer_CL.tar [glob to_aws/${timestamp}*] + +puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Finished creating final tar file in to_aws directory."; + +if {[string compare $notify_via_sns "1"] == 0} { + puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Calling notification script to send e-mail to $env(EMAIL)"; + exec $env(HDK_COMMON_DIR)/scripts/notify_via_sns.py +} + +puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Build complete."; + + diff --git a/aws/zcash_fpga/build/scripts/encrypt.tcl b/aws/zcash_fpga/build/scripts/encrypt.tcl index a577a1d..d08ce66 100644 --- a/aws/zcash_fpga/build/scripts/encrypt.tcl +++ b/aws/zcash_fpga/build/scripts/encrypt.tcl @@ -18,23 +18,25 @@ # Add check if /build and /build/src_port_encryption directories exist # Add check if the vivado_keyfile exist -set ZCASH_DIR $::env(ZCASH_DIR) -set HDK_SHELL_DIR $::env(HDK_SHELL_DIR) -set HDK_SHELL_DESIGN_DIR $::env(HDK_SHELL_DESIGN_DIR) -set CL_DIR $::env(CL_DIR) +#set ZCASH_DIR $::env(ZCASH_DIR) +#set HDK_SHELL_DIR $::env(HDK_SHELL_DIR) +#set HDK_SHELL_DESIGN_DIR $::env(HDK_SHELL_DESIGN_DIR) +#set CL_DIR $::env(CL_DIR) + set TARGET_DIR $CL_DIR/build/src_post_encryption set UNUSED_TEMPLATES_DIR $HDK_SHELL_DESIGN_DIR/interfaces # Remove any previously encrypted files, that may no longer be used -exec rm -f $TARGET_DIR/* +#exec del -f $TARGET_DIR/* #---- Developr would replace this section with design files ---- ## Change file names and paths below to reflect your CL area. DO NOT include AWS RTL files. + set fileName "${ZCASH_DIR}/zcash_fpga/src/rtl/top/include.f" catch {set fptr [open $fileName r]} ; set contents [read -nonewline $fptr] ;#Read the file contents @@ -99,7 +101,7 @@ file copy -force $CL_DIR/design/axi_prot_chk.sv $TARGET_DIR # Make sure files have write permissions for the encryption -exec chmod +w {*}[glob $TARGET_DIR/*] +#exec chmod +w {*}[glob $TARGET_DIR/*] # encrypt .v/.sv/.vh/inc as verilog files #encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile.txt -lang verilog [glob -nocomplain -- $TARGET_DIR/*.{v,sv}] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc] diff --git a/aws/zcash_fpga/build/scripts/synth_zcash_cl_sde.tcl b/aws/zcash_fpga/build/scripts/synth_zcash_cl_sde.tcl new file mode 100644 index 0000000..2b51a24 --- /dev/null +++ b/aws/zcash_fpga/build/scripts/synth_zcash_cl_sde.tcl @@ -0,0 +1,146 @@ +# Amazon FPGA Hardware Development Kit +# +# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. + +#Param needed to avoid clock name collisions +set_param sta.enableAutoGenClkNamePersistence 0 +set CL_MODULE $CL_MODULE + +create_project -in_memory -part [DEVICE_TYPE] -force + +######################################## +## Generate clocks based on Recipe +######################################## + +puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe."; + +source $HDK_SHELL_DIR/build/scripts/aws_gen_clk_constraints.tcl + +############################# +## Read design files +############################# + +#Convenience to set the root of the RTL directory +set ENC_SRC_DIR $CL_DIR\\build\\src_post_encryption + +puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's Custom Logic files post encryption."; + +#---- User would replace this section ----- + +# Reading the .sv and .v files, as proper designs would not require +# reading .v, .vh, nor .inc files + +read_verilog -sv [glob ../src_post_encryption/*.v] +read_verilog -sv [glob ../src_post_encryption/*.sv] + +#---- End of section replaced by User ---- + +puts "AWS FPGA: Reading AWS Shell design"; + +#Read AWS Design files +read_verilog [ list \ + $HDK_SHELL_DESIGN_DIR/lib/lib_pipe.sv \ + $HDK_SHELL_DESIGN_DIR/lib/bram_2rw.sv \ + $HDK_SHELL_DESIGN_DIR/lib/flop_fifo.sv \ + $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sync.v \ + $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/flop_ccf.sv \ + $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/ccf_ctl.v \ + $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/mgt_acc_axl.sv \ + $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/mgt_gen_axl.sv \ + $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sh_ddr.sv \ + $HDK_SHELL_DESIGN_DIR/interfaces/cl_ports.vh +] + +puts "AWS FPGA: Reading IP blocks"; + +# User IP +read_ip [ list \ + $CL_DIR/ip/axis_dwidth_converter_64_to_8/axis_dwidth_converter_64_to_8.xci \ + $CL_DIR/ip/axis_dwidth_converter_8_to_64/axis_dwidth_converter_8_to_64.xci +] + +puts "AWS FPGA: Generating IP blocks"; + +set_property generate_synth_checkpoint false [get_files axis_dwidth_converter_64_to_8.xci] +set_property generate_synth_checkpoint false [get_files axis_dwidth_converter_8_to_64.xci] + +generate_target all [get_ips axis_dwidth_converter_64_to_8] +generate_target all [get_ips axis_dwidth_converter_8_to_64] + +#Read DDR IP +read_ip [ list \ + $HDK_SHELL_DESIGN_DIR/ip/ddr4_core/ddr4_core.xci +] + +#Read IP for axi register slices +read_ip [ list \ + $HDK_SHELL_DESIGN_DIR/ip/axi_register_slice/axi_register_slice.xci \ + $HDK_SHELL_DESIGN_DIR/ip/axi_register_slice_light/axi_register_slice_light.xci +] + +#Read IP for virtual jtag / ILA/VIO +read_ip [ list \ + $HDK_SHELL_DESIGN_DIR/ip/cl_debug_bridge/cl_debug_bridge.xci \ + $CL_DIR/ip/ila_axi4/ila_axi4.xci \ + $CL_DIR/ip/ila_axi4_512/ila_axi4_512.xci \ + $CL_DIR/ip/ila_axis/ila_axis.xci \ + $CL_DIR/ip/ila_sde_c2h_dm/ila_sde_c2h_dm.xci \ + $CL_DIR/ip/ila_sde_h2c_dm/ila_sde_h2c_dm.xci \ + $CL_DIR/ip/ila_sde_c2h_buf/ila_sde_c2h_buf.xci \ + $CL_DIR/ip/ila_sde_h2c_buf/ila_sde_h2c_buf.xci \ + $CL_DIR/ip/ila_sde_wb/ila_sde_wb.xci \ + $CL_DIR/ip/ila_sde_ps/ila_sde_ps.xci +] + +puts "AWS FPGA: Reading AWS constraints"; + +#Read all the constraints +# +# cl_clocks_aws.xdc - AWS auto-generated clock constraint. ***DO NOT MODIFY*** +# cl_ddr.xdc - AWS provided DDR pin constraints. ***DO NOT MODIFY*** +# cl_synth_user.xdc - Developer synthesis constraints. +read_xdc [ list \ + $CL_DIR/build/constraints/cl_clocks_aws.xdc \ + $HDK_SHELL_DIR/build/constraints/cl_ddr.xdc \ + $HDK_SHELL_DIR/build/constraints/cl_synth_aws.xdc \ + $CL_DIR/build/constraints/cl_synth_user.xdc +] + +#Do not propagate local clock constraints for clocks generated in the SH +set_property USED_IN {synthesis implementation OUT_OF_CONTEXT} [get_files cl_clocks_aws.xdc] +set_property PROCESSING_ORDER EARLY [get_files cl_clocks_aws.xdc] + +######################## +# CL Synthesis +######################## +puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Start design synthesis."; + +update_compile_order -fileset sources_1 +puts "\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\]" +eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive] + +set failval [catch {exec grep "FAIL" failfast.csv}] +if { $failval==0 } { + puts "AWS FPGA: FATAL ERROR--Resource utilization error; check failfast.csv for details" + exit 1 +} + +puts "AWS FPGA: ([clock format [clock seconds] -format %T]) writing post synth checkpoint."; +write_checkpoint -force $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp +#write_checkpoint -force $CL_DIR/build/checkpoints/CL.post_synth.dcp + + +close_project +#Set param back to default value +set_param sta.enableAutoGenClkNamePersistence 1 diff --git a/aws/zcash_fpga/design/zcash_cl_sde.sv b/aws/zcash_fpga/design/zcash_cl_sde.sv index 2b41b4a..2f72ca8 100644 --- a/aws/zcash_fpga/design/zcash_cl_sde.sv +++ b/aws/zcash_fpga/design/zcash_cl_sde.sv @@ -248,7 +248,7 @@ logic rst_if, rst_100, rst_200, rst_300; always_comb begin clk_if = clk_main_a0; clk_100 = clk_main_a0; // 125MHz - clk_200 = clk_extra_a2; // 187MHz + clk_200 = clk_main_a0; // 187MHz clk_300 = clk_extra_b0; // 300MHz end