added cycle count to reply message for secp256k1

This commit is contained in:
bsdevlin 2019-04-11 10:07:11 -04:00
parent 79716cf818
commit 7201c3391b
3 changed files with 8 additions and 6 deletions

View File

@ -19,7 +19,7 @@ class zcash_fpga:
'RESET_FPGA_RPL':int('80000000', 16),
'VERIFY_SECP256K1_SIG_RPL':int('80000101', 16)}
fpga_msg_dict = {fpga_msg_type_dict['VERIFY_SECP256K1_SIG_RPL']:{'name':'VERIFY_SECP256K1_SIG_RPL', 'feilds':[(8, 'index', byt_to_hex), (1, 'bm', byt_to_hex)]},
fpga_msg_dict = {fpga_msg_type_dict['VERIFY_SECP256K1_SIG_RPL']:{'name':'VERIFY_SECP256K1_SIG_RPL', 'feilds':[(8, 'index', byt_to_hex), (1, 'bm', byt_to_hex), (2, 'cycle_cnt', byt_to_hex)]},
fpga_msg_type_dict['FPGA_IGNORE_RPL']:{'name':'FPGA_IGNORE_RPL', 'feilds':[(8, 'ignored_header', byt_to_hex)]},
fpga_msg_type_dict['FPGA_STATUS_RPL']:{'name':'FPGA_STATUS_RPL', 'feilds':[(4, 'version', byt_to_ver), (8, 'build_date', byt_to_str), (8, 'buid_host', byt_to_str), (8, 'cmd_cap', byt_to_hex)]},
fpga_msg_type_dict['RESET_FPGA_RPL']:{'name':'RESET_FPGA_RPL', 'feilds':[]}}

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@ -94,7 +94,7 @@ always_ff @ (posedge i_clk) begin
mult_in_if[2].reset_source();
index <= 0;
timeout <= 0;
end else begin
@ -355,14 +355,15 @@ always_ff @ (posedge i_clk) begin
end
2: begin
if (mult_out_if[2].rdy && mult_out_if[2].val) begin
if(mult_out_if[2].dat != pt_mult0_in_p2.x)
if(mult_out_if[2].dat != pt_mult0_in_p2.x) begin
secp256k1_ver.FAILED_SIG_VER <= 1;
end
cnt <= 3;
end
end
3: begin
cnt <= $bits(verify_secp256k1_sig_rpl_t)/8;
msg <= verify_secp256k1_sig_rpl(secp256k1_ver, index);
msg <= verify_secp256k1_sig_rpl(secp256k1_ver, index, timeout);
secp256k1_state <= FINISHED;
end
endcase

View File

@ -86,6 +86,7 @@ begin
fail |= verify_secp256k1_sig_rpl.hdr.cmd != VERIFY_SECP256K1_SIG_RPL;
fail |= (verify_secp256k1_sig_rpl.bm != 0);
fail |= (verify_secp256k1_sig_rpl.index != k);
fail |= (verify_secp256k1_sig_rpl.cycle_cnt == 0);
assert (~fail) else $fatal(1, "%m %t ERROR: test failed :\n%p", $time, verify_secp256k1_sig_rpl);
$display("test #%d PASSED in %d clocks", integer'(k), (finish_time-start_time)/CLK_PERIOD);
@ -97,7 +98,7 @@ initial begin
out_if.rdy = 0;
in_if.val = 0;
#(40*CLK_PERIOD);
/*
test(1, 256'h4c7dbc46486ad9569442d69b558db99a2612c4f003e6631b593942f531e67fd4, // message hash
256'h1375af664ef2b74079687956fd9042e4e547d57c4438f1fc439cbfcb4c9ba8b, // r
256'hde0f72e442f7b5e8e7d53274bf8f97f0674f4f63af582554dbecbb4aa9d5cbcb, // s
@ -109,7 +110,7 @@ initial begin
256'h6abcd5e40fcee8bca6b506228a2dcae67daa5d743e684c4d3fb1cb77e43b48fe, // s
256'hb661c143ffbbad5acfe16d427767cdc57fb2e4c019a4753ba68cd02c29e4a153, //Qx
256'h6e1fb00fdb9ddd39b55596bfb559bc395f220ae51e46dbe4e4df92d1a5599726); //Qy
*/
test(3, 256'h10, // message hash
256'h10, // r
256'h10, // s