Update to AWS test program and cpp library, needs formatting
This commit is contained in:
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d67ddd5581
commit
736b85cff4
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@ -81,6 +81,7 @@ int main(int argc, char **argv) {
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unsigned int timeout = 0;
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unsigned int read_len = 0;
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uint8_t reply[640];
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bool failed = 0;
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// Process command line args
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{
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int i;
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@ -107,8 +108,63 @@ int main(int argc, char **argv) {
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zcash_fpga& zfpga = zcash_fpga::get_instance();
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zfpga.bls12_381_reset_memory(true, true);
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zfpga.bls12_381_set_curr_inst_slot(0);
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// Test the secp256k1 core
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if ((zfpga.m_command_cap & zcash_fpga::ENB_VERIFY_SECP256K1_SIG) != 0) {
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printf("INFO: Testing secp256k1 core...\n");
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zcash_fpga::verify_secp256k1_sig_t verify_secp256k1_sig;
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memset(&verify_secp256k1_sig, 0, sizeof(zcash_fpga::verify_secp256k1_sig_t));
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verify_secp256k1_sig.hdr.cmd = zcash_fpga::VERIFY_SECP256K1_SIG;
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verify_secp256k1_sig.hdr.len = sizeof(zcash_fpga::verify_secp256k1_sig_t);
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verify_secp256k1_sig.index = 0xa;
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string_to_hex("4c7dbc46486ad9569442d69b558db99a2612c4f003e6631b593942f531e67fd4", (unsigned char *)verify_secp256k1_sig.hash);
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string_to_hex("01375af664ef2b74079687956fd9042e4e547d57c4438f1fc439cbfcb4c9ba8b", (unsigned char *)verify_secp256k1_sig.r);
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string_to_hex("de0f72e442f7b5e8e7d53274bf8f97f0674f4f63af582554dbecbb4aa9d5cbcb", (unsigned char *)verify_secp256k1_sig.s);
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string_to_hex("808a2c66c5b90fa1477d7820fc57a8b7574cdcb8bd829bdfcf98aa9c41fde3b4", (unsigned char *)verify_secp256k1_sig.Qx);
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string_to_hex("eed249ffde6e46d784cb53b4df8c9662313c1ce8012da56cb061f12e55a32249", (unsigned char *)verify_secp256k1_sig.Qy);
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rc = zfpga.write_stream((uint8_t*)&verify_secp256k1_sig, sizeof(zcash_fpga::verify_secp256k1_sig_t));
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fail_on(rc, out, "ERROR: Unable to send verify_secp256k1_sig to FPGA!");
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timeout = 0;
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read_len = 0;
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memset(reply, 0, 512);
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while ((read_len = zfpga.read_stream(reply, 256)) == 0) {
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usleep(1);
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timeout++;
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if (timeout > 1000) {
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printf("ERROR: No reply received, timeout\n");
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failed = true;
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break;
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}
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}
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zcash_fpga::verify_secp256k1_sig_rpl_t verify_secp256k1_sig_rpl;
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verify_secp256k1_sig_rpl = *(zcash_fpga::verify_secp256k1_sig_rpl_t*)reply;
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printf("INFO: verify_secp256k1_sig_rpl.hdr.cmd = 0x%x\n", verify_secp256k1_sig_rpl.hdr.cmd);
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printf("INFO: verify_secp256k1_sig_rpl.bm = 0x%x\n", verify_secp256k1_sig_rpl.bm);
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printf("INFO: verify_secp256k1_sig_rpl.index = 0x%lx\n", verify_secp256k1_sig_rpl.index);
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printf("INFO: verify_secp256k1_sig_rpl.cycle_cnt = 0x%x\n", verify_secp256k1_sig_rpl.cycle_cnt);
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if (verify_secp256k1_sig_rpl.hdr.cmd != zcash_fpga::VERIFY_SECP256K1_SIG_RPL) {
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printf("ERROR: Header type was wrong!\n");
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failed = true;
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}
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if (verify_secp256k1_sig_rpl.bm != 0) {
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printf("ERROR: Signature verification failed!\n"); failed = true;
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}
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if (verify_secp256k1_sig_rpl.index != 0xa) {
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printf("ERROR: Index was wrong!\n"); failed = true; }
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}
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if ((zfpga.m_command_cap & zcash_fpga::ENB_BLS12_381) != 0) {
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printf("INFO: Testing bls12_381 coprocessor...\n");
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zfpga.bls12_381_reset_memory(true, true);
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zfpga.bls12_381_set_curr_inst_slot(0);
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// Test Fp2 point multiplication
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zcash_fpga::bls12_381_data_t data;
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@ -116,7 +172,7 @@ int main(int argc, char **argv) {
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// Store generator points in FPGA
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size_t g1_slot = 64;
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size_t g2_slot = 68;
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size_t g2_slot = 66;
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data.point_type = zcash_fpga::FP2_AF;
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memset(&data, 0x0, sizeof(zcash_fpga::bls12_381_data_t));
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@ -132,13 +188,13 @@ int main(int argc, char **argv) {
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data.point_type = zcash_fpga::FP2_AF;
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memset(&data, 0x0, sizeof(zcash_fpga::bls12_381_data_t));
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string_to_hex("ce5d527727d6e118cc9cdc6da2e351aadfd9baa8cbdd3a76d429a695160d12c923ac9cc3baca289e193548608b82801", (unsigned char *)data.dat);
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string_to_hex("0ce5d527727d6e118cc9cdc6da2e351aadfd9baa8cbdd3a76d429a695160d12c923ac9cc3baca289e193548608b82801", (unsigned char *)data.dat);
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rc = zfpga.bls12_381_set_data_slot(g2_slot + 2, data);
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fail_on(rc, out, "ERROR: Unable to write to FPGA!\n");
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data.point_type = zcash_fpga::FP2_AF;
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memset(&data, 0x0, sizeof(zcash_fpga::bls12_381_data_t));
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string_to_hex("606c4a02ea734cc32acd2b02bc28b99cb3e287e85a763af267492ab572e99ab3f370d275cec1da1aaa9075ff05f79be", (unsigned char *)data.dat);
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string_to_hex("0606c4a02ea734cc32acd2b02bc28b99cb3e287e85a763af267492ab572e99ab3f370d275cec1da1aaa9075ff05f79be", (unsigned char *)data.dat);
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rc = zfpga.bls12_381_set_data_slot(g2_slot + 3, data);
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fail_on(rc, out, "ERROR: Unable to write to FPGA!\n");
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@ -192,7 +248,7 @@ int main(int argc, char **argv) {
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inst.code = zcash_fpga::MUL_ELEMENT;
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inst.a = 1;
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inst.b = 12;
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inst.b = 13;
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inst.c = 1;
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rc = zfpga.bls12_381_set_inst_slot(3, inst);
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fail_on(rc, out, "ERROR: Unable to write to FPGA!\n");
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@ -205,7 +261,7 @@ int main(int argc, char **argv) {
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fail_on(rc, out, "ERROR: Unable to write to FPGA!\n");
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// Start the test
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rc = zcash.bls12_381_set_curr_inst_slot(1);
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rc = zfpga.bls12_381_set_curr_inst_slot(1);
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fail_on(rc, out, "ERROR: Unable to write to FPGA!\n");
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// Wait for interrupts
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@ -219,26 +275,26 @@ int main(int argc, char **argv) {
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timeout++;
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if (timeout > 1000) {
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printf("ERROR: No reply received, timeout\n");
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failed = true;
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break;
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}
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}
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printf("Received data: 0x");
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for (int i = read_len-1; i>=0; i--) printf("%x", reply[i]);
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printf("\n");
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zcash_fpga::bls12_381_interrupt_rpl_t bls12_381_interrupt_rpl;
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// Check it matches the expected values
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bls12_381_interrupt_rpl = &(zcash_fpga::bls12_381_interrupt_rpl_t*)&reply;
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bls12_381_interrupt_rpl = *(zcash_fpga::bls12_381_interrupt_rpl_t*)reply;
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if (bls12_381_interrupt_rpl.data_type != zcash_fpga::SCALAR) {
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printf("ERROR: Interrupt data type was wrong, expected SCALAR, was [%d]\n", bls12_381_interrupt_rpl.data_type);
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failed = true;
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}
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if (bls12_381_interrupt_rpl.index != 123) {
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printf("ERROR: Interrupt index was wrong, expected 123, was [%d]\n", bls12_381_interrupt_rpl.index);
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failed = true;
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}
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if (reply[sizeof(zcash_fpga::bls12_381_interrupt_rpl_t)] != 10) {
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printf("ERROR: Interrupt data was wrong, expected 10, was [%d]\n", reply[sizeof(zcash_fpga::bls12_381_interrupt_rpl_t)]);
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failed = true;
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}
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// Try read second reply - should be point value - 12 slots = 576 bytes
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@ -250,21 +306,20 @@ int main(int argc, char **argv) {
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timeout++;
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if (timeout > 1000) {
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printf("ERROR: No reply received, timeout\n");
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failed = true;
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break;
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}
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}
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printf("Received data: 0x");
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for (int i = read_len-1; i>=0; i--) printf("%x", reply[i]);
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printf("\n");
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// Check it matches the expected values
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bls12_381_interrupt_rpl = &(zcash_fpga::bls12_381_interrupt_rpl_t*)&reply;
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bls12_381_interrupt_rpl = *(zcash_fpga::bls12_381_interrupt_rpl_t*)reply;
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if (bls12_381_interrupt_rpl.data_type != zcash_fpga::FE12) {
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printf("ERROR: Interrupt data type was wrong, expected FE12, was [%d]\n", bls12_381_interrupt_rpl.data_type);
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failed = true;
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}
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if (bls12_381_interrupt_rpl.index != 456) {
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printf("ERROR: Interrupt index was wrong, expected 456, was [%d]\n", bls12_381_interrupt_rpl.index);
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failed = true;
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}
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// Check it matches the value expected from our software model
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string_to_hex("017f1c95cf79b22b459599ea57e613e00cb75e35de1f837814a93b443c54241015ac9761f8fb20a44512ff5cfc04ac7f", (unsigned char *)&exp_res[10*48]);
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string_to_hex("079ab7b345eb23c944c957a36a6b74c37537163d4cbf73bad9751de1dd9c68ef72cb21447e259880f72a871c3eda1b0c", (unsigned char *)&exp_res[11*48]);
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if (memcmp((void*)reply[sizeof(zcash_fpga::bls12_381_interrupt_rpl_t)], (void*)exp_res, 576) != 0) {
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printf("ERROR: Interrupt data was wrong (check data slot 1-13)!");
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if (memcmp((void*)&(reply[sizeof(zcash_fpga::bls12_381_interrupt_rpl_t)]), (void*)exp_res, 12*48) != 0) {
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printf("ERROR: Interrupt data was wrong (check data slot 1-13)!\n");
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failed = true;
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}
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@ -292,15 +348,21 @@ int main(int argc, char **argv) {
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rc = zfpga.bls12_381_get_curr_inst_slot(slot_id);
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fail_on(rc, out, "ERROR: Unable to write to FPGA!\n");
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printf("Data slot is now %d\n", slot_id);
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printf("INFO: Data slot is now %d\n", slot_id);
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// Print out data slots
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for(int i = 0; i < 14; i++) {
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for(int i = 0; i < 13; i++) {
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zfpga.bls12_381_get_data_slot(i, data);
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printf("slot %d, pt: %d, data:0x", i, data.point_type);
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for(int j = 47; j >= 0; j--) printf("%02x", data.dat[j]);
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printf("\n");
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}
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}
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if (!failed) {
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printf("INFO: All tests passed!\n");
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} else {
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printf("ERROR: Tests did not pass!\n");
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}
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return rc;
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out:
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@ -98,6 +98,7 @@ int zcash_fpga::init_fpga(int slot_id) {
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rc = get_status(status_rpl);
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fail_on(rc, out, "ERROR: Unable to get FPGA status!");
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m_command_cap = *(command_cap_e*)&status_rpl.cmd_cap;
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printf("INFO: FPGA version: 0x%x, built on 0x%lx\n", status_rpl.version, status_rpl.build_date);
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printf("INFO: FPGA capability register: 0x%lx [ENB_VERIFY_EQUIHASH_200_9: %d, ENB_VERIFY_EQUIHASH_144_5 %d, ENB_VERIFY_SECP256K1_SIG %d, ENB_BLS12_381 %d]\n",
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@ -262,6 +263,7 @@ int zcash_fpga::write_stream(uint8_t* data, unsigned int len) {
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printf("INFO: write_stream::Wrote %d bytes of data\n", len);
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usleep(1);
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// Check transmit complete bit and reset it
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rc = fpga_pci_peek(m_pci_bar_handle_bar0, AXI_FIFO_OFFSET, &rdata);
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@ -47,15 +47,15 @@ class zcash_fpga {
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RESET_FPGA = 0x00000000,
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FPGA_STATUS = 0x00000001,
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VERIFY_EQUIHASH = 0x00000100,
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VERIFY_SECP256K1_SIG = 0x00000200,
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VERIFY_SECP256K1_SIG = 0x00000101,
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// Replies from the FPGA
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RESET_FPGA_RPL = 0x80000000,
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FPGA_STATUS_RPL = 0x80000001,
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FPGA_IGNORE_RPL = 0x80000002,
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VERIFY_EQUIHASH_RPL = 0x80000100,
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VERIFY_SECP256K1_SIG_RPL = 0x80000200,
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BLS12_381_INTERRUPT_RPL = 0x80000300
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VERIFY_SECP256K1_SIG_RPL = 0x80000101,
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BLS12_381_INTERRUPT_RPL = 0x80000200
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} command_t;
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typedef enum : uint8_t {
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@ -141,6 +141,31 @@ class zcash_fpga {
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uint8_t padding[3];
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} bls12_381_interrupt_rpl_t;
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typedef enum : uint8_t {
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TIMEOUT_FAIL = 0,
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FAILED_SIG_VER = 1,
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X_INFINITY_POINT = 2,
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OUT_OF_RANGE_S = 3,
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OUT_OF_RANGE_R = 4
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} secp256k1_ver_t;
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typedef struct __attribute__((__packed__)) {
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header_t hdr;
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uint64_t index;
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uint64_t s[4];
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uint64_t r[4];
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uint64_t hash[4];
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uint64_t Qx[4];
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uint64_t Qy[4];
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} verify_secp256k1_sig_t;
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typedef struct __attribute__((__packed__)) {
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header_t hdr;
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uint64_t index;
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secp256k1_ver_t bm;
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uint16_t cycle_cnt;
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} verify_secp256k1_sig_rpl_t;
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private:
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static const uint16_t s_pci_vendor_id = 0x1D0F; /* Amazon PCI Vendor ID */
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static const uint16_t s_pci_device_id = 0xF000; /* PCI Device ID preassigned by Amazon for F1 applications */
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@ -195,6 +220,8 @@ class zcash_fpga {
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int read_stream(uint8_t* data, unsigned int size);
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int write_stream(uint8_t* data, unsigned int len);
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command_cap_e m_command_cap;
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private:
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/*
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* This connects to the FPGA and is called by the constructor on the first call of get_instance()
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