Adding bls12-381 pairing wrapper to hold all arithmetic for pairing,
will consolidate the bls12-381 logic at a later time.
This commit is contained in:
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481944c547
commit
789a33351d
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/*
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Wrapper for the bls12-381 pairing engine.
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Copyright (C) 2019 Benjamin Devlin and Zcash Foundation
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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module bls12_381_pairing_wrapper
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import bls12_381_pkg::*;
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#(
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parameter type FE_TYPE = fe_t,
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parameter type FE2_TYPE = fe2_t,
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parameter type FE6_TYPE = fe6_t,
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parameter type FE12_TYPE = fe12_t,
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parameter type G1_FP_AF_TYPE = af_point_t,
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parameter type G2_FP_AF_TYPE = fp2_af_point_t,
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parameter type G2_FP_JB_TYPE = fp2_jb_point_t,
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parameter CTL_BITS = 32,
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parameter OVR_WRT_BIT = 8 // We override 36 bits from here
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)(
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input i_clk, i_rst,
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// Inputs
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input i_val,
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output logic o_rdy,
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input G1_FP_AF_TYPE i_g1_af,
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input G2_FP_AF_TYPE i_g2_af,
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// Outputs
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output logic o_val,
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input i_rdy,
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output FE12_TYPE o_fe12,
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// Interface to FE_TYPE multiplier (mod P)
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if_axi_stream.source o_mul_fe_if,
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if_axi_stream.sink i_mul_fe_if,
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// Interface to FE_TYPE adder (mod P)
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if_axi_stream.source o_add_fe_if,
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if_axi_stream.sink i_add_fe_if,
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// Interface to FE_TYPE subtractor (mod P)
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if_axi_stream.source o_sub_fe_if,
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if_axi_stream.sink i_sub_fe_if
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);
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if_axi_stream #(.DAT_BITS(2*$bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) mul_fe_in_if[1:0](i_clk);
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if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) mul_fe_out_if[1:0](i_clk);
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if_axi_stream #(.DAT_BITS(2*$bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) add_fe_in_if[1:0] (i_clk);
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if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) add_fe_out_if[1:0] (i_clk);
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if_axi_stream #(.DAT_BITS(2*$bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) sub_fe_in_if[1:0] (i_clk);
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if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) sub_fe_out_if[1:0] (i_clk);
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if_axi_stream #(.DAT_BITS(2*$bits(FE2_TYPE)), .CTL_BITS(CTL_BITS)) mul_fe2_o_if[2:0](i_clk);
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if_axi_stream #(.DAT_BITS($bits(FE2_TYPE)), .CTL_BITS(CTL_BITS)) mul_fe2_i_if[2:0](i_clk);
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if_axi_stream #(.DAT_BITS(2*$bits(FE2_TYPE)), .CTL_BITS(CTL_BITS)) add_fe2_o_if[2:0](i_clk);
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if_axi_stream #(.DAT_BITS($bits(FE2_TYPE)), .CTL_BITS(CTL_BITS)) add_fe2_i_if[2:0](i_clk);
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if_axi_stream #(.DAT_BITS(2*$bits(FE2_TYPE)), .CTL_BITS(CTL_BITS)) sub_fe2_o_if[2:0](i_clk);
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if_axi_stream #(.DAT_BITS($bits(FE2_TYPE)), .CTL_BITS(CTL_BITS)) sub_fe2_i_if[2:0](i_clk);
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if_axi_stream #(.DAT_BITS($bits(FE2_TYPE)), .CTL_BITS(CTL_BITS)) mnr_fe2_o_if[2:0](i_clk);
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if_axi_stream #(.DAT_BITS($bits(FE2_TYPE)), .CTL_BITS(CTL_BITS)) mnr_fe2_i_if[2:0](i_clk);
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if_axi_stream #(.DAT_BYTS((2*$bits(FE6_TYPE)+7)/8), .CTL_BITS(CTL_BITS)) mul_fe6_o_if(i_clk);
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if_axi_stream #(.DAT_BYTS(($bits(FE6_TYPE)+7)/8), .CTL_BITS(CTL_BITS)) mul_fe6_i_if(i_clk);
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if_axi_stream #(.DAT_BYTS((2*$bits(FE6_TYPE)+7)/8), .CTL_BITS(CTL_BITS)) add_fe6_o_if(i_clk);
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if_axi_stream #(.DAT_BYTS(($bits(FE6_TYPE)+7)/8), .CTL_BITS(CTL_BITS)) add_fe6_i_if(i_clk);
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if_axi_stream #(.DAT_BYTS((2*$bits(FE6_TYPE)+7)/8), .CTL_BITS(CTL_BITS)) sub_fe6_o_if(i_clk);
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if_axi_stream #(.DAT_BYTS(($bits(FE6_TYPE)+7)/8), .CTL_BITS(CTL_BITS)) sub_fe6_i_if(i_clk);
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if_axi_stream #(.DAT_BITS($bits(FE6_TYPE)), .CTL_BITS(CTL_BITS)) mnr_fe6_o_if(i_clk);
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if_axi_stream #(.DAT_BITS($bits(FE6_TYPE)), .CTL_BITS(CTL_BITS)) mnr_fe6_i_if(i_clk);
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if_axi_stream #(.DAT_BYTS((2*$bits(FE12_TYPE)+7)/8), .CTL_BITS(CTL_BITS)) mul_fe12_o_if(i_clk);
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if_axi_stream #(.DAT_BYTS(($bits(FE12_TYPE)+7)/8), .CTL_BITS(CTL_BITS)) mul_fe12_i_if(i_clk);
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if_axi_stream #(.DAT_BYTS((2*$bits(FE12_TYPE)+7)/8), .CTL_BITS(CTL_BITS)) add_fe12_o_if(i_clk);
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if_axi_stream #(.DAT_BYTS(($bits(FE12_TYPE)+7)/8), .CTL_BITS(CTL_BITS)) add_fe12_i_if(i_clk);
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if_axi_stream #(.DAT_BYTS((2*$bits(FE12_TYPE)+7)/8), .CTL_BITS(CTL_BITS)) sub_fe12_o_if(i_clk);
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if_axi_stream #(.DAT_BYTS(($bits(FE12_TYPE)+7)/8), .CTL_BITS(CTL_BITS)) sub_fe12_i_if(i_clk);
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always_comb begin
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add_fe12_o_if.reset_source();
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add_fe12_i_if.rdy = 0;
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sub_fe12_o_if.reset_source();
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sub_fe12_i_if.rdy = 0;
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end
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ec_fe2_arithmetic #(
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.FE_TYPE ( FE_TYPE ),
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.FE2_TYPE ( FE2_TYPE ),
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.CTL_BITS ( CTL_BITS ),
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.OVR_WRT_BIT ( OVR_WRT_BIT + 0 )
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)
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ec_fe2_arithmetic (
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.i_clk ( i_clk ),
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.i_rst ( i_rst ),
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.i_fp_mode ( 1'd0 ),
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.o_mul_fe_if ( mul_fe_in_if[0] ),
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.i_mul_fe_if ( mul_fe_out_if[0] ),
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.o_add_fe_if ( add_fe_in_if[0] ),
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.i_add_fe_if ( add_fe_out_if[0] ),
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.o_sub_fe_if ( sub_fe_in_if[0] ),
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.i_sub_fe_if ( sub_fe_out_if[0] ),
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.o_mul_fe2_if ( mul_fe2_i_if[2] ),
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.i_mul_fe2_if ( mul_fe2_o_if[2] ),
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.o_add_fe2_if ( add_fe2_i_if[2] ),
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.i_add_fe2_if ( add_fe2_o_if[2] ),
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.o_sub_fe2_if ( sub_fe2_i_if[2] ),
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.i_sub_fe2_if ( sub_fe2_o_if[2] )
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);
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ec_fe6_arithmetic #(
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.FE2_TYPE ( FE2_TYPE ),
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.FE6_TYPE ( FE6_TYPE ),
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.OVR_WRT_BIT ( OVR_WRT_BIT + 4 ),
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.CTL_BITS ( CTL_BITS )
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)
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ec_fe6_arithmetic (
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.i_clk ( i_clk ),
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.i_rst ( i_rst ),
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.o_mul_fe2_if ( mul_fe2_o_if[0] ),
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.i_mul_fe2_if ( mul_fe2_i_if[0] ),
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.o_add_fe2_if ( add_fe2_o_if[0] ),
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.i_add_fe2_if ( add_fe2_i_if[0] ),
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.o_sub_fe2_if ( sub_fe2_o_if[0] ),
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.i_sub_fe2_if ( sub_fe2_i_if[0] ),
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.o_mnr_fe2_if ( mnr_fe2_i_if[0] ),
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.i_mnr_fe2_if ( mnr_fe2_o_if[0] ),
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.o_mul_fe6_if ( mul_fe6_i_if ),
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.i_mul_fe6_if ( mul_fe6_o_if ),
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.o_add_fe6_if ( add_fe6_i_if ),
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.i_add_fe6_if ( add_fe6_o_if ),
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.o_sub_fe6_if ( sub_fe6_i_if ),
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.i_sub_fe6_if ( sub_fe6_o_if )
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);
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ec_fe12_arithmetic #(
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.FE6_TYPE ( FE6_TYPE ),
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.FE12_TYPE ( FE12_TYPE ),
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.OVR_WRT_BIT ( OVR_WRT_BIT + 10 ),
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.CTL_BITS ( CTL_BITS )
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)
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ec_fe12_arithmetic (
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.i_clk ( i_clk ),
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.i_rst ( i_rst ),
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.o_mul_fe6_if ( mul_fe6_o_if ),
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.i_mul_fe6_if ( mul_fe6_i_if ),
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.o_add_fe6_if ( add_fe6_o_if ),
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.i_add_fe6_if ( add_fe6_i_if ),
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.o_sub_fe6_if ( sub_fe6_o_if ),
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.i_sub_fe6_if ( sub_fe6_i_if ),
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.o_mnr_fe6_if ( mnr_fe6_o_if ),
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.i_mnr_fe6_if ( mnr_fe6_i_if ),
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.o_mul_fe12_if ( mul_fe12_i_if ),
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.i_mul_fe12_if ( mul_fe12_o_if ),
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.o_add_fe12_if ( add_fe12_i_if ),
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.i_add_fe12_if ( add_fe12_o_if ),
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.o_sub_fe12_if ( sub_fe12_i_if ),
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.i_sub_fe12_if ( sub_fe12_o_if )
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);
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fe2_mul_by_nonresidue #(
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.FE_TYPE ( FE_TYPE )
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)
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fe2_mul_by_nonresidue (
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.i_clk ( i_clk ),
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.i_rst ( i_rst ),
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.o_mnr_fe2_if ( mnr_fe2_o_if[2] ),
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.i_mnr_fe2_if ( mnr_fe2_i_if[2] ),
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.o_add_fe_if ( add_fe_in_if[1] ),
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.i_add_fe_if ( add_fe_out_if[1] ),
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.o_sub_fe_if ( sub_fe_in_if[1] ),
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.i_sub_fe_if ( sub_fe_out_if[1] )
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);
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fe6_mul_by_nonresidue #(
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.FE2_TYPE ( FE2_TYPE )
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)
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fe6_mul_by_nonresidue (
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.i_clk ( i_clk ),
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.i_rst ( i_rst ),
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.o_mnr_fe6_if ( mnr_fe6_i_if ),
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.i_mnr_fe6_if ( mnr_fe6_o_if ),
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.o_mnr_fe2_if ( mnr_fe2_i_if[1] ),
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.i_mnr_fe2_if ( mnr_fe2_o_if[1] )
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);
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bls12_381_pairing #(
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.FE_TYPE ( FE_TYPE ),
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.FE2_TYPE ( FE2_TYPE ),
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.FE12_TYPE ( FE12_TYPE ),
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.CTL_BITS ( CTL_BITS ),
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.OVR_WRT_BIT ( OVR_WRT_BIT + 16 )
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)
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bls12_381_pairing (
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.i_clk ( i_clk ),
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.i_rst ( i_rst ),
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.i_val ( i_val ),
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.o_rdy ( o_rdy ),
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.i_g1_af ( i_g1_af ),
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.i_g2_af ( i_g2_af ),
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.o_val ( o_val ),
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.i_rdy ( i_rdy ),
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.o_fe12 ( o_fe12 ),
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.o_mul_fe2_if ( mul_fe2_o_if[1] ),
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.i_mul_fe2_if ( mul_fe2_i_if[1] ),
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.o_add_fe2_if ( add_fe2_o_if[1] ),
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.i_add_fe2_if ( add_fe2_i_if[1] ),
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.o_sub_fe2_if ( sub_fe2_o_if[1] ),
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.i_sub_fe2_if ( sub_fe2_i_if[1] ),
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.o_mul_fe12_if ( mul_fe12_o_if ),
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.i_mul_fe12_if ( mul_fe12_i_if ),
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.o_mul_fe_if ( mul_fe_in_if[1] ),
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.i_mul_fe_if ( mul_fe_out_if[1] )
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);
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resource_share # (
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.NUM_IN ( 2 ),
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.DAT_BITS ( 2*$bits(FE_TYPE) ),
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.CTL_BITS ( CTL_BITS ),
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.OVR_WRT_BIT ( OVR_WRT_BIT + 32 ),
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.PIPELINE_IN ( 1 ),
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.PIPELINE_OUT ( 0 )
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)
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resource_share_sub (
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.i_clk ( i_clk ),
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.i_rst ( i_rst ),
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.i_axi ( sub_fe_in_if[1:0] ),
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.o_res ( o_sub_fe_if ),
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.i_res ( i_sub_fe_if ),
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.o_axi ( sub_fe_out_if[1:0] )
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);
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resource_share # (
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.NUM_IN ( 2 ),
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.DAT_BITS ( 2*$bits(FE_TYPE) ),
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.CTL_BITS ( CTL_BITS ),
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.OVR_WRT_BIT ( OVR_WRT_BIT + 32 ),
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.PIPELINE_IN ( 1 ),
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.PIPELINE_OUT ( 0 )
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)
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resource_share_add (
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.i_clk ( i_clk ),
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.i_rst ( i_rst ),
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.i_axi ( add_fe_in_if[1:0] ),
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.o_res ( o_add_fe_if ),
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.i_res ( i_add_fe_if ),
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.o_axi ( add_fe_out_if[1:0] )
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);
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resource_share # (
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.NUM_IN ( 2 ),
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.DAT_BITS ( 2*$bits(FE_TYPE) ),
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.CTL_BITS ( CTL_BITS ),
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.OVR_WRT_BIT ( OVR_WRT_BIT + 32 ),
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.PIPELINE_IN ( 1 ),
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.PIPELINE_OUT ( 0 )
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)
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resource_share_mul (
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.i_clk ( i_clk ),
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.i_rst ( i_rst ),
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.i_axi ( mul_fe_in_if[1:0] ),
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.o_res ( o_mul_fe_if ),
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.i_res ( i_mul_fe_if ),
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.o_axi ( mul_fe_out_if[1:0] )
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);
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resource_share # (
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.NUM_IN ( 2 ),
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.DAT_BITS ( $bits(FE2_TYPE) ),
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.CTL_BITS ( CTL_BITS ),
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.OVR_WRT_BIT ( OVR_WRT_BIT + 34 ),
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.PIPELINE_IN ( 1 ),
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.PIPELINE_OUT ( 0 )
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)
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resource_share_mnr (
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.i_clk ( i_clk ),
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.i_rst ( i_rst ),
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.i_axi ( mnr_fe2_i_if[1:0] ),
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.o_res ( mnr_fe2_i_if[2] ),
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.i_res ( mnr_fe2_o_if[2] ),
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.o_axi ( mnr_fe2_o_if[1:0] )
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);
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resource_share # (
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.NUM_IN ( 2 ),
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.DAT_BITS ( 2*$bits(FE2_TYPE) ),
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.CTL_BITS ( CTL_BITS ),
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.OVR_WRT_BIT ( OVR_WRT_BIT + 34 ),
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.PIPELINE_IN ( 1 ),
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.PIPELINE_OUT ( 0 )
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)
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resource_share_fe2_add (
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.i_clk ( i_clk ),
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.i_rst ( i_rst ),
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.i_axi ( add_fe2_o_if[1:0] ),
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.o_res ( add_fe2_o_if[2] ),
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.i_res ( add_fe2_i_if[2] ),
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.o_axi ( add_fe2_i_if[1:0] )
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);
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resource_share # (
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.NUM_IN ( 2 ),
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.DAT_BITS ( 2*$bits(FE2_TYPE) ),
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.CTL_BITS ( CTL_BITS ),
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.OVR_WRT_BIT ( OVR_WRT_BIT + 34 ),
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.PIPELINE_IN ( 1 ),
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.PIPELINE_OUT ( 0 )
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)
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resource_share_fe2_sub (
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.i_clk ( i_clk ),
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.i_rst ( i_rst ),
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.i_axi ( sub_fe2_o_if[1:0] ),
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.o_res ( sub_fe2_o_if[2] ),
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.i_res ( sub_fe2_i_if[2] ),
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.o_axi ( sub_fe2_i_if[1:0] )
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);
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resource_share # (
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.NUM_IN ( 2 ),
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.DAT_BITS ( 2*$bits(FE2_TYPE) ),
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.CTL_BITS ( CTL_BITS ),
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.OVR_WRT_BIT ( OVR_WRT_BIT + 34 ),
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.PIPELINE_IN ( 1 ),
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.PIPELINE_OUT ( 0 )
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)
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resource_share_fe2_mul (
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.i_clk ( i_clk ),
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.i_rst ( i_rst ),
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.i_axi ( mul_fe2_o_if[1:0] ),
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.o_res ( mul_fe2_o_if[2] ),
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.i_res ( mul_fe2_i_if[2] ),
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.o_axi ( mul_fe2_i_if[1:0] )
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);
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endmodule
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