diff --git a/bittware_xupvvh/ip/axi_uartlite_0/axi_uartlite_0.xci b/bittware_xupvvh/ip/axi_uartlite_0/axi_uartlite_0.xci new file mode 100644 index 0000000..7555851 --- /dev/null +++ b/bittware_xupvvh/ip/axi_uartlite_0/axi_uartlite_0.xci @@ -0,0 +1,116 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_uartlite_0 + + + + 100000000 + 0 + 0.000 + 0 + 1 + 4 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 921600 + 8 + virtexuplusHBM + 0 + 300000000 + 0 + 921600 + 8 + 0 + 300000000 + 300 + 0 + axi_uartlite_0 + No_Parity + Custom + false + virtexuplusHBM + + + xcvu37p + fsvh2892 + VERILOG + es1 + MIXED + -2 + E + TRUE + TRUE + IP_Flow + 22 + TRUE + . + + . + 2018.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bittware_xupvvh/ip/clk_wiz_0/clk_wiz_0.xci b/bittware_xupvvh/ip/clk_wiz_0/clk_wiz_0.xci new file mode 100644 index 0000000..36ff8f8 --- /dev/null +++ b/bittware_xupvvh/ip/clk_wiz_0/clk_wiz_0.xci @@ -0,0 +1,721 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_wiz_0 + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0.000 + 0 + 0 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 149.99 + 0000 + 0000 + 100.000 + 0000 + 0000 + 200.000 + BUFG + 50.0 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0000 + 0000 + 300.000 + BUFG + 50.0 + false + 200.000 + 0.000 + 50.000 + 200.000 + 0.000 + 1 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.0 + false + 300.000 + 0.000 + 50.000 + 300.000 + 0.000 + 1 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + clk_out100 + clk_out200 + clk_out300 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 0.5 + 0.3333333333333333 + 1.0 + 1.0 + 1.0 + 1.0 + dout + drdy + dwe + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________100.000____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 12.000 + 0.000 + FALSE + 10.000 + 10.000 + 12.000 + 0.5 + 0.000 + FALSE + 6 + 0.5 + 0.000 + FALSE + 4 + 0.5 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + AUTO + 1 + None + 0.010 + 0.010 + FALSE + 3 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + clk_out100___100.000______0.000______50.0______115.831_____87.180 + clk_out200___200.000______0.000______50.0______102.086_____87.180 + clk_out300___300.000______0.000______50.0_______94.862_____87.180 + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + LATENCY + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in1 + MMCM + AUTO + 100.000 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + clk_wiz_0 + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 0.010 + 149.99 + 0.010 + Buffer + 115.831 + false + 87.180 + 50.000 + 100.000 + 0.000 + 1 + true + Buffer + 102.086 + false + 87.180 + 50.000 + 200.000 + 0.000 + 1 + true + Buffer + 94.862 + false + 87.180 + 50.000 + 300.000 + 0.000 + 1 + true + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk_out100 + false + clk_out200 + false + clk_out300 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + clk_wiz_0 + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 12.000 + 0.000 + false + 10.000 + 10.000 + 12.000 + 0.5 + 0.000 + false + 6 + 0.5 + 0.000 + false + 4 + 0.5 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + AUTO + 1 + None + 0.010 + 0.010 + false + 3 + false + false + LATENCY + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + MMCM + mmcm_adv + 100.000 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + false + false + false + true + false + false + false + false + false + false + virtexuplusHBM + + + xcvu37p + fsvh2892 + VERILOG + es1 + MIXED + -2 + E + TRUE + TRUE + IP_Flow + 2 + TRUE + . + + . + 2018.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bittware_xupvvh/src/rtl/bittware_xupvvh_top.sv b/bittware_xupvvh/src/rtl/bittware_xupvvh_top.sv index 7240820..f46c785 100644 --- a/bittware_xupvvh/src/rtl/bittware_xupvvh_top.sv +++ b/bittware_xupvvh/src/rtl/bittware_xupvvh_top.sv @@ -1,315 +1,131 @@ -//************************************************************************** -//************* BittWare Incorporated ************* -//************* 45 S. Main Street, Concord, NH 03301 ************* -//************************************************************************** -// LEGAL NOTICE: -// Copyright (c) 2018 BittWare, Inc. -// The user is hereby granted a non-exclusive license to use and or -// modify this code provided that it runs on BittWare hardware. -// Usage of this code on non-BittWare hardware without the express -// written permission of BittWare is strictly prohibited. -// -// E-mail: support@bittware.com Tel: 603-226-0404 -//************************************************************************** - -//# Created by: Jeff Sanders -//# Date: 20 Jun 2018 -/// -//************************************************************************** -// pcie_base: Default PCIe-based design incorporating the following functionality: -// - PCIe Gen3x16 interface w/integrated PCIe-to-AXI4 conversion (within IPI subsystem) -// - SPI controller (within IPI subsystem) -// - I2C controller (within IPI subsystem) -// - 16550-compatible UART (within IPI subsystem) -// - STARTUPE3 primitive configured to allow writes to QSPI flash -// -// PCIe address map: (BAR0, 32-bit) -// 0x0000: CSR (0x0=Version(rd);LED[2:0](wr), 0x4=UAR timestamp(rd), 0x8=CSR(rd/wr)) -// 0x1100: SPI core -// 0x2200: I2C Core -// 0x3300: UART Core -// 0x4000: 4KB scratchpad BRAM -// -//************************************************************************** - `timescale 1ps/1ps - -`define DEV_SEL_HI_BIT 11 -`define DEV_SEL_LO_BIT 8 -`define VERSION_REG 32'h00600000 - -module bittware_xupvvh_top ( - led_pins, - pcie_7x_mgt_rxn, - pcie_7x_mgt_rxp, - pcie_7x_mgt_txn, - pcie_7x_mgt_txp, - prog_b5_p, - prog_b5_n, - avr_rxd, - avr_txd, - usb_rxd, - usb_txd, - i2c_sda, - i2c_scl, - FPGA_I2C_MASTER_L, - QSFP_CTL_EN, - SAS_CTL_EN, - sys_clkp, - sys_clkn, - sys_reset_l); - - //####### Misc. Board-specific ####### - output [3:0]led_pins; // On-board LEDs 0-3 - output FPGA_I2C_MASTER_L; // Drive high to allow BMC to control QSFPs - output QSFP_CTL_EN; // Drive high for normal operation - output SAS_CTL_EN; // Drive high for normal operation - //####### PCIe Interface ####### - input [15:0]pcie_7x_mgt_rxn; - input [15:0]pcie_7x_mgt_rxp; - output [15:0]pcie_7x_mgt_txn; - output [15:0]pcie_7x_mgt_txp; - //####### I2C and UART I/F's ####### - input avr_txd; // Tx UART data from the AVR - output avr_rxd; // Rx UART data to the AVR - inout i2c_sda; // I2C biderectional data - inout i2c_scl; // I2C clock - input usb_uart_txd; // Tx UART data from the USB - output logic usb_uart_rxd; // Rx UART data to the USB - //####### Clocks & Reset ####### - input sys_clkp; // PCIe reference clock - input sys_clkn; - input prog_b5_p; - input prog_b5_n; - input sys_reset_l; // PCIe PERSTN - - - wire [3:0] spi_in; - wire [3:0] spi_out; - wire [3:0] spi_tri; - wire spi_sel; - wire spi_clk_o; - wire spi_clk_t; - reg spi_cs_l; - reg [31:0] clk_cnt; - reg [3:0] led_q; - wire [3:0] memtest_ok; - reg led_test_reg; - reg [3:0] qsfp_rst_reg; - reg [3:0] qsfp_lp_reg; - reg [3:0] qsfp_sel_oh; - reg [3:0] qsfp_i2c_ctri_vec; - reg [3:0] qsfp_i2c_dtri_vec; - reg [3:0] qsfp_i2c_cin_vec; - reg [3:0] qsfp_i2c_din_vec; - wire [31:0] CSR_awaddr; - wire [31:0] CSR_wdata; - wire [31:0] CSR_araddr; - reg [31:0] CSR_rdata; - reg CSR_rvalid; - reg CSR_awready; - reg CSR_arready; - reg CSR_wready; - reg CSR_bvalid; - wire CSR_wdecode; - wire CSR_rdecode; - wire csr_ren; - wire csr_wen; - wire sys_clk; - wire sys_clk_gt; - wire [31:0] UAR_DATA; - - - IBUFDS_GTE4 refclk_ibuf (.O(sys_clk_gt), .ODIV2(sys_clk), .I(sys_clkp), .CEB(1'b0), .IB(sys_clkn)); - - // STARTUPE3 block: Allows FPGA logic connections to dedicated config. pins - // From the UltraScale Configuration Guide: - // FCSBO: FPGA logic signal to external FCS_B configuration pin. FCSBO allows user - // control of FCS_B pin for Flash access. - // USRCCLKO (User CCLK input). USRCCLKO is an input from the FPGA logic. USERCCLKO drives a custom, - // FPGA-generated clock frequency onto the external FPGA CCLK pin. This is useful for - // post-configuration access of external SPI flash devices. - - // STARTUPE3: STARTUP Block - // UltraScale - // Xilinx HDL Libraries Guide, version 2014.4 - STARTUPE3 #( - .PROG_USR("FALSE") // Activate program event security feature. Requires encrypted bitstreams. - ) - STARTUPE3_inst ( - .CFGCLK(), // 1-bit output: Configuration main clock output - .CFGMCLK(), // 1-bit output: Configuration internal oscillator clock output - .DI(spi_in), // 4-bit output: Allow receiving on the D input pin - .EOS(), // 1-bit output: Active-High output signal indicating the End Of Startup - .PREQ(), // 1-bit output: PROGRAM request to fabric output - .DO({3'b000,spi_mosi}),// 4-bit input: Allows control of the D pin output - .DTS(4'b1110), // 4-bit input: Allows tristate of the D pin - .FCSBO(spi_cs_l), // 1-bit input: Contols the FCS_B pin for flash access - .FCSBTS(1'b0), // 1-bit input: Tristate the FCS_B pin - .GSR(), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port) - .GTS(1'b0), // 1-bit input: Global 3-state input (GTS cannot be used for the port name) - .KEYCLEARB(), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM) - .PACK(), // 1-bit input: PROGRAM acknowledge input - .USRCCLKO(spi_sck_o), // 1-bit input: User CCLK input - .USRCCLKTS(1'b0), // 1-bit input: User CCLK 3-state enable input - .USRDONEO(1'b1), // 1-bit input: User DONE pin output control - .USRDONETS(1'b1) // 1-bit input: User DONE 3-state enable output - ); - - // - // PCIe IPI subsystem instantiation - // - pcie2axilite_sub pcie2axilite_sub_i( - .sys_clk(sys_clk), - .sys_clk_gt(sys_clk_gt), - .clk_100_clk_p(prog_b5_p), - .clk_100_clk_n(prog_b5_n), - .sys_reset_l(sys_reset_l), - .pcie_7x_mgt_rxn(pcie_7x_mgt_rxn), - .pcie_7x_mgt_rxp(pcie_7x_mgt_rxp), - .pcie_7x_mgt_txn(pcie_7x_mgt_txn), - .pcie_7x_mgt_txp(pcie_7x_mgt_txp), - .axi_aclk(axi_clk), - .user_link_up(rst_l), - .m00_axi_0_araddr(CSR_araddr), - .m00_axi_0_arprot(CSR_arprot), - .m00_axi_0_arready(CSR_arready), - .m00_axi_0_arvalid(CSR_arvalid), - .m00_axi_0_awaddr(CSR_awaddr), - .m00_axi_0_awprot(CSR_awprot), - .m00_axi_0_awready(CSR_awready), - .m00_axi_0_awvalid(CSR_awvalid), - .m00_axi_0_bready(CSR_bready), - .m00_axi_0_bresp(1'b0), - .m00_axi_0_bvalid(CSR_bvalid), - .m00_axi_0_rdata(CSR_rdata), - .m00_axi_0_rready(CSR_rready), - .m00_axi_0_rresp(1'b0), - .m00_axi_0_rvalid(CSR_rvalid), - .m00_axi_0_wdata(CSR_wdata), - .m00_axi_0_wready(CSR_wready), - .m00_axi_0_wstrb(CSR_wstrb), - .m00_axi_0_wvalid(CSR_wvalid), - .uart_0_baudoutn(), - .uart_0_ctsn(1'b0), - .uart_0_dcdn(1'b0), - .uart_0_ddis(), - .uart_0_dsrn(1'b0), - .uart_0_dtrn(), - .uart_0_out1n(), - .uart_0_out2n(), - .uart_0_ri(1'b0), - .uart_0_rtsn(), - .uart_0_rxd(avr_txd), - .uart_0_rxrdyn(), - .uart_0_txd(avr_rxd), - .uart_0_txrdyn(), - .iic_0_scl_i(i2c_cin), - .iic_0_scl_o(i2c_cout), - .iic_0_scl_t(i2c_ctri), - .iic_0_sda_i(i2c_din), - .iic_0_sda_o(i2c_dout), - .iic_0_sda_t(i2c_dtri), - .spi_0_io0_o(spi_io0_o), - .spi_0_io1_i(spi_io1_i), - .spi_0_sck_o(spi_sck_o), - .spi_0_ss_o(spi_ss_o_0), - .spi_0_ss_t(spi_ss_t) - ); - - assign spi_mosi = spi_io0_o; - assign spi_io1_i = spi_miso; - - always@(posedge axi_clk) begin - if (spi_ss_t == 0) - spi_cs_l <= spi_ss_o_0; - else - spi_cs_l <= 1'b1; - end - - //*************************************************************************** - // Buffers for I2C Tri-State I/O - //*************************************************************************** - IOBUF IOBUF_i2c_clk_inst ( - .O(i2c_cin), - .I(i2c_cout), - .IO(i2c_scl), - .T(i2c_ctri) - ); - - IOBUF IOBUF_i2c_data_inst ( - .O(i2c_din), - .I(i2c_dout), - .IO(i2c_sda), - .T(i2c_dtri) - ); - - USR_ACCESSE2 USR_ACCESSE2_inst ( - .CFGCLK(), // 1-bit output: Configuration Clock - .DATA(UAR_DATA), // 32-bit output: Configuration Data reflecting the contents of the AXSS register - .DATAVALID() // 1-bit output: Active High Data Valid - ); - - // decode CSR Transaction - assign CSR_wdecode = (CSR_awaddr[`DEV_SEL_HI_BIT:`DEV_SEL_LO_BIT] == 0) | (CSR_awaddr[`DEV_SEL_HI_BIT:`DEV_SEL_LO_BIT] > 3); // Decode 0x0 and out-of-range to CSR - assign CSR_rdecode = (CSR_araddr[`DEV_SEL_HI_BIT:`DEV_SEL_LO_BIT] == 0) | (CSR_araddr[`DEV_SEL_HI_BIT:`DEV_SEL_LO_BIT] > 3); // Decode 0x0 and out-of-range to CSR - assign csr_wen = CSR_awready & CSR_wdecode; - assign csr_ren = CSR_arready & CSR_rdecode; - - always@(posedge axi_clk or negedge(rst_l)) begin - if (rst_l == 1'b0) begin - CSR_awready <= 1'b0; - CSR_arready <= 1'b0; - clk_cnt <= 0; - led_q <= 0; - led_test_reg <= 1'b0; - qsfp_rst_reg <= 'h0; - qsfp_lp_reg <= 'h0; - qsfp_sel_oh <= 4'h0; - end - else begin - clk_cnt <= clk_cnt + 1; - led_q[3] <= clk_cnt[25]; - CSR_awready <= CSR_awvalid; - CSR_arready <= CSR_arvalid; - if (csr_wen & CSR_wvalid) begin - CSR_wready <= CSR_wvalid & ~(CSR_awvalid); - if (CSR_awaddr[`DEV_SEL_LO_BIT-1]) begin - qsfp_rst_reg <= CSR_wdata[19:16]; // AXI Write to addr 0x80 Config Reg, R/W - qsfp_lp_reg <= CSR_wdata[15:12]; - qsfp_sel_oh <= CSR_wdata[11:8]; - led_test_reg <= CSR_wdata[7]; - led_q[2:0] <= CSR_wdata[6:4]; - end - CSR_bvalid <= 1; - end - else if (csr_ren & CSR_rready) begin - CSR_rvalid <= CSR_rready & ~(CSR_arvalid); - // AXI Read: 0x80 reads config reg, 0x0 reads VERSION REG, 0x4 reads UAR. 0x0 and 0x4 are READ ONLY - CSR_rdata <= CSR_araddr[`DEV_SEL_LO_BIT-1] ? {12'h0, - qsfp_rst_reg, - qsfp_lp_reg, - qsfp_sel_oh, - led_test_reg, - led_q[2:0], - 4'b0000} : CSR_araddr[3] ? 32'h0 : (CSR_araddr[2] ? UAR_DATA : `VERSION_REG); - end - else begin - CSR_rvalid <= 0; - CSR_wready <= 0; - end - end - end - - assign spi_miso = spi_in[1]; - - assign led_pins = ~led_q; - assign FPGA_I2C_MASTER_L = 1'b1; // Change to 1'b0 to allow FPGA control of QSFP I2C bus - assign QSFP_CTL_EN = 1'b1; - assign SAS_CTL_EN = 1'b1; - // User logic +module bittware_xupvvh_top ( + output logic [3:0] led_pins, + input user_ref_100_p, // 100MHz referennce clock + input user_ref_100_n, // 100MHz referennce clock + input sys_reset_n, // Global reset + input usb_uart_txd, // USB UART + output logic usb_uart_rxd // USB UART +); + +logic clk_out100, clk_out200, clk_out300; +logic clk_out100_rst, clk_out200_rst, clk_out300_rst; +logic [2:0] clk_out100_rst_r, clk_out200_rst_r, clk_out300_rst_r; + +clk_wiz_0 clk_wiz_mmcm ( + .clk_out100 ( clk_out100 ), + .clk_out200 ( clk_out200 ), + .clk_out300 ( clk_out300 ), + .clk_in1_p ( user_ref_100_p ), + .clk_in1_n ( user_ref_100_n ) +); + +always_comb begin + clk_out100_rst = clk_out100_rst_r[2]; + clk_out200_rst = clk_out200_rst_r[2]; + clk_out300_rst = clk_out300_rst_r[2]; +end + +always @ (posedge clk_out200) clk_out200_rst_r <= {clk_out200_rst_r, ~sys_reset_n}; +always @ (posedge clk_out300) clk_out300_rst_r <= {clk_out300_rst_r, ~sys_reset_n}; +always @ (posedge clk_out100) clk_out100_rst_r <= {clk_out100_rst_r, ~sys_reset_n}; + + +// Logic for programming UART core +(* mark_debug = "true" *) logic interrupt; +enum {UART_STARTUP, UART_LOOPBACK, UART_STREAM} uart_state; +(* mark_debug = "true" *) logic [31:0] uart_axi_wdata, uart_axi_rdata; +(* mark_debug = "true" *) logic [3:0] uart_axi_awaddr, uart_axi_araddr; +(* mark_debug = "true" *) logic [1:0] uart_axi_rresp; +(* mark_debug = "true" *) logic uart_axi_awready, uart_axi_awvalid, uart_axi_arvalid, uart_axi_arready, uart_axi_rvalid, uart_axi_wready; + +logic sop_l; + +always_comb begin + led_pins[3:0] = 0; +end - - +always_ff @ (posedge clk_out300) begin + if (clk_out300_rst) begin + uart_axi_wdata <= 0; + uart_axi_awvalid <= 0; + uart_axi_arvalid <= 0; + uart_axi_araddr <= 0; + uart_state <= UART_STARTUP; + sop_l <= 0; + end else begin + + if (uart_axi_awvalid && uart_axi_awready) uart_axi_awvalid <= 0; + if (uart_axi_arvalid && uart_axi_arready) uart_axi_arvalid <= 0; + + case (uart_state) + UART_STARTUP: begin + uart_axi_wdata[4] <= 1; // Enable interrupt + uart_axi_awvalid <= 1; + uart_axi_awaddr <= 'hc; + if (uart_axi_awvalid && uart_axi_awready) begin + uart_state <= UART_LOOPBACK; + uart_axi_awaddr <= 'h4; + end + end + UART_LOOPBACK: begin + // Just read data and put it back on write interface + uart_axi_araddr <= 0; + if (interrupt) uart_axi_arvalid <= 1; + if (uart_axi_rvalid && uart_axi_rresp == 0) begin + uart_axi_wdata <= uart_axi_rdata; + uart_axi_awvalid <= 1; + uart_axi_awaddr <= 'h4; + end + // If we detect a + end + UART_STREAM: begin + // In this mode we connect to an axi stream, and create the sop/eop signals based on line return - eop is 8'h0a + // Data is decoded as hex + uart_axi_araddr <= 0; + if (interrupt) uart_axi_arvalid <= 1; + // Code for rx + if (uart_axi_rvalid && uart_axi_rresp == 0) begin + if (~sop_l) begin + sop_l <= 1; + end + uart_axi_wdata <= uart_axi_rdata; + uart_axi_awvalid <= 1; + uart_axi_awaddr <= 'h4; + end + + + // Logic for tx + + end + endcase + end +end + +axi_uartlite_0 uart ( + .s_axi_aclk(clk_out300), // input wire s_axi_aclk + .s_axi_aresetn(~clk_out300_rst), // input wire s_axi_aresetn + .interrupt(interrupt), // output wire interrupt + .s_axi_awaddr(uart_axi_awaddr), // input wire [3 : 0] s_axi_awaddr + .s_axi_awvalid(uart_axi_awvalid), // input wire s_axi_awvalid + .s_axi_awready(uart_axi_awready), // output wire s_axi_awready + .s_axi_wdata(uart_axi_wdata), // input wire [31 : 0] s_axi_wdata + .s_axi_wstrb('d0), // input wire [3 : 0] s_axi_wstrb + .s_axi_wvalid(uart_axi_awvalid), // input wire s_axi_wvalid + .s_axi_wready(uart_axi_wready), // output wire s_axi_wready + .s_axi_bresp(), // output wire [1 : 0] s_axi_bresp + .s_axi_bvalid(), // output wire s_axi_bvalid + .s_axi_bready(1'b1), // input wire s_axi_bready + .s_axi_araddr(uart_axi_araddr), // input wire [3 : 0] s_axi_araddr + .s_axi_arvalid(uart_axi_arvalid), // input wire s_axi_arvalid + .s_axi_arready(uart_axi_arready), // output wire s_axi_arready + .s_axi_rdata(uart_axi_rdata), // output wire [31 : 0] s_axi_rdata + .s_axi_rresp(uart_axi_rresp), // output wire [1 : 0] s_axi_rresp + .s_axi_rvalid(uart_axi_rvalid), // output wire s_axi_rvalid + .s_axi_rready(1'd1), // input wire s_axi_rready + .rx(usb_uart_txd), // input wire rx + .tx(usb_uart_rxd) // output wire tx +); + endmodule diff --git a/bittware_xupvvh/synth/bittware_xupvvh_top.xdc b/bittware_xupvvh/synth/bittware_xupvvh_top.xdc index 460b1db..f11a918 100644 --- a/bittware_xupvvh/synth/bittware_xupvvh_top.xdc +++ b/bittware_xupvvh/synth/bittware_xupvvh_top.xdc @@ -1,15 +1,17 @@ set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design] +# Global reset set_property IOSTANDARD LVCMOS18 [get_ports sys_reset_n] set_property PACKAGE_PIN F18 [get_ports sys_reset_n] +# 100MHz reference clock set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports user_ref_100_p] set_property ODT RTT_48 [get_ports user_ref_100_p] set_property PACKAGE_PIN BH27 [get_ports user_ref_100_p] create_clock -period 10.000 -name user_ref_100_p [get_ports user_ref_100_p] - +# LED pins for debug set_property IOSTANDARD LVCMOS18 [get_ports {led_pins[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {led_pins[1]}] set_property IOSTANDARD LVCMOS18 [get_ports {led_pins[2]}] @@ -19,7 +21,7 @@ set_property PACKAGE_PIN L18 [get_ports {led_pins[1]}] set_property PACKAGE_PIN L21 [get_ports {led_pins[2]}] set_property PACKAGE_PIN L20 [get_ports {led_pins[3]}] - +# USB-UART connections set_property IOSTANDARD LVCMOS18 [get_ports usb_uart_txd] set_property IOSTANDARD LVCMOS18 [get_ports usb_uart_rxd] set_property PACKAGE_PIN G21 [get_ports usb_uart_txd] @@ -32,77 +34,91 @@ connect_debug_port u_ila_0/probe7 [get_nets [list tx]] connect_debug_port u_ila_0/probe8 [get_nets [list tx2]] connect_debug_port u_ila_0/probe15 [get_nets [list usb_uart_txd_IBUF]] - -connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_pll/inst/clk_out300]] -connect_debug_port u_ila_0/probe0 [get_nets [list {check_rst[0]} {check_rst[1]} {check_rst[2]} {check_rst[3]} {check_rst[4]} {check_rst[5]} {check_rst[6]} {check_rst[7]}]] -connect_debug_port u_ila_0/probe7 [get_nets [list {clk_out300_rst_r[0]} {clk_out300_rst_r[1]} {clk_out300_rst_r[2]}]] -connect_debug_port u_ila_1/clk [get_nets [list clk_wiz_pll/inst/clk_out100]] -connect_debug_port u_ila_1/probe0 [get_nets [list {clk_out100_rst_r[0]} {clk_out100_rst_r[1]} {clk_out100_rst_r[2]}]] -connect_debug_port dbg_hub/clk [get_nets clk_out100] - create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] -set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0] set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property port_width 1 [get_debug_ports u_ila_0/clk] -connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_mmcm/inst/clk_out300]] +connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_pll/inst/clk_out300]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] set_property port_width 32 [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {uart_axi_rdata[0]} {uart_axi_rdata[1]} {uart_axi_rdata[2]} {uart_axi_rdata[3]} {uart_axi_rdata[4]} {uart_axi_rdata[5]} {uart_axi_rdata[6]} {uart_axi_rdata[7]} {uart_axi_rdata[8]} {uart_axi_rdata[9]} {uart_axi_rdata[10]} {uart_axi_rdata[11]} {uart_axi_rdata[12]} {uart_axi_rdata[13]} {uart_axi_rdata[14]} {uart_axi_rdata[15]} {uart_axi_rdata[16]} {uart_axi_rdata[17]} {uart_axi_rdata[18]} {uart_axi_rdata[19]} {uart_axi_rdata[20]} {uart_axi_rdata[21]} {uart_axi_rdata[22]} {uart_axi_rdata[23]} {uart_axi_rdata[24]} {uart_axi_rdata[25]} {uart_axi_rdata[26]} {uart_axi_rdata[27]} {uart_axi_rdata[28]} {uart_axi_rdata[29]} {uart_axi_rdata[30]} {uart_axi_rdata[31]}]] +connect_debug_port u_ila_0/probe0 [get_nets [list {uart_axi_wdata[0]} {uart_axi_wdata[1]} {uart_axi_wdata[2]} {uart_axi_wdata[3]} {uart_axi_wdata[4]} {uart_axi_wdata[5]} {uart_axi_wdata[6]} {uart_axi_wdata[7]} {uart_axi_wdata[8]} {uart_axi_wdata[9]} {uart_axi_wdata[10]} {uart_axi_wdata[11]} {uart_axi_wdata[12]} {uart_axi_wdata[13]} {uart_axi_wdata[14]} {uart_axi_wdata[15]} {uart_axi_wdata[16]} {uart_axi_wdata[17]} {uart_axi_wdata[18]} {uart_axi_wdata[19]} {uart_axi_wdata[20]} {uart_axi_wdata[21]} {uart_axi_wdata[22]} {uart_axi_wdata[23]} {uart_axi_wdata[24]} {uart_axi_wdata[25]} {uart_axi_wdata[26]} {uart_axi_wdata[27]} {uart_axi_wdata[28]} {uart_axi_wdata[29]} {uart_axi_wdata[30]} {uart_axi_wdata[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] -set_property port_width 2 [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {uart_axi_rresp[0]} {uart_axi_rresp[1]}]] +set_property port_width 4 [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list {uart_axi_awaddr[0]} {uart_axi_awaddr[1]} {uart_axi_awaddr[2]} {uart_axi_awaddr[3]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] -set_property port_width 32 [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list {uart_axi_wdata[0]} {uart_axi_wdata[1]} {uart_axi_wdata[2]} {uart_axi_wdata[3]} {uart_axi_wdata[4]} {uart_axi_wdata[5]} {uart_axi_wdata[6]} {uart_axi_wdata[7]} {uart_axi_wdata[8]} {uart_axi_wdata[9]} {uart_axi_wdata[10]} {uart_axi_wdata[11]} {uart_axi_wdata[12]} {uart_axi_wdata[13]} {uart_axi_wdata[14]} {uart_axi_wdata[15]} {uart_axi_wdata[16]} {uart_axi_wdata[17]} {uart_axi_wdata[18]} {uart_axi_wdata[19]} {uart_axi_wdata[20]} {uart_axi_wdata[21]} {uart_axi_wdata[22]} {uart_axi_wdata[23]} {uart_axi_wdata[24]} {uart_axi_wdata[25]} {uart_axi_wdata[26]} {uart_axi_wdata[27]} {uart_axi_wdata[28]} {uart_axi_wdata[29]} {uart_axi_wdata[30]} {uart_axi_wdata[31]}]] +set_property port_width 8 [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list {check_rst[0]} {check_rst[1]} {check_rst[2]} {check_rst[3]} {check_rst[4]} {check_rst[5]} {check_rst[6]} {check_rst[7]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] -set_property port_width 4 [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {uart_axi_araddr[0]} {uart_axi_araddr[1]} {uart_axi_araddr[2]} {uart_axi_araddr[3]}]] +set_property port_width 32 [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {uart_state[0]} {uart_state[1]} {uart_state[2]} {uart_state[3]} {uart_state[4]} {uart_state[5]} {uart_state[6]} {uart_state[7]} {uart_state[8]} {uart_state[9]} {uart_state[10]} {uart_state[11]} {uart_state[12]} {uart_state[13]} {uart_state[14]} {uart_state[15]} {uart_state[16]} {uart_state[17]} {uart_state[18]} {uart_state[19]} {uart_state[20]} {uart_state[21]} {uart_state[22]} {uart_state[23]} {uart_state[24]} {uart_state[25]} {uart_state[26]} {uart_state[27]} {uart_state[28]} {uart_state[29]} {uart_state[30]} {uart_state[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] -set_property port_width 4 [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {uart_axi_awaddr[0]} {uart_axi_awaddr[1]} {uart_axi_awaddr[2]} {uart_axi_awaddr[3]}]] +set_property port_width 2 [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {uart_axi_rresp[0]} {uart_axi_rresp[1]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] -set_property port_width 1 [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {uart_state[0]}]] +set_property port_width 3 [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {clk_out300_rst_r[0]} {clk_out300_rst_r[1]} {clk_out300_rst_r[2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] -set_property port_width 1 [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list interrupt]] +set_property port_width 4 [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {uart_axi_araddr[0]} {uart_axi_araddr[1]} {uart_axi_araddr[2]} {uart_axi_araddr[3]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] -set_property port_width 1 [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list uart_axi_arready]] +set_property port_width 32 [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list {uart_axi_rdata[0]} {uart_axi_rdata[1]} {uart_axi_rdata[2]} {uart_axi_rdata[3]} {uart_axi_rdata[4]} {uart_axi_rdata[5]} {uart_axi_rdata[6]} {uart_axi_rdata[7]} {uart_axi_rdata[8]} {uart_axi_rdata[9]} {uart_axi_rdata[10]} {uart_axi_rdata[11]} {uart_axi_rdata[12]} {uart_axi_rdata[13]} {uart_axi_rdata[14]} {uart_axi_rdata[15]} {uart_axi_rdata[16]} {uart_axi_rdata[17]} {uart_axi_rdata[18]} {uart_axi_rdata[19]} {uart_axi_rdata[20]} {uart_axi_rdata[21]} {uart_axi_rdata[22]} {uart_axi_rdata[23]} {uart_axi_rdata[24]} {uart_axi_rdata[25]} {uart_axi_rdata[26]} {uart_axi_rdata[27]} {uart_axi_rdata[28]} {uart_axi_rdata[29]} {uart_axi_rdata[30]} {uart_axi_rdata[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] set_property port_width 1 [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list uart_axi_arvalid]] +connect_debug_port u_ila_0/probe8 [get_nets [list interrupt]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] set_property port_width 1 [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list uart_axi_awready]] +connect_debug_port u_ila_0/probe9 [get_nets [list uart_axi_arready]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] set_property port_width 1 [get_debug_ports u_ila_0/probe10] -connect_debug_port u_ila_0/probe10 [get_nets [list uart_axi_awvalid]] +connect_debug_port u_ila_0/probe10 [get_nets [list uart_axi_arvalid]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] set_property port_width 1 [get_debug_ports u_ila_0/probe11] -connect_debug_port u_ila_0/probe11 [get_nets [list uart_axi_rvalid]] +connect_debug_port u_ila_0/probe11 [get_nets [list uart_axi_awready]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] set_property port_width 1 [get_debug_ports u_ila_0/probe12] -connect_debug_port u_ila_0/probe12 [get_nets [list usb_uart_rxd_OBUF]] +connect_debug_port u_ila_0/probe12 [get_nets [list uart_axi_awvalid]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] +set_property port_width 1 [get_debug_ports u_ila_0/probe13] +connect_debug_port u_ila_0/probe13 [get_nets [list uart_axi_rvalid]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] +set_property port_width 1 [get_debug_ports u_ila_0/probe14] +connect_debug_port u_ila_0/probe14 [get_nets [list usb_uart_rxd_OBUF]] +create_debug_core u_ila_1 ila +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1] +set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_1] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_1] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1] +set_property port_width 1 [get_debug_ports u_ila_1/clk] +connect_debug_port u_ila_1/clk [get_nets [list clk_wiz_pll/inst/clk_out100]] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0] +set_property port_width 3 [get_debug_ports u_ila_1/probe0] +connect_debug_port u_ila_1/probe0 [get_nets [list {clk_out100_rst_r[0]} {clk_out100_rst_r[1]} {clk_out100_rst_r[2]}]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] -connect_debug_port dbg_hub/clk [get_nets clk_out300] +connect_debug_port dbg_hub/clk [get_nets clk_out100]