zecfoundation
/
zcash-fpga
mirror of https://github.com/ZcashFoundation/zcash-fpga.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

update to control and uart block

This commit is contained in:
bsdevlin 2019-04-07 14:19:06 -04:00
parent d35d61f89b
commit 8d53314851
6 changed files with 543 additions and 201 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

139
bittware_xupvvh/src/rtl/bittware_xupvvh_top.sv
View File

@ -9,123 +9,58 @@ module bittware_xupvvh_top (
output logic usb_uart_rxd // USB UART
);
logic clk_out100, clk_out200, clk_out300;
logic clk_out100_rst, clk_out200_rst, clk_out300_rst;
logic [2:0] clk_out100_rst_r, clk_out200_rst_r, clk_out300_rst_r;
logic clk_100, clk_200, clk_300;
logic rst_100, rst_200, rst_300;
logic [2:0] rst_100_r, rst_200_r, rst_300_r;
clk_wiz_0 clk_wiz_mmcm (
.clk_out100 ( clk_out100 ),
.clk_out200 ( clk_out200 ),
.clk_out300 ( clk_out300 ),
.clk_100 ( clk_100 ),
.clk_200 ( clk_200 ),
.clk_300 ( clk_300 ),
.clk_in1_p ( user_ref_100_p ),
.clk_in1_n ( user_ref_100_n )
);
always_comb begin
clk_out100_rst = clk_out100_rst_r[2];
clk_out200_rst = clk_out200_rst_r[2];
clk_out300_rst = clk_out300_rst_r[2];
rst_100 = rst_100_r[2];
rst_200 = rst_200_r[2];
rst_300 = rst_300_r[2];
end
always @ (posedge clk_out200) clk_out200_rst_r <= {clk_out200_rst_r, ~sys_reset_n};
always @ (posedge clk_out300) clk_out300_rst_r <= {clk_out300_rst_r, ~sys_reset_n};
always @ (posedge clk_out100) clk_out100_rst_r <= {clk_out100_rst_r, ~sys_reset_n};
always_ff @ (posedge clk_200) rst_200_r <= {rst_200_r, ~sys_reset_n};
always_ff @ (posedge clk_300) rst_300_r <= {rst_300_r, ~sys_reset_n};
always_ff @ (posedge clk_100) rst_100_r <= {rst_100_r, ~sys_reset_n};
// Logic for programming UART core
(* mark_debug = "true" *) logic interrupt;
enum {UART_STARTUP, UART_LOOPBACK, UART_STREAM} uart_state;
(* mark_debug = "true" *) logic [31:0] uart_axi_wdata, uart_axi_rdata;
(* mark_debug = "true" *) logic [3:0] uart_axi_awaddr, uart_axi_araddr;
(* mark_debug = "true" *) logic [1:0] uart_axi_rresp;
(* mark_debug = "true" *) logic uart_axi_awready, uart_axi_awvalid, uart_axi_arvalid, uart_axi_arready, uart_axi_rvalid, uart_axi_wready;
logic sop_l;
if_axi_stream #(.DAT_BYTS(1)) uart_axi_rx(clk_300);
if_axi_stream #(.DAT_BYTS(1)) uart_axi_tx(clk_300);
always_comb begin
led_pins[3:0] = 0;
end
always_ff @ (posedge clk_out300) begin
if (clk_out300_rst) begin
uart_axi_wdata <= 0;
uart_axi_awvalid <= 0;
uart_axi_arvalid <= 0;
uart_axi_araddr <= 0;
uart_state <= UART_STARTUP;
sop_l <= 0;
end else begin
if (uart_axi_awvalid && uart_axi_awready) uart_axi_awvalid <= 0;
if (uart_axi_arvalid && uart_axi_arready) uart_axi_arvalid <= 0;
case (uart_state)
UART_STARTUP: begin
uart_axi_wdata[4] <= 1; // Enable interrupt
uart_axi_awvalid <= 1;
uart_axi_awaddr <= 'hc;
if (uart_axi_awvalid && uart_axi_awready) begin
uart_state <= UART_LOOPBACK;
uart_axi_awaddr <= 'h4;
end
end
UART_LOOPBACK: begin
// Just read data and put it back on write interface
uart_axi_araddr <= 0;
if (interrupt) uart_axi_arvalid <= 1;
if (uart_axi_rvalid && uart_axi_rresp == 0) begin
uart_axi_wdata <= uart_axi_rdata;
uart_axi_awvalid <= 1;
uart_axi_awaddr <= 'h4;
end
// If we detect a
end
UART_STREAM: begin
// In this mode we connect to an axi stream, and create the sop/eop signals based on line return - eop is 8'h0a
// Data is decoded as hex
uart_axi_araddr <= 0;
if (interrupt) uart_axi_arvalid <= 1;
// Code for rx
if (uart_axi_rvalid && uart_axi_rresp == 0) begin
if (~sop_l) begin
sop_l <= 1;
end
uart_axi_wdata <= uart_axi_rdata;
uart_axi_awvalid <= 1;
uart_axi_awaddr <= 'h4;
end
// Logic for tx
end
endcase
end
end
axi_uartlite_0 uart (
.s_axi_aclk(clk_out300), // input wire s_axi_aclk
.s_axi_aresetn(~clk_out300_rst), // input wire s_axi_aresetn
.interrupt(interrupt), // output wire interrupt
.s_axi_awaddr(uart_axi_awaddr), // input wire [3 : 0] s_axi_awaddr
.s_axi_awvalid(uart_axi_awvalid), // input wire s_axi_awvalid
.s_axi_awready(uart_axi_awready), // output wire s_axi_awready
.s_axi_wdata(uart_axi_wdata), // input wire [31 : 0] s_axi_wdata
.s_axi_wstrb('d0), // input wire [3 : 0] s_axi_wstrb
.s_axi_wvalid(uart_axi_awvalid), // input wire s_axi_wvalid
.s_axi_wready(uart_axi_wready), // output wire s_axi_wready
.s_axi_bresp(), // output wire [1 : 0] s_axi_bresp
.s_axi_bvalid(), // output wire s_axi_bvalid
.s_axi_bready(1'b1), // input wire s_axi_bready
.s_axi_araddr(uart_axi_araddr), // input wire [3 : 0] s_axi_araddr
.s_axi_arvalid(uart_axi_arvalid), // input wire s_axi_arvalid
.s_axi_arready(uart_axi_arready), // output wire s_axi_arready
.s_axi_rdata(uart_axi_rdata), // output wire [31 : 0] s_axi_rdata
.s_axi_rresp(uart_axi_rresp), // output wire [1 : 0] s_axi_rresp
.s_axi_rvalid(uart_axi_rvalid), // output wire s_axi_rvalid
.s_axi_rready(1'd1), // input wire s_axi_rready
.rx(usb_uart_txd), // input wire rx
.tx(usb_uart_rxd) // output wire tx
uart_wrapper uart_wrapper (
.i_clk ( clk_300 ),
.i_rst ( rst_300 ),
.i_rx_uart ( usb_uart_txd ),
.o_tx_uart ( usb_uart_rxd ),
.tx_if ( uart_axi_tx ),
.rx_if ( uart_axi_rx )
);
zcash_fpga_top #(
.IF_DAT_BYTS ( 1 ),
.CORE_DAT_BYTS ( 8 )
)
zcash_fpga_top (
// Clocks and resets
.i_clk_core0 ( clk_200 ),
.i_rst_core0 ( rst_200 ),
.i_clk_core1 ( clk_300 ),
.i_rst_core1 ( rst_300 ),
.i_clk_if ( clk_300 ),
.i_rst_if ( rst_300 ),
.rx_if ( uart_axi_tx ),
.tx_if ( uart_axi_rx )
);
endmodule

164
bittware_xupvvh/src/rtl/uart_wrapper.sv
View File

@ -17,7 +17,9 @@
along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
module uart_wrapper (
module uart_wrapper #(
parameter MODE = "STREAM" // [STREAM, LOOPBACK]
)(
input i_clk,
input i_rst,
// Interfaces to UART
@ -28,15 +30,18 @@ module uart_wrapper (
if_axi_stream.sink rx_if
);
(* mark_debug = "true" *) enum {UART_STARTUP, UART_LOOPBACK, UART_STREAM} uart_state;
enum {UART_STARTUP, UART_LOOPBACK, UART_TX_STREAM, UART_RX_STREAM, UART_WAIT_STREAM} uart_state;
(* mark_debug = "true" *) logic interrupt;
(* mark_debug = "true" *) logic [31:0] uart_axi_wdata, uart_axi_rdata;
(* mark_debug = "true" *) logic [3:0] uart_axi_awaddr, uart_axi_araddr;
(* mark_debug = "true" *) logic [1:0] uart_axi_rresp;
(* mark_debug = "true" *) logic uart_axi_awready, uart_axi_awvalid, uart_axi_arvalid, uart_axi_arready, uart_axi_rvalid, uart_axi_wready;
(* mark_debug = "true" *) logic sop_l, eop_l;
logic interrupt;
logic [31:0] uart_axi_wdata, uart_axi_rdata;
logic [3:0] uart_axi_awaddr, uart_axi_araddr;
logic [1:0] uart_axi_rresp, uart_axi_bresp;
logic uart_axi_awready, uart_axi_awvalid, uart_axi_arvalid, uart_axi_arready, uart_axi_rvalid, uart_axi_wready;
logic [15:0] tx_byt_cnt, tx_byt_len, rx_byt_cnt, rx_byt_len;
debug_if #(.DAT_BYTS (1), .CTL_BITS (1)) txuart_debug_if (.i_if(tx_if));
debug_if #(.DAT_BYTS (1), .CTL_BITS (1)) rxuart_debug_if (.i_if(rx_if));
always_ff @ (posedge i_clk) begin
if (i_rst) begin
@ -45,10 +50,12 @@ always_ff @ (posedge i_clk) begin
uart_axi_arvalid <= 0;
uart_axi_araddr <= 0;
uart_state <= UART_STARTUP;
sop_l <= 0;
eop_l <= 0;
tx_if.reset_source();
rx_if.rdy <= 0;
tx_byt_cnt <= 0;
tx_byt_len <= 0;
rx_byt_cnt <= 0;
rx_byt_len <= 0;
end else begin
if (uart_axi_awvalid && uart_axi_awready) uart_axi_awvalid <= 0;
@ -61,11 +68,16 @@ always_ff @ (posedge i_clk) begin
uart_axi_awvalid <= 1;
uart_axi_awaddr <= 'hc;
if (uart_axi_awvalid && uart_axi_awready) begin
uart_state <= UART_LOOPBACK;
uart_state <= (MODE == "STREAM" ? UART_WAIT_STREAM : UART_LOOPBACK);
uart_axi_awaddr <= 'h4;
uart_axi_awvalid <= 0;
end
end
UART_LOOPBACK: begin
tx_byt_cnt <= 0;
tx_byt_len <= 0;
rx_byt_cnt <= 0;
rx_byt_len <= 0;
// Just read data and put it back on write interface
uart_axi_araddr <= 0;
if (interrupt) uart_axi_arvalid <= 1;
@ -75,61 +87,97 @@ always_ff @ (posedge i_clk) begin
uart_axi_awaddr <= 'h4;
// Switch modes if we detect a null character
// We can't exit STREAM mode without FPGA reset
if (uart_axi_rdata == 0) begin
uart_state <= UART_STREAM;
uart_state <= UART_WAIT_STREAM;
end
end
end
UART_STREAM: begin
// In this mode we connect to an axi stream, and create the sop/eop signals based on line return - eop is 8'h0a
// Data is decoded as hex
// TODO we should really read fifo status and not interrupt
if(~sop_l)
rx_if.rdy <= 1;
uart_axi_araddr <= 0;
if (interrupt) uart_axi_arvalid <= 1;
// Code for rx
if (uart_axi_rvalid && uart_axi_rresp == 0) begin
UART_WAIT_STREAM: begin
uart_axi_arvalid <= 1;
uart_axi_araddr <= 'h8;
if (tx_if.val || uart_axi_awvalid) begin
// Wait
end else
if (uart_axi_rvalid && uart_axi_rdata[0]) begin
uart_state <= UART_RX_STREAM;
end else
if (rx_if.val) begin
uart_state <= UART_TX_STREAM;
end
end
// Receiving data from host
UART_RX_STREAM: begin
// In this mode we connect to an axi stream, and create the sop/eop signals based on line return - the first 2 bytes
// are taken to be the stream length (so smallest stream is 2 bytes)
// Swap between checking data and status register
// Check status
uart_axi_arvalid <= 1;
if (uart_axi_araddr == 'h8) begin
if (uart_axi_rvalid && uart_axi_rdata[0]) begin
uart_axi_araddr <= 0;
end
// Then check data
end else
// Check for valid data byte
if (uart_axi_rvalid) begin
uart_axi_araddr <= 'h8;
tx_if.dat <= uart_axi_rdata;
tx_if.val <= 1;
tx_if.sop <= ~sop_l;
if (~sop_l) begin
sop_l <= 1;
end
if (uart_axi_rdata == 8'h0a) begin
tx_if.eop <= 1;
sop_l <= 0;
end
// Switch modes if null character
if (uart_axi_rdata == 0) begin
tx_if.val <= 0;
sop_l <= 0;
eop_l <= 0;
uart_state <= UART_LOOPBACK;
tx_if.sop <= 0;
tx_if.eop <= 0;
tx_byt_cnt <= tx_byt_cnt + 1;
if (tx_byt_cnt == 0) begin
tx_byt_len[0 +: 8] <= uart_axi_rdata;
tx_if.sop <= 1;
end else
if (tx_byt_cnt == 1) begin
tx_byt_len[8 +: 8] <= uart_axi_rdata;
if (tx_byt_len[0 +: 8] <= 2 && uart_axi_rdata == 0) begin
tx_if.eop <= 1;
tx_byt_cnt <= 0;
tx_byt_len <= 0;
uart_state <= UART_WAIT_STREAM;
end
end else begin
// If we hit our length
if (tx_byt_cnt + 1 >= tx_byt_len) begin
tx_if.eop <= 1;
tx_byt_cnt <= 0;
tx_byt_len <= 0;
uart_state <= UART_WAIT_STREAM;
end
end
end
end
// Sending data to host
UART_TX_STREAM: begin
uart_axi_araddr <= 'h8;
// Swap between sending data and status register (checking for full)
// Check status
if (~rx_if.rdy && ~uart_axi_awvalid) begin
uart_axi_arvalid <= 1;
if (uart_axi_rvalid && ~uart_axi_rdata[3]) begin
rx_if.rdy <= 1;
uart_axi_arvalid <= 0;
end
end
// Logic for tx
if (rx_if.val && rx_if.rdy) begin
uart_axi_wdata <= rx_if.dat;
uart_axi_awvalid <= 1;
uart_axi_awaddr <= 'h4;
if (rx_if.eop) begin
eop_l <= 1;
rx_if.rdy <= 0;
end else begin
if (~uart_axi_awvalid) begin
// Then check data
if (rx_if.val && rx_if.rdy) begin
rx_if.rdy <= 0;
uart_axi_wdata <= rx_if.dat;
uart_axi_awvalid <= 1;
uart_axi_awaddr <= 'h4;
if (rx_if.eop) begin
uart_state <= UART_WAIT_STREAM;
end
end
end
end
if (eop_l && ~uart_axi_awvalid) begin
uart_axi_wdata <= 8'h0a;
uart_axi_awvalid <= 1;
uart_axi_awaddr <= 'h4;
eop_l <= 0;
sop_l <= 0;
end
end
endcase
end
@ -146,7 +194,7 @@ axi_uartlite_0 uart (
.s_axi_wstrb('d0), // input wire [3 : 0] s_axi_wstrb
.s_axi_wvalid(uart_axi_awvalid), // input wire s_axi_wvalid
.s_axi_wready(uart_axi_wready), // output wire s_axi_wready
.s_axi_bresp(), // output wire [1 : 0] s_axi_bresp
.s_axi_bresp(uart_axi_bresp), // output wire [1 : 0] s_axi_bresp
.s_axi_bvalid(), // output wire s_axi_bvalid
.s_axi_bready(1'b1), // input wire s_axi_bready
.s_axi_araddr(uart_axi_araddr), // input wire [3 : 0] s_axi_araddr

333
bittware_xupvvh/synth/bittware_xupvvh_top.xdc
View File

@ -34,91 +34,354 @@ connect_debug_port u_ila_0/probe7 [get_nets [list tx]]
connect_debug_port u_ila_0/probe8 [get_nets [list tx2]]
connect_debug_port u_ila_0/probe15 [get_nets [list usb_uart_txd_IBUF]]
connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_pll/inst/clk_out300]]
connect_debug_port u_ila_0/probe2 [get_nets [list {check_rst[0]} {check_rst[1]} {check_rst[2]} {check_rst[3]} {check_rst[4]} {check_rst[5]} {check_rst[6]} {check_rst[7]}]]
connect_debug_port u_ila_0/probe5 [get_nets [list {clk_out300_rst_r[0]} {clk_out300_rst_r[1]} {clk_out300_rst_r[2]}]]
connect_debug_port u_ila_1/clk [get_nets [list clk_wiz_pll/inst/clk_out100]]
connect_debug_port u_ila_1/probe0 [get_nets [list {clk_out100_rst_r[0]} {clk_out100_rst_r[1]} {clk_out100_rst_r[2]}]]
connect_debug_port dbg_hub/clk [get_nets clk_out100]
connect_debug_port u_ila_0/probe1 [get_nets [list {uart_state[0]} {uart_state[1]} {uart_state[2]} {uart_state[3]} {uart_state[4]} {uart_state[5]} {uart_state[6]} {uart_state[7]} {uart_state[8]} {uart_state[9]} {uart_state[10]} {uart_state[11]} {uart_state[12]} {uart_state[13]} {uart_state[14]} {uart_state[15]} {uart_state[16]} {uart_state[17]} {uart_state[18]} {uart_state[19]} {uart_state[20]} {uart_state[21]} {uart_state[22]} {uart_state[23]} {uart_state[24]} {uart_state[25]} {uart_state[26]} {uart_state[27]} {uart_state[28]} {uart_state[29]} {uart_state[30]} {uart_state[31]}]]
connect_debug_port u_ila_0/probe2 [get_nets [list {uart_axi_awaddr[0]} {uart_axi_awaddr[1]} {uart_axi_awaddr[2]} {uart_axi_awaddr[3]}]]
connect_debug_port u_ila_0/probe3 [get_nets [list {uart_axi_rdata[0]} {uart_axi_rdata[1]} {uart_axi_rdata[2]} {uart_axi_rdata[3]} {uart_axi_rdata[4]} {uart_axi_rdata[5]} {uart_axi_rdata[6]} {uart_axi_rdata[7]} {uart_axi_rdata[8]} {uart_axi_rdata[9]} {uart_axi_rdata[10]} {uart_axi_rdata[11]} {uart_axi_rdata[12]} {uart_axi_rdata[13]} {uart_axi_rdata[14]} {uart_axi_rdata[15]} {uart_axi_rdata[16]} {uart_axi_rdata[17]} {uart_axi_rdata[18]} {uart_axi_rdata[19]} {uart_axi_rdata[20]} {uart_axi_rdata[21]} {uart_axi_rdata[22]} {uart_axi_rdata[23]} {uart_axi_rdata[24]} {uart_axi_rdata[25]} {uart_axi_rdata[26]} {uart_axi_rdata[27]} {uart_axi_rdata[28]} {uart_axi_rdata[29]} {uart_axi_rdata[30]} {uart_axi_rdata[31]}]]
connect_debug_port u_ila_0/probe4 [get_nets [list {uart_axi_rresp[0]} {uart_axi_rresp[1]}]]
connect_debug_port u_ila_0/probe5 [get_nets [list {uart_axi_araddr[0]} {uart_axi_araddr[1]} {uart_axi_araddr[2]} {uart_axi_araddr[3]}]]
connect_debug_port u_ila_0/probe6 [get_nets [list {uart_axi_wdata[0]} {uart_axi_wdata[1]} {uart_axi_wdata[2]} {uart_axi_wdata[3]} {uart_axi_wdata[4]} {uart_axi_wdata[5]} {uart_axi_wdata[6]} {uart_axi_wdata[7]} {uart_axi_wdata[8]} {uart_axi_wdata[9]} {uart_axi_wdata[10]} {uart_axi_wdata[11]} {uart_axi_wdata[12]} {uart_axi_wdata[13]} {uart_axi_wdata[14]} {uart_axi_wdata[15]} {uart_axi_wdata[16]} {uart_axi_wdata[17]} {uart_axi_wdata[18]} {uart_axi_wdata[19]} {uart_axi_wdata[20]} {uart_axi_wdata[21]} {uart_axi_wdata[22]} {uart_axi_wdata[23]} {uart_axi_wdata[24]} {uart_axi_wdata[25]} {uart_axi_wdata[26]} {uart_axi_wdata[27]} {uart_axi_wdata[28]} {uart_axi_wdata[29]} {uart_axi_wdata[30]} {uart_axi_wdata[31]}]]
connect_debug_port u_ila_0/probe7 [get_nets [list eop_l]]
connect_debug_port u_ila_0/probe9 [get_nets [list interrupt]]
connect_debug_port u_ila_0/probe10 [get_nets [list sop_l]]
connect_debug_port u_ila_0/probe11 [get_nets [list uart_axi_arready]]
connect_debug_port u_ila_0/probe12 [get_nets [list uart_axi_arvalid]]
connect_debug_port u_ila_0/probe13 [get_nets [list uart_axi_awready]]
connect_debug_port u_ila_0/probe14 [get_nets [list uart_axi_awvalid]]
connect_debug_port u_ila_0/probe15 [get_nets [list uart_axi_rvalid]]
connect_debug_port u_ila_0/probe16 [get_nets [list uart_axi_wready]]
connect_debug_port u_ila_1/probe5 [get_nets [list {uart_wrapper/uart_axi_wdata_0[0]} {uart_wrapper/uart_axi_wdata_0[1]} {uart_wrapper/uart_axi_wdata_0[2]} {uart_wrapper/uart_axi_wdata_0[3]} {uart_wrapper/uart_axi_wdata_0[4]} {uart_wrapper/uart_axi_wdata_0[5]} {uart_wrapper/uart_axi_wdata_0[6]} {uart_wrapper/uart_axi_wdata_0[7]} {uart_wrapper/uart_axi_wdata_0[8]} {uart_wrapper/uart_axi_wdata_0[9]} {uart_wrapper/uart_axi_wdata_0[10]} {uart_wrapper/uart_axi_wdata_0[11]} {uart_wrapper/uart_axi_wdata_0[12]} {uart_wrapper/uart_axi_wdata_0[13]} {uart_wrapper/uart_axi_wdata_0[14]} {uart_wrapper/uart_axi_wdata_0[15]} {uart_wrapper/uart_axi_wdata_0[16]} {uart_wrapper/uart_axi_wdata_0[17]} {uart_wrapper/uart_axi_wdata_0[18]} {uart_wrapper/uart_axi_wdata_0[19]} {uart_wrapper/uart_axi_wdata_0[20]} {uart_wrapper/uart_axi_wdata_0[21]} {uart_wrapper/uart_axi_wdata_0[22]} {uart_wrapper/uart_axi_wdata_0[23]} {uart_wrapper/uart_axi_wdata_0[24]} {uart_wrapper/uart_axi_wdata_0[25]} {uart_wrapper/uart_axi_wdata_0[26]} {uart_wrapper/uart_axi_wdata_0[27]} {uart_wrapper/uart_axi_wdata_0[28]} {uart_wrapper/uart_axi_wdata_0[29]} {uart_wrapper/uart_axi_wdata_0[30]} {uart_wrapper/uart_axi_wdata_0[31]}]]
connect_debug_port u_ila_0/probe0 [get_nets [list {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[0]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[1]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[2]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[3]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[4]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[5]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[6]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[7]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[8]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[9]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[10]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[11]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[12]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[13]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[14]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[15]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[16]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[17]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[18]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[19]}]]
connect_debug_port u_ila_0/probe9 [get_nets [list zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_val_a]]
connect_debug_port u_ila_0/probe11 [get_nets [list zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/o_rdy_a]]
connect_debug_port u_ila_0/probe12 [get_nets [list zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/o_val_b]]
connect_debug_port u_ila_1/probe1 [get_nets [list {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[0]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[1]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[2]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[3]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[4]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[5]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[6]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[7]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[8]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[9]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[10]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[11]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[12]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[13]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[14]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[15]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[16]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[17]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[18]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[19]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[20]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[21]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[22]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[23]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[24]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[25]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[26]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[27]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[28]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[29]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[30]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[31]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[32]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[33]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[34]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[35]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[36]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[37]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[38]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[39]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[40]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[41]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[42]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[43]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[44]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[45]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[46]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[47]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[48]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[49]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[50]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[51]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[52]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[53]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[54]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[55]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[56]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[57]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[58]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[59]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[60]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[61]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[62]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[63]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[64]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[65]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[66]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[67]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[68]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[69]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[70]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[71]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[72]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[73]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[74]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[75]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[76]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[77]}]]
connect_debug_port u_ila_1/probe2 [get_nets [list zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_val_a]]
connect_debug_port u_ila_1/probe3 [get_nets [list zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/o_rdy_a]]
connect_debug_port u_ila_1/probe4 [get_nets [list zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/o_val_b]]
connect_debug_port u_ila_0/probe8 [get_nets [list {zcash_fpga_top/control_top/debug_if/mod[0]} {zcash_fpga_top/control_top/debug_if/mod[-1]}]]
connect_debug_port u_ila_0/probe5 [get_nets [list zcash_fpga_top/control_top/debug_if2/mod]]
connect_debug_port u_ila_0/probe2 [get_nets [list {uart_wrapper/uart_axi_wdata_0[0]} {uart_wrapper/uart_axi_wdata_0[1]} {uart_wrapper/uart_axi_wdata_0[2]} {uart_wrapper/uart_axi_wdata_0[3]} {uart_wrapper/uart_axi_wdata_0[4]} {uart_wrapper/uart_axi_wdata_0[5]} {uart_wrapper/uart_axi_wdata_0[6]} {uart_wrapper/uart_axi_wdata_0[7]} {uart_wrapper/uart_axi_wdata_0[8]} {uart_wrapper/uart_axi_wdata_0[9]} {uart_wrapper/uart_axi_wdata_0[10]} {uart_wrapper/uart_axi_wdata_0[11]} {uart_wrapper/uart_axi_wdata_0[12]} {uart_wrapper/uart_axi_wdata_0[13]} {uart_wrapper/uart_axi_wdata_0[14]} {uart_wrapper/uart_axi_wdata_0[15]} {uart_wrapper/uart_axi_wdata_0[16]} {uart_wrapper/uart_axi_wdata_0[17]} {uart_wrapper/uart_axi_wdata_0[18]} {uart_wrapper/uart_axi_wdata_0[19]} {uart_wrapper/uart_axi_wdata_0[20]} {uart_wrapper/uart_axi_wdata_0[21]} {uart_wrapper/uart_axi_wdata_0[22]} {uart_wrapper/uart_axi_wdata_0[23]} {uart_wrapper/uart_axi_wdata_0[24]} {uart_wrapper/uart_axi_wdata_0[25]} {uart_wrapper/uart_axi_wdata_0[26]} {uart_wrapper/uart_axi_wdata_0[27]} {uart_wrapper/uart_axi_wdata_0[28]} {uart_wrapper/uart_axi_wdata_0[29]} {uart_wrapper/uart_axi_wdata_0[30]} {uart_wrapper/uart_axi_wdata_0[31]}]]
connect_debug_port u_ila_0/probe8 [get_nets [list {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/o_dat_b[0]}]]
connect_debug_port u_ila_0/probe11 [get_nets [list uart_wrapper/eop_l]]
connect_debug_port u_ila_0/probe17 [get_nets [list uart_wrapper/sop_l]]
connect_debug_port u_ila_1/probe4 [get_nets [list {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/o_dat_b[0]}]]
connect_debug_port u_ila_0/probe2 [get_nets [list {uart_wrapper/debug_if/dat[0]} {uart_wrapper/debug_if/dat[1]} {uart_wrapper/debug_if/dat[2]} {uart_wrapper/debug_if/dat[3]} {uart_wrapper/debug_if/dat[4]} {uart_wrapper/debug_if/dat[5]} {uart_wrapper/debug_if/dat[6]} {uart_wrapper/debug_if/dat[7]}]]
connect_debug_port u_ila_0/probe13 [get_nets [list uart_wrapper/debug_if/ctl]]
connect_debug_port u_ila_0/probe15 [get_nets [list uart_wrapper/debug_if/eop]]
connect_debug_port u_ila_0/probe16 [get_nets [list uart_wrapper/debug_if/err]]
connect_debug_port u_ila_0/probe19 [get_nets [list uart_wrapper/debug_if/mod]]
connect_debug_port u_ila_0/probe21 [get_nets [list uart_wrapper/debug_if/rdy]]
connect_debug_port u_ila_0/probe23 [get_nets [list uart_wrapper/debug_if/sop]]
connect_debug_port u_ila_0/probe31 [get_nets [list uart_wrapper/debug_if/val]]
connect_debug_port u_ila_0/probe11 [get_nets [list {zcash_fpga_top/control_top/debug_if/dat[0]} {zcash_fpga_top/control_top/debug_if/dat[1]} {zcash_fpga_top/control_top/debug_if/dat[2]} {zcash_fpga_top/control_top/debug_if/dat[3]} {zcash_fpga_top/control_top/debug_if/dat[4]} {zcash_fpga_top/control_top/debug_if/dat[5]} {zcash_fpga_top/control_top/debug_if/dat[6]} {zcash_fpga_top/control_top/debug_if/dat[7]}]]
connect_debug_port u_ila_0/probe13 [get_nets [list zcash_fpga_top/control_top/debug_if/ctl]]
connect_debug_port u_ila_0/probe14 [get_nets [list zcash_fpga_top/control_top/debug_if/eop]]
connect_debug_port u_ila_0/probe17 [get_nets [list zcash_fpga_top/control_top/debug_if/err]]
connect_debug_port u_ila_0/probe20 [get_nets [list zcash_fpga_top/control_top/debug_if/mod]]
connect_debug_port u_ila_0/probe22 [get_nets [list zcash_fpga_top/control_top/debug_if/rdy]]
connect_debug_port u_ila_0/probe23 [get_nets [list zcash_fpga_top/control_top/debug_if/sop]]
connect_debug_port u_ila_0/probe32 [get_nets [list zcash_fpga_top/control_top/debug_if/val]]
connect_debug_port u_ila_1/probe0 [get_nets [list {zcash_fpga_top/control_top/debug_if2/mod[0]} {zcash_fpga_top/control_top/debug_if2/mod[1]} {zcash_fpga_top/control_top/debug_if2/mod[2]}]]
connect_debug_port u_ila_1/probe1 [get_nets [list {zcash_fpga_top/control_top/debug_if2/dat[0]} {zcash_fpga_top/control_top/debug_if2/dat[1]} {zcash_fpga_top/control_top/debug_if2/dat[2]} {zcash_fpga_top/control_top/debug_if2/dat[3]} {zcash_fpga_top/control_top/debug_if2/dat[4]} {zcash_fpga_top/control_top/debug_if2/dat[5]} {zcash_fpga_top/control_top/debug_if2/dat[6]} {zcash_fpga_top/control_top/debug_if2/dat[7]} {zcash_fpga_top/control_top/debug_if2/dat[8]} {zcash_fpga_top/control_top/debug_if2/dat[9]} {zcash_fpga_top/control_top/debug_if2/dat[10]} {zcash_fpga_top/control_top/debug_if2/dat[11]} {zcash_fpga_top/control_top/debug_if2/dat[12]} {zcash_fpga_top/control_top/debug_if2/dat[13]} {zcash_fpga_top/control_top/debug_if2/dat[14]} {zcash_fpga_top/control_top/debug_if2/dat[15]} {zcash_fpga_top/control_top/debug_if2/dat[16]} {zcash_fpga_top/control_top/debug_if2/dat[17]} {zcash_fpga_top/control_top/debug_if2/dat[18]} {zcash_fpga_top/control_top/debug_if2/dat[19]} {zcash_fpga_top/control_top/debug_if2/dat[20]} {zcash_fpga_top/control_top/debug_if2/dat[21]} {zcash_fpga_top/control_top/debug_if2/dat[22]} {zcash_fpga_top/control_top/debug_if2/dat[23]} {zcash_fpga_top/control_top/debug_if2/dat[24]} {zcash_fpga_top/control_top/debug_if2/dat[25]} {zcash_fpga_top/control_top/debug_if2/dat[26]} {zcash_fpga_top/control_top/debug_if2/dat[27]} {zcash_fpga_top/control_top/debug_if2/dat[28]} {zcash_fpga_top/control_top/debug_if2/dat[29]} {zcash_fpga_top/control_top/debug_if2/dat[30]} {zcash_fpga_top/control_top/debug_if2/dat[31]} {zcash_fpga_top/control_top/debug_if2/dat[32]} {zcash_fpga_top/control_top/debug_if2/dat[33]} {zcash_fpga_top/control_top/debug_if2/dat[34]} {zcash_fpga_top/control_top/debug_if2/dat[35]} {zcash_fpga_top/control_top/debug_if2/dat[36]} {zcash_fpga_top/control_top/debug_if2/dat[37]} {zcash_fpga_top/control_top/debug_if2/dat[38]} {zcash_fpga_top/control_top/debug_if2/dat[39]} {zcash_fpga_top/control_top/debug_if2/dat[40]} {zcash_fpga_top/control_top/debug_if2/dat[41]} {zcash_fpga_top/control_top/debug_if2/dat[42]} {zcash_fpga_top/control_top/debug_if2/dat[43]} {zcash_fpga_top/control_top/debug_if2/dat[44]} {zcash_fpga_top/control_top/debug_if2/dat[45]} {zcash_fpga_top/control_top/debug_if2/dat[46]} {zcash_fpga_top/control_top/debug_if2/dat[47]} {zcash_fpga_top/control_top/debug_if2/dat[48]} {zcash_fpga_top/control_top/debug_if2/dat[49]} {zcash_fpga_top/control_top/debug_if2/dat[50]} {zcash_fpga_top/control_top/debug_if2/dat[51]} {zcash_fpga_top/control_top/debug_if2/dat[52]} {zcash_fpga_top/control_top/debug_if2/dat[53]} {zcash_fpga_top/control_top/debug_if2/dat[54]} {zcash_fpga_top/control_top/debug_if2/dat[55]} {zcash_fpga_top/control_top/debug_if2/dat[56]} {zcash_fpga_top/control_top/debug_if2/dat[57]} {zcash_fpga_top/control_top/debug_if2/dat[58]} {zcash_fpga_top/control_top/debug_if2/dat[59]} {zcash_fpga_top/control_top/debug_if2/dat[60]} {zcash_fpga_top/control_top/debug_if2/dat[61]} {zcash_fpga_top/control_top/debug_if2/dat[62]} {zcash_fpga_top/control_top/debug_if2/dat[63]}]]
connect_debug_port u_ila_1/probe2 [get_nets [list {zcash_fpga_top/control_top/debug_if3/dat[0]} {zcash_fpga_top/control_top/debug_if3/dat[1]} {zcash_fpga_top/control_top/debug_if3/dat[2]} {zcash_fpga_top/control_top/debug_if3/dat[3]} {zcash_fpga_top/control_top/debug_if3/dat[4]} {zcash_fpga_top/control_top/debug_if3/dat[5]} {zcash_fpga_top/control_top/debug_if3/dat[6]} {zcash_fpga_top/control_top/debug_if3/dat[7]} {zcash_fpga_top/control_top/debug_if3/dat[8]} {zcash_fpga_top/control_top/debug_if3/dat[9]} {zcash_fpga_top/control_top/debug_if3/dat[10]} {zcash_fpga_top/control_top/debug_if3/dat[11]} {zcash_fpga_top/control_top/debug_if3/dat[12]} {zcash_fpga_top/control_top/debug_if3/dat[13]} {zcash_fpga_top/control_top/debug_if3/dat[14]} {zcash_fpga_top/control_top/debug_if3/dat[15]} {zcash_fpga_top/control_top/debug_if3/dat[16]} {zcash_fpga_top/control_top/debug_if3/dat[17]} {zcash_fpga_top/control_top/debug_if3/dat[18]} {zcash_fpga_top/control_top/debug_if3/dat[19]} {zcash_fpga_top/control_top/debug_if3/dat[20]} {zcash_fpga_top/control_top/debug_if3/dat[21]} {zcash_fpga_top/control_top/debug_if3/dat[22]} {zcash_fpga_top/control_top/debug_if3/dat[23]} {zcash_fpga_top/control_top/debug_if3/dat[24]} {zcash_fpga_top/control_top/debug_if3/dat[25]} {zcash_fpga_top/control_top/debug_if3/dat[26]} {zcash_fpga_top/control_top/debug_if3/dat[27]} {zcash_fpga_top/control_top/debug_if3/dat[28]} {zcash_fpga_top/control_top/debug_if3/dat[29]} {zcash_fpga_top/control_top/debug_if3/dat[30]} {zcash_fpga_top/control_top/debug_if3/dat[31]} {zcash_fpga_top/control_top/debug_if3/dat[32]} {zcash_fpga_top/control_top/debug_if3/dat[33]} {zcash_fpga_top/control_top/debug_if3/dat[34]} {zcash_fpga_top/control_top/debug_if3/dat[35]} {zcash_fpga_top/control_top/debug_if3/dat[36]} {zcash_fpga_top/control_top/debug_if3/dat[37]} {zcash_fpga_top/control_top/debug_if3/dat[38]} {zcash_fpga_top/control_top/debug_if3/dat[39]} {zcash_fpga_top/control_top/debug_if3/dat[40]} {zcash_fpga_top/control_top/debug_if3/dat[41]} {zcash_fpga_top/control_top/debug_if3/dat[42]} {zcash_fpga_top/control_top/debug_if3/dat[43]} {zcash_fpga_top/control_top/debug_if3/dat[44]} {zcash_fpga_top/control_top/debug_if3/dat[45]} {zcash_fpga_top/control_top/debug_if3/dat[46]} {zcash_fpga_top/control_top/debug_if3/dat[47]} {zcash_fpga_top/control_top/debug_if3/dat[48]} {zcash_fpga_top/control_top/debug_if3/dat[49]} {zcash_fpga_top/control_top/debug_if3/dat[50]} {zcash_fpga_top/control_top/debug_if3/dat[51]} {zcash_fpga_top/control_top/debug_if3/dat[52]} {zcash_fpga_top/control_top/debug_if3/dat[53]} {zcash_fpga_top/control_top/debug_if3/dat[54]} {zcash_fpga_top/control_top/debug_if3/dat[55]} {zcash_fpga_top/control_top/debug_if3/dat[56]} {zcash_fpga_top/control_top/debug_if3/dat[57]} {zcash_fpga_top/control_top/debug_if3/dat[58]} {zcash_fpga_top/control_top/debug_if3/dat[59]} {zcash_fpga_top/control_top/debug_if3/dat[60]} {zcash_fpga_top/control_top/debug_if3/dat[61]} {zcash_fpga_top/control_top/debug_if3/dat[62]} {zcash_fpga_top/control_top/debug_if3/dat[63]}]]
connect_debug_port u_ila_1/probe3 [get_nets [list {zcash_fpga_top/control_top/debug_if3/mod[0]} {zcash_fpga_top/control_top/debug_if3/mod[1]} {zcash_fpga_top/control_top/debug_if3/mod[2]}]]
connect_debug_port u_ila_1/probe4 [get_nets [list zcash_fpga_top/control_top/debug_if2/ctl]]
connect_debug_port u_ila_1/probe5 [get_nets [list zcash_fpga_top/control_top/debug_if3/ctl]]
connect_debug_port u_ila_1/probe6 [get_nets [list zcash_fpga_top/control_top/debug_if3/eop]]
connect_debug_port u_ila_1/probe7 [get_nets [list zcash_fpga_top/control_top/debug_if2/eop]]
connect_debug_port u_ila_1/probe8 [get_nets [list zcash_fpga_top/control_top/debug_if2/err]]
connect_debug_port u_ila_1/probe9 [get_nets [list zcash_fpga_top/control_top/debug_if3/err]]
connect_debug_port u_ila_1/probe10 [get_nets [list zcash_fpga_top/control_top/debug_if3/rdy]]
connect_debug_port u_ila_1/probe11 [get_nets [list zcash_fpga_top/control_top/debug_if2/rdy]]
connect_debug_port u_ila_1/probe12 [get_nets [list zcash_fpga_top/control_top/debug_if3/sop]]
connect_debug_port u_ila_1/probe13 [get_nets [list zcash_fpga_top/control_top/debug_if2/sop]]
connect_debug_port u_ila_1/probe14 [get_nets [list zcash_fpga_top/control_top/debug_if2/val]]
connect_debug_port u_ila_1/probe15 [get_nets [list zcash_fpga_top/control_top/debug_if3/val]]
connect_debug_port u_ila_1/probe10 [get_nets [list {uart_wrapper/uart_debug_if/dat[0]} {uart_wrapper/uart_debug_if/dat[1]} {uart_wrapper/uart_debug_if/dat[2]} {uart_wrapper/uart_debug_if/dat[3]} {uart_wrapper/uart_debug_if/dat[4]} {uart_wrapper/uart_debug_if/dat[5]} {uart_wrapper/uart_debug_if/dat[6]} {uart_wrapper/uart_debug_if/dat[7]}]]
connect_debug_port u_ila_1/probe12 [get_nets [list uart_wrapper/uart_debug_if/ctl]]
connect_debug_port u_ila_1/probe15 [get_nets [list uart_wrapper/uart_debug_if/eop]]
connect_debug_port u_ila_1/probe16 [get_nets [list uart_wrapper/uart_debug_if/err]]
connect_debug_port u_ila_1/probe19 [get_nets [list uart_wrapper/uart_debug_if/mod]]
connect_debug_port u_ila_1/probe21 [get_nets [list uart_wrapper/uart_debug_if/rdy]]
connect_debug_port u_ila_1/probe24 [get_nets [list uart_wrapper/uart_debug_if/sop]]
connect_debug_port u_ila_1/probe31 [get_nets [list uart_wrapper/uart_debug_if/val]]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_pll/inst/clk_out300]]
connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_mmcm/inst/clk_300]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 32 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {uart_axi_wdata[0]} {uart_axi_wdata[1]} {uart_axi_wdata[2]} {uart_axi_wdata[3]} {uart_axi_wdata[4]} {uart_axi_wdata[5]} {uart_axi_wdata[6]} {uart_axi_wdata[7]} {uart_axi_wdata[8]} {uart_axi_wdata[9]} {uart_axi_wdata[10]} {uart_axi_wdata[11]} {uart_axi_wdata[12]} {uart_axi_wdata[13]} {uart_axi_wdata[14]} {uart_axi_wdata[15]} {uart_axi_wdata[16]} {uart_axi_wdata[17]} {uart_axi_wdata[18]} {uart_axi_wdata[19]} {uart_axi_wdata[20]} {uart_axi_wdata[21]} {uart_axi_wdata[22]} {uart_axi_wdata[23]} {uart_axi_wdata[24]} {uart_axi_wdata[25]} {uart_axi_wdata[26]} {uart_axi_wdata[27]} {uart_axi_wdata[28]} {uart_axi_wdata[29]} {uart_axi_wdata[30]} {uart_axi_wdata[31]}]]
set_property port_width 8 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {zcash_fpga_top/control_top/debug_if2/dat[0]} {zcash_fpga_top/control_top/debug_if2/dat[1]} {zcash_fpga_top/control_top/debug_if2/dat[2]} {zcash_fpga_top/control_top/debug_if2/dat[3]} {zcash_fpga_top/control_top/debug_if2/dat[4]} {zcash_fpga_top/control_top/debug_if2/dat[5]} {zcash_fpga_top/control_top/debug_if2/dat[6]} {zcash_fpga_top/control_top/debug_if2/dat[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 4 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {uart_axi_awaddr[0]} {uart_axi_awaddr[1]} {uart_axi_awaddr[2]} {uart_axi_awaddr[3]}]]
set_property port_width 16 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {uart_wrapper/rx_byt_len[0]} {uart_wrapper/rx_byt_len[1]} {uart_wrapper/rx_byt_len[2]} {uart_wrapper/rx_byt_len[3]} {uart_wrapper/rx_byt_len[4]} {uart_wrapper/rx_byt_len[5]} {uart_wrapper/rx_byt_len[6]} {uart_wrapper/rx_byt_len[7]} {uart_wrapper/rx_byt_len[8]} {uart_wrapper/rx_byt_len[9]} {uart_wrapper/rx_byt_len[10]} {uart_wrapper/rx_byt_len[11]} {uart_wrapper/rx_byt_len[12]} {uart_wrapper/rx_byt_len[13]} {uart_wrapper/rx_byt_len[14]} {uart_wrapper/rx_byt_len[15]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 8 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {check_rst[0]} {check_rst[1]} {check_rst[2]} {check_rst[3]} {check_rst[4]} {check_rst[5]} {check_rst[6]} {check_rst[7]}]]
set_property port_width 16 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {uart_wrapper/rx_byt_cnt[0]} {uart_wrapper/rx_byt_cnt[1]} {uart_wrapper/rx_byt_cnt[2]} {uart_wrapper/rx_byt_cnt[3]} {uart_wrapper/rx_byt_cnt[4]} {uart_wrapper/rx_byt_cnt[5]} {uart_wrapper/rx_byt_cnt[6]} {uart_wrapper/rx_byt_cnt[7]} {uart_wrapper/rx_byt_cnt[8]} {uart_wrapper/rx_byt_cnt[9]} {uart_wrapper/rx_byt_cnt[10]} {uart_wrapper/rx_byt_cnt[11]} {uart_wrapper/rx_byt_cnt[12]} {uart_wrapper/rx_byt_cnt[13]} {uart_wrapper/rx_byt_cnt[14]} {uart_wrapper/rx_byt_cnt[15]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 32 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {uart_state[0]} {uart_state[1]} {uart_state[2]} {uart_state[3]} {uart_state[4]} {uart_state[5]} {uart_state[6]} {uart_state[7]} {uart_state[8]} {uart_state[9]} {uart_state[10]} {uart_state[11]} {uart_state[12]} {uart_state[13]} {uart_state[14]} {uart_state[15]} {uart_state[16]} {uart_state[17]} {uart_state[18]} {uart_state[19]} {uart_state[20]} {uart_state[21]} {uart_state[22]} {uart_state[23]} {uart_state[24]} {uart_state[25]} {uart_state[26]} {uart_state[27]} {uart_state[28]} {uart_state[29]} {uart_state[30]} {uart_state[31]}]]
set_property port_width 16 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {uart_wrapper/tx_byt_cnt[0]} {uart_wrapper/tx_byt_cnt[1]} {uart_wrapper/tx_byt_cnt[2]} {uart_wrapper/tx_byt_cnt[3]} {uart_wrapper/tx_byt_cnt[4]} {uart_wrapper/tx_byt_cnt[5]} {uart_wrapper/tx_byt_cnt[6]} {uart_wrapper/tx_byt_cnt[7]} {uart_wrapper/tx_byt_cnt[8]} {uart_wrapper/tx_byt_cnt[9]} {uart_wrapper/tx_byt_cnt[10]} {uart_wrapper/tx_byt_cnt[11]} {uart_wrapper/tx_byt_cnt[12]} {uart_wrapper/tx_byt_cnt[13]} {uart_wrapper/tx_byt_cnt[14]} {uart_wrapper/tx_byt_cnt[15]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 2 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {uart_axi_rresp[0]} {uart_axi_rresp[1]}]]
set_property port_width 4 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {uart_wrapper/uart_axi_araddr[0]} {uart_wrapper/uart_axi_araddr[1]} {uart_wrapper/uart_axi_araddr[2]} {uart_wrapper/uart_axi_araddr[3]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 3 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {clk_out300_rst_r[0]} {clk_out300_rst_r[1]} {clk_out300_rst_r[2]}]]
set_property port_width 4 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {uart_wrapper/uart_axi_awaddr[0]} {uart_wrapper/uart_axi_awaddr[1]} {uart_wrapper/uart_axi_awaddr[2]} {uart_wrapper/uart_axi_awaddr[3]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 4 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {uart_axi_araddr[0]} {uart_axi_araddr[1]} {uart_axi_araddr[2]} {uart_axi_araddr[3]}]]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {uart_wrapper/uart_axi_bresp[1]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 32 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list {uart_axi_rdata[0]} {uart_axi_rdata[1]} {uart_axi_rdata[2]} {uart_axi_rdata[3]} {uart_axi_rdata[4]} {uart_axi_rdata[5]} {uart_axi_rdata[6]} {uart_axi_rdata[7]} {uart_axi_rdata[8]} {uart_axi_rdata[9]} {uart_axi_rdata[10]} {uart_axi_rdata[11]} {uart_axi_rdata[12]} {uart_axi_rdata[13]} {uart_axi_rdata[14]} {uart_axi_rdata[15]} {uart_axi_rdata[16]} {uart_axi_rdata[17]} {uart_axi_rdata[18]} {uart_axi_rdata[19]} {uart_axi_rdata[20]} {uart_axi_rdata[21]} {uart_axi_rdata[22]} {uart_axi_rdata[23]} {uart_axi_rdata[24]} {uart_axi_rdata[25]} {uart_axi_rdata[26]} {uart_axi_rdata[27]} {uart_axi_rdata[28]} {uart_axi_rdata[29]} {uart_axi_rdata[30]} {uart_axi_rdata[31]}]]
set_property port_width 8 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list {uart_wrapper/txuart_debug_if/dat[0]} {uart_wrapper/txuart_debug_if/dat[1]} {uart_wrapper/txuart_debug_if/dat[2]} {uart_wrapper/txuart_debug_if/dat[3]} {uart_wrapper/txuart_debug_if/dat[4]} {uart_wrapper/txuart_debug_if/dat[5]} {uart_wrapper/txuart_debug_if/dat[6]} {uart_wrapper/txuart_debug_if/dat[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list interrupt]]
set_property port_width 16 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list {uart_wrapper/tx_byt_len[0]} {uart_wrapper/tx_byt_len[1]} {uart_wrapper/tx_byt_len[2]} {uart_wrapper/tx_byt_len[3]} {uart_wrapper/tx_byt_len[4]} {uart_wrapper/tx_byt_len[5]} {uart_wrapper/tx_byt_len[6]} {uart_wrapper/tx_byt_len[7]} {uart_wrapper/tx_byt_len[8]} {uart_wrapper/tx_byt_len[9]} {uart_wrapper/tx_byt_len[10]} {uart_wrapper/tx_byt_len[11]} {uart_wrapper/tx_byt_len[12]} {uart_wrapper/tx_byt_len[13]} {uart_wrapper/tx_byt_len[14]} {uart_wrapper/tx_byt_len[15]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list uart_axi_arready]]
set_property port_width 32 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list {uart_wrapper/uart_axi_rdata[0]} {uart_wrapper/uart_axi_rdata[1]} {uart_wrapper/uart_axi_rdata[2]} {uart_wrapper/uart_axi_rdata[3]} {uart_wrapper/uart_axi_rdata[4]} {uart_wrapper/uart_axi_rdata[5]} {uart_wrapper/uart_axi_rdata[6]} {uart_wrapper/uart_axi_rdata[7]} {uart_wrapper/uart_axi_rdata[8]} {uart_wrapper/uart_axi_rdata[9]} {uart_wrapper/uart_axi_rdata[10]} {uart_wrapper/uart_axi_rdata[11]} {uart_wrapper/uart_axi_rdata[12]} {uart_wrapper/uart_axi_rdata[13]} {uart_wrapper/uart_axi_rdata[14]} {uart_wrapper/uart_axi_rdata[15]} {uart_wrapper/uart_axi_rdata[16]} {uart_wrapper/uart_axi_rdata[17]} {uart_wrapper/uart_axi_rdata[18]} {uart_wrapper/uart_axi_rdata[19]} {uart_wrapper/uart_axi_rdata[20]} {uart_wrapper/uart_axi_rdata[21]} {uart_wrapper/uart_axi_rdata[22]} {uart_wrapper/uart_axi_rdata[23]} {uart_wrapper/uart_axi_rdata[24]} {uart_wrapper/uart_axi_rdata[25]} {uart_wrapper/uart_axi_rdata[26]} {uart_wrapper/uart_axi_rdata[27]} {uart_wrapper/uart_axi_rdata[28]} {uart_wrapper/uart_axi_rdata[29]} {uart_wrapper/uart_axi_rdata[30]} {uart_wrapper/uart_axi_rdata[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list uart_axi_arvalid]]
set_property port_width 8 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list {uart_wrapper/rxuart_debug_if/dat[0]} {uart_wrapper/rxuart_debug_if/dat[1]} {uart_wrapper/rxuart_debug_if/dat[2]} {uart_wrapper/rxuart_debug_if/dat[3]} {uart_wrapper/rxuart_debug_if/dat[4]} {uart_wrapper/rxuart_debug_if/dat[5]} {uart_wrapper/rxuart_debug_if/dat[6]} {uart_wrapper/rxuart_debug_if/dat[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list uart_axi_awready]]
set_property port_width 2 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list {uart_wrapper/uart_axi_rresp[0]} {uart_wrapper/uart_axi_rresp[1]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list uart_axi_awvalid]]
set_property port_width 32 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list {uart_wrapper/uart_axi_wdata[0]} {uart_wrapper/uart_axi_wdata[1]} {uart_wrapper/uart_axi_wdata[2]} {uart_wrapper/uart_axi_wdata[3]} {uart_wrapper/uart_axi_wdata[4]} {uart_wrapper/uart_axi_wdata[5]} {uart_wrapper/uart_axi_wdata[6]} {uart_wrapper/uart_axi_wdata[7]} {uart_wrapper/uart_axi_wdata[8]} {uart_wrapper/uart_axi_wdata[9]} {uart_wrapper/uart_axi_wdata[10]} {uart_wrapper/uart_axi_wdata[11]} {uart_wrapper/uart_axi_wdata[12]} {uart_wrapper/uart_axi_wdata[13]} {uart_wrapper/uart_axi_wdata[14]} {uart_wrapper/uart_axi_wdata[15]} {uart_wrapper/uart_axi_wdata[16]} {uart_wrapper/uart_axi_wdata[17]} {uart_wrapper/uart_axi_wdata[18]} {uart_wrapper/uart_axi_wdata[19]} {uart_wrapper/uart_axi_wdata[20]} {uart_wrapper/uart_axi_wdata[21]} {uart_wrapper/uart_axi_wdata[22]} {uart_wrapper/uart_axi_wdata[23]} {uart_wrapper/uart_axi_wdata[24]} {uart_wrapper/uart_axi_wdata[25]} {uart_wrapper/uart_axi_wdata[26]} {uart_wrapper/uart_axi_wdata[27]} {uart_wrapper/uart_axi_wdata[28]} {uart_wrapper/uart_axi_wdata[29]} {uart_wrapper/uart_axi_wdata[30]} {uart_wrapper/uart_axi_wdata[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list uart_axi_rvalid]]
set_property port_width 32 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list {uart_wrapper/uart_state[0]} {uart_wrapper/uart_state[1]} {uart_wrapper/uart_state[2]} {uart_wrapper/uart_state[3]} {uart_wrapper/uart_state[4]} {uart_wrapper/uart_state[5]} {uart_wrapper/uart_state[6]} {uart_wrapper/uart_state[7]} {uart_wrapper/uart_state[8]} {uart_wrapper/uart_state[9]} {uart_wrapper/uart_state[10]} {uart_wrapper/uart_state[11]} {uart_wrapper/uart_state[12]} {uart_wrapper/uart_state[13]} {uart_wrapper/uart_state[14]} {uart_wrapper/uart_state[15]} {uart_wrapper/uart_state[16]} {uart_wrapper/uart_state[17]} {uart_wrapper/uart_state[18]} {uart_wrapper/uart_state[19]} {uart_wrapper/uart_state[20]} {uart_wrapper/uart_state[21]} {uart_wrapper/uart_state[22]} {uart_wrapper/uart_state[23]} {uart_wrapper/uart_state[24]} {uart_wrapper/uart_state[25]} {uart_wrapper/uart_state[26]} {uart_wrapper/uart_state[27]} {uart_wrapper/uart_state[28]} {uart_wrapper/uart_state[29]} {uart_wrapper/uart_state[30]} {uart_wrapper/uart_state[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list usb_uart_rxd_OBUF]]
connect_debug_port u_ila_0/probe14 [get_nets [list uart_wrapper/rxuart_debug_if/ctl]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list uart_wrapper/txuart_debug_if/ctl]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list zcash_fpga_top/control_top/debug_if2/ctl]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list uart_wrapper/rxuart_debug_if/eop]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list uart_wrapper/txuart_debug_if/eop]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list zcash_fpga_top/control_top/debug_if2/eop]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
connect_debug_port u_ila_0/probe20 [get_nets [list uart_wrapper/txuart_debug_if/err]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
connect_debug_port u_ila_0/probe21 [get_nets [list zcash_fpga_top/control_top/debug_if2/err]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
set_property port_width 1 [get_debug_ports u_ila_0/probe22]
connect_debug_port u_ila_0/probe22 [get_nets [list uart_wrapper/rxuart_debug_if/err]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
set_property port_width 1 [get_debug_ports u_ila_0/probe23]
connect_debug_port u_ila_0/probe23 [get_nets [list uart_wrapper/interrupt]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
set_property port_width 1 [get_debug_ports u_ila_0/probe24]
connect_debug_port u_ila_0/probe24 [get_nets [list uart_wrapper/txuart_debug_if/mod]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
set_property port_width 1 [get_debug_ports u_ila_0/probe25]
connect_debug_port u_ila_0/probe25 [get_nets [list uart_wrapper/rxuart_debug_if/mod]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
set_property port_width 1 [get_debug_ports u_ila_0/probe26]
connect_debug_port u_ila_0/probe26 [get_nets [list zcash_fpga_top/control_top/debug_if2/mod]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
set_property port_width 1 [get_debug_ports u_ila_0/probe27]
connect_debug_port u_ila_0/probe27 [get_nets [list zcash_fpga_top/control_top/debug_if2/rdy]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
set_property port_width 1 [get_debug_ports u_ila_0/probe28]
connect_debug_port u_ila_0/probe28 [get_nets [list uart_wrapper/rxuart_debug_if/rdy]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
set_property port_width 1 [get_debug_ports u_ila_0/probe29]
connect_debug_port u_ila_0/probe29 [get_nets [list uart_wrapper/txuart_debug_if/rdy]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
connect_debug_port u_ila_0/probe30 [get_nets [list zcash_fpga_top/control_top/debug_if2/sop]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
connect_debug_port u_ila_0/probe31 [get_nets [list uart_wrapper/txuart_debug_if/sop]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
connect_debug_port u_ila_0/probe32 [get_nets [list uart_wrapper/rxuart_debug_if/sop]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
connect_debug_port u_ila_0/probe33 [get_nets [list uart_wrapper/uart_axi_arready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
connect_debug_port u_ila_0/probe34 [get_nets [list uart_wrapper/uart_axi_arvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
connect_debug_port u_ila_0/probe35 [get_nets [list uart_wrapper/uart_axi_awready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
connect_debug_port u_ila_0/probe36 [get_nets [list uart_wrapper/uart_axi_awvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
connect_debug_port u_ila_0/probe37 [get_nets [list uart_wrapper/uart_axi_rvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
connect_debug_port u_ila_0/probe38 [get_nets [list uart_wrapper/uart_axi_wready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
connect_debug_port u_ila_0/probe39 [get_nets [list uart_wrapper/txuart_debug_if/val]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
connect_debug_port u_ila_0/probe40 [get_nets [list zcash_fpga_top/control_top/debug_if2/val]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
connect_debug_port u_ila_0/probe41 [get_nets [list uart_wrapper/rxuart_debug_if/val]]
create_debug_core u_ila_1 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_1]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
set_property port_width 1 [get_debug_ports u_ila_1/clk]
connect_debug_port u_ila_1/clk [get_nets [list clk_wiz_pll/inst/clk_out100]]
connect_debug_port u_ila_1/clk [get_nets [list clk_wiz_mmcm/inst/clk_200]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
set_property port_width 3 [get_debug_ports u_ila_1/probe0]
connect_debug_port u_ila_1/probe0 [get_nets [list {clk_out100_rst_r[0]} {clk_out100_rst_r[1]} {clk_out100_rst_r[2]}]]
connect_debug_port u_ila_1/probe0 [get_nets [list {zcash_fpga_top/control_top/debug_if0/mod[0]} {zcash_fpga_top/control_top/debug_if0/mod[1]} {zcash_fpga_top/control_top/debug_if0/mod[2]}]]
create_debug_port u_ila_1 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
set_property port_width 64 [get_debug_ports u_ila_1/probe1]
connect_debug_port u_ila_1/probe1 [get_nets [list {zcash_fpga_top/control_top/debug_if1/dat[0]} {zcash_fpga_top/control_top/debug_if1/dat[1]} {zcash_fpga_top/control_top/debug_if1/dat[2]} {zcash_fpga_top/control_top/debug_if1/dat[3]} {zcash_fpga_top/control_top/debug_if1/dat[4]} {zcash_fpga_top/control_top/debug_if1/dat[5]} {zcash_fpga_top/control_top/debug_if1/dat[6]} {zcash_fpga_top/control_top/debug_if1/dat[7]} {zcash_fpga_top/control_top/debug_if1/dat[8]} {zcash_fpga_top/control_top/debug_if1/dat[9]} {zcash_fpga_top/control_top/debug_if1/dat[10]} {zcash_fpga_top/control_top/debug_if1/dat[11]} {zcash_fpga_top/control_top/debug_if1/dat[12]} {zcash_fpga_top/control_top/debug_if1/dat[13]} {zcash_fpga_top/control_top/debug_if1/dat[14]} {zcash_fpga_top/control_top/debug_if1/dat[15]} {zcash_fpga_top/control_top/debug_if1/dat[16]} {zcash_fpga_top/control_top/debug_if1/dat[17]} {zcash_fpga_top/control_top/debug_if1/dat[18]} {zcash_fpga_top/control_top/debug_if1/dat[19]} {zcash_fpga_top/control_top/debug_if1/dat[20]} {zcash_fpga_top/control_top/debug_if1/dat[21]} {zcash_fpga_top/control_top/debug_if1/dat[22]} {zcash_fpga_top/control_top/debug_if1/dat[23]} {zcash_fpga_top/control_top/debug_if1/dat[24]} {zcash_fpga_top/control_top/debug_if1/dat[25]} {zcash_fpga_top/control_top/debug_if1/dat[26]} {zcash_fpga_top/control_top/debug_if1/dat[27]} {zcash_fpga_top/control_top/debug_if1/dat[28]} {zcash_fpga_top/control_top/debug_if1/dat[29]} {zcash_fpga_top/control_top/debug_if1/dat[30]} {zcash_fpga_top/control_top/debug_if1/dat[31]} {zcash_fpga_top/control_top/debug_if1/dat[32]} {zcash_fpga_top/control_top/debug_if1/dat[33]} {zcash_fpga_top/control_top/debug_if1/dat[34]} {zcash_fpga_top/control_top/debug_if1/dat[35]} {zcash_fpga_top/control_top/debug_if1/dat[36]} {zcash_fpga_top/control_top/debug_if1/dat[37]} {zcash_fpga_top/control_top/debug_if1/dat[38]} {zcash_fpga_top/control_top/debug_if1/dat[39]} {zcash_fpga_top/control_top/debug_if1/dat[40]} {zcash_fpga_top/control_top/debug_if1/dat[41]} {zcash_fpga_top/control_top/debug_if1/dat[42]} {zcash_fpga_top/control_top/debug_if1/dat[43]} {zcash_fpga_top/control_top/debug_if1/dat[44]} {zcash_fpga_top/control_top/debug_if1/dat[45]} {zcash_fpga_top/control_top/debug_if1/dat[46]} {zcash_fpga_top/control_top/debug_if1/dat[47]} {zcash_fpga_top/control_top/debug_if1/dat[48]} {zcash_fpga_top/control_top/debug_if1/dat[49]} {zcash_fpga_top/control_top/debug_if1/dat[50]} {zcash_fpga_top/control_top/debug_if1/dat[51]} {zcash_fpga_top/control_top/debug_if1/dat[52]} {zcash_fpga_top/control_top/debug_if1/dat[53]} {zcash_fpga_top/control_top/debug_if1/dat[54]} {zcash_fpga_top/control_top/debug_if1/dat[55]} {zcash_fpga_top/control_top/debug_if1/dat[56]} {zcash_fpga_top/control_top/debug_if1/dat[57]} {zcash_fpga_top/control_top/debug_if1/dat[58]} {zcash_fpga_top/control_top/debug_if1/dat[59]} {zcash_fpga_top/control_top/debug_if1/dat[60]} {zcash_fpga_top/control_top/debug_if1/dat[61]} {zcash_fpga_top/control_top/debug_if1/dat[62]} {zcash_fpga_top/control_top/debug_if1/dat[63]}]]
create_debug_port u_ila_1 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
set_property port_width 3 [get_debug_ports u_ila_1/probe2]
connect_debug_port u_ila_1/probe2 [get_nets [list {zcash_fpga_top/control_top/debug_if1/mod[0]} {zcash_fpga_top/control_top/debug_if1/mod[1]} {zcash_fpga_top/control_top/debug_if1/mod[2]}]]
create_debug_port u_ila_1 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
set_property port_width 64 [get_debug_ports u_ila_1/probe3]
connect_debug_port u_ila_1/probe3 [get_nets [list {zcash_fpga_top/control_top/debug_if0/dat[0]} {zcash_fpga_top/control_top/debug_if0/dat[1]} {zcash_fpga_top/control_top/debug_if0/dat[2]} {zcash_fpga_top/control_top/debug_if0/dat[3]} {zcash_fpga_top/control_top/debug_if0/dat[4]} {zcash_fpga_top/control_top/debug_if0/dat[5]} {zcash_fpga_top/control_top/debug_if0/dat[6]} {zcash_fpga_top/control_top/debug_if0/dat[7]} {zcash_fpga_top/control_top/debug_if0/dat[8]} {zcash_fpga_top/control_top/debug_if0/dat[9]} {zcash_fpga_top/control_top/debug_if0/dat[10]} {zcash_fpga_top/control_top/debug_if0/dat[11]} {zcash_fpga_top/control_top/debug_if0/dat[12]} {zcash_fpga_top/control_top/debug_if0/dat[13]} {zcash_fpga_top/control_top/debug_if0/dat[14]} {zcash_fpga_top/control_top/debug_if0/dat[15]} {zcash_fpga_top/control_top/debug_if0/dat[16]} {zcash_fpga_top/control_top/debug_if0/dat[17]} {zcash_fpga_top/control_top/debug_if0/dat[18]} {zcash_fpga_top/control_top/debug_if0/dat[19]} {zcash_fpga_top/control_top/debug_if0/dat[20]} {zcash_fpga_top/control_top/debug_if0/dat[21]} {zcash_fpga_top/control_top/debug_if0/dat[22]} {zcash_fpga_top/control_top/debug_if0/dat[23]} {zcash_fpga_top/control_top/debug_if0/dat[24]} {zcash_fpga_top/control_top/debug_if0/dat[25]} {zcash_fpga_top/control_top/debug_if0/dat[26]} {zcash_fpga_top/control_top/debug_if0/dat[27]} {zcash_fpga_top/control_top/debug_if0/dat[28]} {zcash_fpga_top/control_top/debug_if0/dat[29]} {zcash_fpga_top/control_top/debug_if0/dat[30]} {zcash_fpga_top/control_top/debug_if0/dat[31]} {zcash_fpga_top/control_top/debug_if0/dat[32]} {zcash_fpga_top/control_top/debug_if0/dat[33]} {zcash_fpga_top/control_top/debug_if0/dat[34]} {zcash_fpga_top/control_top/debug_if0/dat[35]} {zcash_fpga_top/control_top/debug_if0/dat[36]} {zcash_fpga_top/control_top/debug_if0/dat[37]} {zcash_fpga_top/control_top/debug_if0/dat[38]} {zcash_fpga_top/control_top/debug_if0/dat[39]} {zcash_fpga_top/control_top/debug_if0/dat[40]} {zcash_fpga_top/control_top/debug_if0/dat[41]} {zcash_fpga_top/control_top/debug_if0/dat[42]} {zcash_fpga_top/control_top/debug_if0/dat[43]} {zcash_fpga_top/control_top/debug_if0/dat[44]} {zcash_fpga_top/control_top/debug_if0/dat[45]} {zcash_fpga_top/control_top/debug_if0/dat[46]} {zcash_fpga_top/control_top/debug_if0/dat[47]} {zcash_fpga_top/control_top/debug_if0/dat[48]} {zcash_fpga_top/control_top/debug_if0/dat[49]} {zcash_fpga_top/control_top/debug_if0/dat[50]} {zcash_fpga_top/control_top/debug_if0/dat[51]} {zcash_fpga_top/control_top/debug_if0/dat[52]} {zcash_fpga_top/control_top/debug_if0/dat[53]} {zcash_fpga_top/control_top/debug_if0/dat[54]} {zcash_fpga_top/control_top/debug_if0/dat[55]} {zcash_fpga_top/control_top/debug_if0/dat[56]} {zcash_fpga_top/control_top/debug_if0/dat[57]} {zcash_fpga_top/control_top/debug_if0/dat[58]} {zcash_fpga_top/control_top/debug_if0/dat[59]} {zcash_fpga_top/control_top/debug_if0/dat[60]} {zcash_fpga_top/control_top/debug_if0/dat[61]} {zcash_fpga_top/control_top/debug_if0/dat[62]} {zcash_fpga_top/control_top/debug_if0/dat[63]}]]
create_debug_port u_ila_1 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
set_property port_width 1 [get_debug_ports u_ila_1/probe4]
connect_debug_port u_ila_1/probe4 [get_nets [list zcash_fpga_top/control_top/debug_if0/ctl]]
create_debug_port u_ila_1 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
set_property port_width 1 [get_debug_ports u_ila_1/probe5]
connect_debug_port u_ila_1/probe5 [get_nets [list zcash_fpga_top/control_top/debug_if1/ctl]]
create_debug_port u_ila_1 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
set_property port_width 1 [get_debug_ports u_ila_1/probe6]
connect_debug_port u_ila_1/probe6 [get_nets [list zcash_fpga_top/control_top/debug_if1/eop]]
create_debug_port u_ila_1 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7]
set_property port_width 1 [get_debug_ports u_ila_1/probe7]
connect_debug_port u_ila_1/probe7 [get_nets [list zcash_fpga_top/control_top/debug_if0/eop]]
create_debug_port u_ila_1 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8]
set_property port_width 1 [get_debug_ports u_ila_1/probe8]
connect_debug_port u_ila_1/probe8 [get_nets [list zcash_fpga_top/control_top/debug_if0/err]]
create_debug_port u_ila_1 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9]
set_property port_width 1 [get_debug_ports u_ila_1/probe9]
connect_debug_port u_ila_1/probe9 [get_nets [list zcash_fpga_top/control_top/debug_if1/err]]
create_debug_port u_ila_1 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10]
set_property port_width 1 [get_debug_ports u_ila_1/probe10]
connect_debug_port u_ila_1/probe10 [get_nets [list zcash_fpga_top/control_top/debug_if0/rdy]]
create_debug_port u_ila_1 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe11]
set_property port_width 1 [get_debug_ports u_ila_1/probe11]
connect_debug_port u_ila_1/probe11 [get_nets [list zcash_fpga_top/control_top/debug_if1/rdy]]
create_debug_port u_ila_1 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe12]
set_property port_width 1 [get_debug_ports u_ila_1/probe12]
connect_debug_port u_ila_1/probe12 [get_nets [list zcash_fpga_top/control_top/debug_if1/sop]]
create_debug_port u_ila_1 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe13]
set_property port_width 1 [get_debug_ports u_ila_1/probe13]
connect_debug_port u_ila_1/probe13 [get_nets [list zcash_fpga_top/control_top/debug_if0/sop]]
create_debug_port u_ila_1 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe14]
set_property port_width 1 [get_debug_ports u_ila_1/probe14]
connect_debug_port u_ila_1/probe14 [get_nets [list zcash_fpga_top/control_top/debug_if0/val]]
create_debug_port u_ila_1 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe15]
set_property port_width 1 [get_debug_ports u_ila_1/probe15]
connect_debug_port u_ila_1/probe15 [get_nets [list zcash_fpga_top/control_top/debug_if1/val]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk_out100]
connect_debug_port dbg_hub/clk [get_nets clk_200]

5
zcash_fpga/src/rtl/control/control_top.sv
View File

@ -64,6 +64,11 @@ if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BYTS(1)) rx_typ1_if (i_clk_core);
if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BYTS(1)) tx_arb_in_if [2] (i_clk_core);
if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BYTS(1)) tx_int_if (i_clk_core);
debug_if #(.DAT_BYTS (CORE_DAT_BYTS), .CTL_BITS (1)) debug_if_rx (.i_if(rx_int_if));
debug_if #(.DAT_BYTS (CORE_DAT_BYTS), .CTL_BITS (1)) debug_if_tx (.i_if(tx_int_if));
typedef enum {TYP0_IDLE = 0,
TYP0_SEND_STATUS = 1,
TYP0_RESET_FPGA = 2,

23
zcash_fpga/src/tb/control_top_tb.sv
View File

@ -27,7 +27,7 @@ localparam CORE_CLK_PERIOD = 600;
localparam UART_CLK_PERIOD = 1000;
localparam CORE_BYTS = 8;
localparam UART_BYTS = 4; // Use real value TODO
localparam UART_BYTS = 1;
logic core_clk, core_rst, uart_clk, uart_rst, usr_rst;
@ -36,6 +36,9 @@ logic equihash_mask_val;
if_axi_stream #(.DAT_BYTS(CORE_BYTS)) equihash_axi(core_clk);
if_axi_stream #(.DAT_BYTS(CORE_BYTS)) secp256k1_tx_if(core_clk);
if_axi_stream #(.DAT_BYTS(CORE_BYTS)) secp256k1_rx_if(core_clk);
if_axi_stream #(.DAT_BYTS(UART_BYTS)) uart_rx_if (uart_clk);
if_axi_stream #(.DAT_BYTS(UART_BYTS)) uart_tx_if (uart_clk);
@ -59,20 +62,28 @@ initial begin
forever #UART_CLK_PERIOD uart_clk = ~uart_clk;
end
always_comb begin
secp256k1_tx_if.reset_source();
secp256k1_tx_if.rdy = 1;
end
control_top #(
.IN_DAT_BYTS(UART_BYTS)
)
DUT (
.i_clk_core ( core_clk ),
.i_rst_core ( core_rst ),
.i_rst_core_perm (core_rst),
.o_usr_rst ( usr_rst ),
.i_clk_if ( uart_clk ),
.i_rst_if ( uart_rst ),
.rx_if ( uart_tx_if ),
.tx_if ( uart_rx_if ),
.o_equihash_axi ( equihash_axi ),
.o_equihash_if ( equihash_axi ),
.i_equihash_mask ( equihash_mask ),
.i_equihash_mask_val ( equihash_mask_val )
.i_equihash_mask_val ( equihash_mask_val ),
.o_secp256k1_if( secp256k1_tx_if ),
.i_secp256k1_if( secp256k1_tx_if )
);
// This is a tests sending a request for FPGA status
@ -89,7 +100,7 @@ begin
fork
uart_tx_if.put_stream(header, $bits(header)/8);
uart_rx_if.get_stream(get_dat, get_len);
uart_rx_if.get_stream(get_dat, get_len, 0);
join
fpga_status_rpl = get_dat;
@ -99,8 +110,8 @@ begin
fail |= fpga_status_rpl.hdr.len != get_len;
fail |= fpga_status_rpl.version != FPGA_VERSION;
fail |= fpga_status_rpl.build_host != "test";
fail |= fpga_status_rpl.build_date != "20180311";
fail |= fpga_status_rpl.fpga_state != 0;
fail |= fpga_status_rpl.build_date != "20180311";
fail |= fpga_status_rpl.fpga_state != 0;
assert (~fail) else $fatal(1, "%m %t ERROR: test_status_message status reply was wrong:\n%p", $time, fpga_status_rpl);

80
zcash_fpga/synth/zcash_fpga_top.xdc
View File

@ -65,3 +65,83 @@ set_property PULLUP true [get_ports i_rst_core0]
set_property PACKAGE_PIN AR15 [get_ports i_clk_core1]
set_property PACKAGE_PIN AR14 [get_ports i_clk_core0]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_mmcm/inst/clk_300]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 20 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[0]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[1]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[2]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[3]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[4]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[5]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[6]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[7]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[8]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[9]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[10]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[11]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[12]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[13]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[14]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[15]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[16]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[17]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[18]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[19]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 4 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {uart_axi_awaddr[0]} {uart_axi_awaddr[1]} {uart_axi_awaddr[2]} {uart_axi_awaddr[3]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 4 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {uart_axi_araddr[0]} {uart_axi_araddr[1]} {uart_axi_araddr[2]} {uart_axi_araddr[3]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 32 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {uart_axi_rdata[0]} {uart_axi_rdata[1]} {uart_axi_rdata[2]} {uart_axi_rdata[3]} {uart_axi_rdata[4]} {uart_axi_rdata[5]} {uart_axi_rdata[6]} {uart_axi_rdata[7]} {uart_axi_rdata[8]} {uart_axi_rdata[9]} {uart_axi_rdata[10]} {uart_axi_rdata[11]} {uart_axi_rdata[12]} {uart_axi_rdata[13]} {uart_axi_rdata[14]} {uart_axi_rdata[15]} {uart_axi_rdata[16]} {uart_axi_rdata[17]} {uart_axi_rdata[18]} {uart_axi_rdata[19]} {uart_axi_rdata[20]} {uart_axi_rdata[21]} {uart_axi_rdata[22]} {uart_axi_rdata[23]} {uart_axi_rdata[24]} {uart_axi_rdata[25]} {uart_axi_rdata[26]} {uart_axi_rdata[27]} {uart_axi_rdata[28]} {uart_axi_rdata[29]} {uart_axi_rdata[30]} {uart_axi_rdata[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 32 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {uart_axi_wdata[0]} {uart_axi_wdata[1]} {uart_axi_wdata[2]} {uart_axi_wdata[3]} {uart_axi_wdata[4]} {uart_axi_wdata[5]} {uart_axi_wdata[6]} {uart_axi_wdata[7]} {uart_axi_wdata[8]} {uart_axi_wdata[9]} {uart_axi_wdata[10]} {uart_axi_wdata[11]} {uart_axi_wdata[12]} {uart_axi_wdata[13]} {uart_axi_wdata[14]} {uart_axi_wdata[15]} {uart_axi_wdata[16]} {uart_axi_wdata[17]} {uart_axi_wdata[18]} {uart_axi_wdata[19]} {uart_axi_wdata[20]} {uart_axi_wdata[21]} {uart_axi_wdata[22]} {uart_axi_wdata[23]} {uart_axi_wdata[24]} {uart_axi_wdata[25]} {uart_axi_wdata[26]} {uart_axi_wdata[27]} {uart_axi_wdata[28]} {uart_axi_wdata[29]} {uart_axi_wdata[30]} {uart_axi_wdata[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 2 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {uart_axi_rresp[0]} {uart_axi_rresp[1]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list eop_l]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_val_a]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list interrupt]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list sop_l]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list uart_axi_arready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list uart_axi_arvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list uart_axi_awready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list uart_axi_awvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list uart_axi_rvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list uart_axi_wready]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk_300]