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@ -12,6 +12,12 @@ This is the top level for the Zcash verification FPGA board. It targets both Xil
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Architecture document is [here]()
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Contains the following top-level engine:
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### Equihash verification engine
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### EC secp256k1 signature verification engine
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### EC bls12-381 co-processor
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## ip_cores
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These contain custom IP cores used in the projects in this repo.
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