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# Hello World CL Example
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## :exclamation: NOTE: If this is your first time using F1, you should read [How To Create an Amazon FPGA Image (AFI) From One of The CL Examples: Step-by-Step Guide](./../../../README.md) first!!
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## Table of Contents
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1. [Overview](#overview)
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2. [Functional Description](#description)
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3. [Hello World Example Metadata](#metadata)
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<a name="overview"></a>
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## Overview
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This simple *hello_world* example builds a Custom Logic (CL) that will enable the instance to "peek" and "poke" registers in the Custom Logic (CL).
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These registers will be in the memory space behind AppPF BAR0, which is the ocl\_cl\_ AXI-lite bus on the Shell to CL interface.
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This example demonstrate a basic use-case of the Virtual LED and Virtual DIP switches.
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All of the unused interfaces between AWS Shell and the CL are tied to fixed values, and it is recommended that the developer use similar values for every unused interface in the developer's CL.
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<a name="description"></a>
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## Functional Description
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The cl_hello_world example demonstrates basic Shell-to-CL connectivity, memory-mapped register instantiations and the use of the Virtual LED and DIP switches. The cl_hello_world example implements two registers in the FPGA AppPF BAR0 memory space connected to the OCL AXI-L interface. The two registers are:
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1. Hello World Register (offset 0x500)
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2. Virtual LED Register (offset 0x504)
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Please refer to the [FPGA PCIe memory space overview](../../../docs/AWS_Fpga_Pcie_Memory_Map.md)
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The Hello World Register is a 32-bit read/write register. However, in order to demonstrate that the register is being accessed correctly, the read data returned for the register will be byte swapped.
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The Virtual LED register is a 16-bit read-only register that shadows the lower 16 bits of the Hello World Register such that it will hold the same value as bits 15:0 of the Hello World Register.
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The cl_hello_world design utilizes the Virtual LED and DIP switch interface which consistes of two signals described in the [cl_ports.vh] (./../../../common/shell_stable/design/interfaces/cl_ports.vh) file:
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```
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input[15:0] sh_cl_status_vdip, //Virtual DIP switches. Controlled through FPGA management PF and tools.
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output logic[15:0] cl_sh_status_vled, //Virtual LEDs, monitored through FPGA management PF and tools
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```
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In this example the Virtual LED Register is used to drive the Virtual LED signal, cl_sh_status_vled. In addition, the Virtual DIP switch, sh_cl_status_vdip, is used to gate the Virtual LED Register value sent to the Virtual LEDs. So, for example, if the sh_cl_status_vdip is set to 16'h00FF, then only the lower 8 bits of the Virtual LED Register will be signaled on the Virtual LED signal cl_sh_status_vled.
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While running on F1, the developer can use the FPGA tools `fpga-get-virtual-led` to read the LED values on the CL-to-Shell interface. While `fpga-set-virtual-dip-switch` tool is used to set the DIP switch values on the Shell-to-CL interface.
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### Unused interfaces
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The Hello World example does not use most of AWS Shell interface, hence the unused signals are tied off.
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At the end of `cl_hello_world.sv` file, there is a specific `include` command for an interface-specific `.inc` file, to handle the tie-off\'s for every unused interface.
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<a name="metadata"></a>
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## Hello World Example Metadata
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The following table displays information about the CL that is required to register it as an AFI with AWS.
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Alternatively, you can directly use a pre-generated AFI for this CL.
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| Key | Value |
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|-----------|------|
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| Shell Version | 0x04261818 |
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| PCI Device ID | 0xF000 |
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| PCI Vendor ID | 0x1D0F (Amazon) |
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| PCI Subsystem ID | 0x1D51 |
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| PCI Subsystem Vendor ID | 0xFEDD |
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| Pre-generated AFI ID | afi-03d11a4ea66e883ef |
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| Pre-generated AGFI ID | agfi-0fcf87119b8e97bf3 |
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# How to build and submit your Custom Logic (CL) to AWS
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# Table of Contents
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1. [Overview of AFI Build process](#buildoverview)
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2. [Build procedure step by step](#stepbystep)
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3. [Build strategies and parallel builds](#strategies)
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4. [About Encryption during build process](#buildencryption)
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5. [Advanced Notes](#buildadvanced_notes)
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6. [Build Frequently Asked Questions](#buildfaq)
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<a name="buildoverview"></a>
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## Overview
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Once the developer has a functional design, the next steps are to: synthesize the design into basic FPGA cells, perform place-and-route, and check that the design meets the timing/frequency constraints. This could be an iterative process. Upon success, the developer will need to pass the output of the flow to AWS for final AFI creation.
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The developer needs to transfer to AWS a tar file that includes the encrypted placed-and-routed design checkpoint (referred to as DCP throughout this document) and [manifest](./../../../../docs/AFI_Manifest.md). The DCP includes the complete developer design that meets timing/frequency constraints, placement boundaries within the allocated CL area on the FPGA, and the functional requirements laid out in the [Shell Interface Specification](./../../../../docs/AWS_Shell_Interface_Specification.md#overview). The [manifest.txt](./../../../../docs/AFI_Manifest.md) should include key parameters needed for registering and loading the AFI, such as target frequency.
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To assist in this process, AWS provides a reference DCP that includes the shell (SH) logic with a black-boxed CL under: `$HDK_SHELL_DIR/build/checkpoints/from_aws/SH_CL_BB_routed.dcp`
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AWS also provides an out-of-the-box generic script called `aws_build_dcp_from_cl.sh` that is used to test compile a few examples, such as the `cl_hello_world` design, as if they were developer code. These reference examples can serve as starting points for new designs. The output of the AWS-provided scripts will create a tar file, with both the encrypted placed-and-routed DCP and the corresponding `manifest.txt`, which AWS will use to generate the final bitstream.
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AWS provides multiple options to generate a DCP that meets placement and timing constraints. The `aws_build_dcp_from_cl.sh` provides multiple choices for implementation strategies, invoked by the `-strategy` option. For more details refer to [Build Strategies](#strategies) below or call `aws_build_dcp_from_cl.sh -help` for the list of supported capabilities.
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Advanced developers can use different scripts, tools, and techniques (e.g., regioning), with the condition that they submit both the `manifest.txt` and "encrypted placed-and-routed design checkpoint (DCP)" in a single tar file that passes final checks.
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<a name="stepbystep"></a>
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## Build Procedure
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The following describes the step-by-step procedure to build developer CLs. Some of these steps can be modified or adjusted based on developer experience and design needs.
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A developer can execute `$HDK_SHELL_DIR/build/scripts/aws_build_dcp_from_cl.sh` to check the environment, setup the build directory, invoke Xilinx Vivado to create the encrypted placed-and-routed DCP (which include AWS Shell + Developer CL), create the [`manifest.txt`](./../../../../docs/AFI_Manifest.md) that AWS will ingest through the CreateFpgaImage EC2 API. Executing this script also entails encryption of developer-specified RTL files. Further details on invoking the script from Vivado are provided below.
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### 1) Pre-requisite: Environment Variables and Tools
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1. The environment variable `HDK_SHELL_DIR` should have been set. This is usually done by executing `source hdk_setup.sh` from the HDK root directory
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2. The environment variable `CL_DIR` should have been set pointing to the root directory where the CL exists. The CL root directory should have the `/build` and `/design` subdirectories. One way to make sure to have the right directory is to execute `source $(HDK_DIR)/cl/developer_designs/prepare_new_cl.sh`
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3. Developer have Xilinx Vivado tools installed, with the supported version by the HDK, and with proper license. If the developer is using AWS supplied [FPGA Development AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) from AWS marketplace, it includes the README.md how to setup up the tools and license.
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### 2) Encrypt Source Files
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CL Encryption is required and AFI creation will fail if your CL source files are not encrypted. As a pre-cursor to the build process, modify the `$CL_DIR/build/scripts/encrypt.tcl` script to include all the CL source files, so the script can encrypt and copy them to the `$CL_DIR/build/src_post_encryption` directory.
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### 3) Prepare for the CL Build
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Modify the `$CL_DIR/build/scripts/create_dcp_from_cl.tcl` script to include:
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1. The list of CL encrypted files in `$CL_DIR/build/src_post_encryption`.
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2. The list of CL specific timing and placement constraints in `$CL_DIR/build/constraints`.
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3. The specific constraints and design file for IP any included in your CL (e.g., DDR4).
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### 4) Build
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Run the build script, aws_build_dcp_from_cl.sh, from the `$CL_DIR/build/scripts` directory.
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The build script performs:
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- Synthesis of CL.
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- Implementation of CL with AWS Shell.
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- Generation of Design Checkpoint (DCP) for AWS ingestion with the associated logs.
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- Generation of the corresponding manifest.txt.
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<a name="strategies"></a>
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#### Build Strategies
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In order to help developers close timing goals and successfully build their designs efficiently, the build script provides the means to synthesize with different strategies. The different strategies alter the directives used by the synthesis tool. For example, some directives might specify additional optimizations to close timing, while others may specify less effort to minimize synthesis time for designs that can more easily close timing and area goals. Since every design is different, some strategies may provide better results than another build strategies. If a developer has trouble successfully building their design with one strategy it is encouraged that they try a different strategy, or run a few strategies in parallel using the FPGA Developer AMI. The strategies are described in more detail below.
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Build script usage:
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$ ./aws_build_dcp_from_cl.sh [ [-script <vivado_script>] | [-strategy BASIC | DEFAULT | EXPLORE | TIMING | CONGESTION] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1 | B2 | B3 | B4 | B5] [-clock_recipe_c C0 | C1 | C2 | C3] [-uram_option 2 | 3 | 4] [-foreground] [-notify] | [-h] | [-H] | [-help] ]
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Options:
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* -script \<vivado_script>
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* Use the specified vivado script. The default script create_dcp_from_cl.tcl will be used if a script is not specified.
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* -h, -H, -help
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* Print a usage message.
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* -strategy \<BASIC | EXPLORE | TIMING | CONGESTION | DEFAULT>
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* Use the specified strategy to alter the directives used during synthesis. The DEFAULT strategy will be used if a strategy is not specified.
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* -clock_recipe_a \<A0 ... An>
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* Use the Clock Group A clock frequencies defined for the specified Clock Group A recipe. This is an optional argument and the default value will be A0. Refer to the [Clock Group Recipes Table](./../../../../docs/clock_recipes.csv).
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* -clock_recipe_b \<B0 ... Bn>
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* Use the Clock Group B clock frequencies defined for the specified Clock Group B recipe. This is an optional argument and the default value will be B0. Refer to the [Clock Group Recipes Table](./../../../../docs/clock_recipes.csv).
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* -clock_recipe_c \<C0 ... Cn>
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* Use the Clock Group C clock frequencies defined for the specified Clock Group C recipe. This is an optional argument and the default value will be C0. Refer to the [Clock Group Recipes Table](./../../../../docs/clock_recipes.csv).
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* -uram_option \<2 | 3 | 4>
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* Use the specified URAM option to define the percentage of URAM sites used for the design. A value of 2 indicates 50%, a value of 3 indicates 75%, and a value of 4 indicates 100%. This is an optional argument and the default value will be 2.
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* -foreground
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* Run the build in the foreground such that all output will go to the terminal and the build may be terminated if the terminal is closed. This option is useful if you want to wait for the build to complete. This option is safe if the terminal is running on the AWS instance, for example on a GUI desktop on the instance.
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* -notify
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* Send e-mail to notify user once the build is complete. Requires setup described in `$HDK_DIR/README.md`.
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Strategy descriptions:
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* BASIC
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* This is the basic flow in Vivado and contains the mandatory steps to be able to build a design. It is designed to provide a good balance between runtime and Quality of Results (QOR).
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* EXPLORE
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* This is a high-effort flow which is designed to give improved QOR results at the expense of runtime.
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* TIMING
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* This flow is designed for more aggressive timing optimization at the expense of runtime and congestion.
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* CONGESTION
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* This flow is designed to insert more aggressive whitespace to alleviate routing congestion.
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* DEFAULT
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* This is an additional high-effort flow that results in improved QOR results for the example design at the expense of runtime.
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In addition, in order to aid developers with build verification, there is a final step in the build script that emulates the process that AWS uses to generate bitstreams from a developer DCP.
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The outputs of the build script are:
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- `$CL_DIR/build/checkpoints/*`: Various checkpoints generated during the build process.
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- `$CL_DIR/build/to_aws/SH_CL_routed.dcp`: Encrypted placed-and-routed design checkpoint for AWS ingestion.
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- `$CL_DIR/build/reports/*`: Various build reports (generally, check_timing/report_timing).
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- `$CL_DIR/build/src_post_encryption/*`: Encrypted developer source.
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- `$CL_DIR/build/constraints/*`: Implementation constraints.
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A developer may need to iterate multiple times through this process until arriving upon an error-free run.
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### 5) Submit the final tar file to AWS to register the AFI
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To submit the DCP, create an S3 bucket for submitting the design and upload the tarball file into that bucket.
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You need to prepare the following information:
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1. Name of the logic design *(Optional)*.
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2. Generic description of the logic design *(Optional)*.
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3. PCI IDs: Device, Vendor, Subsystem, SubsystemVendor.
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4. Location of the tarball file object in S3.
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5. Location of an S3 directory where AWS would write back logs of the AFI creation.
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6. Version of the AWS Shell.
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**NOTE**: *The PCI IDs for the example CLs should be found in the README files in the respective CL example directory.
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If you are building a custom CL, then you need to incorporate these values in your design as shown in the [AWS Shell Interface Specifications](./../../../../docs/AWS_Shell_Interface_Specification.md#misc).*
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[Refer to step 3 for instructions on how to submit the Design Checkpoint to AWS](./../../../../README.md)
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<a name="buildstratgies"></a>
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## Build Strategies and Parallel Builds
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Developers may face challenges fitting the CL design into the FPGA due to routing congestion, placement congestion, or not being able to meet timing. These are typical challenges in FPGA and chip development.
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AWS script `./aws_build_dcp_from_cl.sh` offers an optional flag to set one of a few useful implementation strategies, which would automatically different directives to various build steps. You can learn about the various strategy options by running `$ ./aws_build_dcp_from_cl.sh -help`.
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If you are running on one of the EC2 compute instances with 31GiB DRAM or more, you could run multiple builds concurrently for the same CL, but calling the build script multiple times with different `-strategy` options, taking advantage of the large vCPU count typically available on EC2 instances, as each build would typically consume between 1 to 8 vCPUs throughout the entire run of a given build.
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<a name="buildencryption"></a>
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## About Encryption
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Developer RTL is encrypted using IEEE 1735 V2 encryption. This level of encryption protects both the raw source files and the implemented design.
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<a name="buildadvanced_notes"></a>
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## Advanced Notes
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* The included implementation flow is a baseline flow. It is possible to add advanced commands/constraints (e.g, rejoining) to the flow.
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* Developers are free to modify the flow, but the final output must be a tar file with manifest.txt and the combined (AWS Shell + CL), encrypted, placed-and-routed design checkpoint,.
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<a name="buildfaq"></a>
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# Frequently Asked Questions
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**Q: What are the different files that a developer needs to provide to AWS?**
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The developer should submit a tar file that contains the placed-and-routed DCP along with the required manifest.txt file.
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**Q: What should I do my design is not meeting timing?**
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The developer should evaluate the timing path to identify a solution that may include design changes or additional constraints. Additionally, the developer can try using one of the different build strategies that may help resolve the timing violations.
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**Q: My design was meeting timing, but even without changes, subsequent builds are not meeting timing?**
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This may happen due to various reasons. The developer should investigate the timing violation regardless of the lack of design changes. Additionally, the developer can try using one of the different build strategies that may help resolve the timing violations.
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**Q: "pr_verify" is complaining that the design checkpoints are incompatible. What should I do?**
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The developer can double-check that the AWS Shell DCP, SH_CL_BB_routed.dcp, was downloaded properly from the S3 bucket to the `hdk/common/shell_stable/build/checkpoints/from_aws` directory during the [hdk_setup.sh](../../../../../hdk_setup.sh) step and that there aren't errors in the build log.
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**Q: What version of Vivado do I need to use?**
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The valid version of Vivado is verified during the [hdk_setup.sh](../../../../../hdk_setup.sh) step.
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# This contains the CL specific constraints for Top level PNR
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# False path between vled on CL clock and Shell asynchronous clock
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set_false_path -from [get_cells WRAPPER_INST/CL/vled_q_reg*]
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# False paths between main clock and tck
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set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins WRAPPER_INST/SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
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set_clock_groups -name TIG_SRAI_2 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
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set_clock_groups -name TIG_SRAI_3 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
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# This contains the CL specific constraints for synthesis at the CL level
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#!/bin/bash
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# Amazon FPGA Hardware Development Kit
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#
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# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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#
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# Licensed under the Amazon Software License (the "License"). You may not use
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# this file except in compliance with the License. A copy of the License is
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# located at
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#
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# http://aws.amazon.com/asl/
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#
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# or in the "license" file accompanying this file. This file is distributed on
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# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
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# implied. See the License for the specific language governing permissions and
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# limitations under the License.
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# Usage help
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function usage
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{
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echo "usage: aws_build_dcp_from_cl.sh [ [-script <vivado_script>] | [-strategy BASIC | DEFAULT | EXPLORE | TIMING | CONGESTION] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1 | B2 | B3 | B4 | B5] [-clock_recipe_c C0 | C1 | C2 | C3] [-uram_option 2 | 3 | 4] [-vdefine macro1,macro2,macro3,.....,macrox] -foreground] [-notify] | [-h] | [-H] | [-help] ]"
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echo " "
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echo "By default the build is run in the background using nohup so that the"
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echo "process will not be terminated if the terminal window is closed."
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echo "The window can be closed if it is running on your computer and the"
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echo "network connection is lost. All build output will be redirected to a"
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echo "log file called *.nohup.out."
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echo " "
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echo "The -foreground option runs the build in the foreground. All output will"
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echo "go to the terminal and the build may be terminated if the terminal"
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echo "is closed. This option is useful if you want to wait for the build"
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echo "to complete. This option is safe if the terminal is running on the"
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echo "AWS instance, for example on a GUI desktop on the instance."
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}
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# Default arguments for script and strategy
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strategy=DEFAULT
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clock_recipe_a=A0
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clock_recipe_b=B0
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clock_recipe_c=C0
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vivado_script="create_dcp_from_cl.tcl"
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foreground=0
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notify=0
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ignore_memory_requirement=0
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expected_memory_usage=30000000
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uram_option=2
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vdefine=""
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function info_msg {
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echo -e "INFO: $1"
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}
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function debug_msg {
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||||
if [[ $debug == 0 ]]; then
|
||||
return
|
||||
fi
|
||||
echo -e "DEBUG: $1"
|
||||
}
|
||||
|
||||
function warn_msg {
|
||||
echo -e "WARNING: $1"
|
||||
}
|
||||
|
||||
function err_msg {
|
||||
echo -e >&2 "ERROR: $1"
|
||||
}
|
||||
|
||||
function get_instance_memory {
|
||||
local mem=$(awk -F"[: ]+" '/MemTotal/ {print $2;exit}' /proc/meminfo)
|
||||
echo "$mem"
|
||||
}
|
||||
|
||||
# Parse command-line arguments
|
||||
while [ "$1" != "" ]; do
|
||||
case $1 in
|
||||
-script ) shift
|
||||
vivado_script=$1
|
||||
;;
|
||||
-strategy ) shift
|
||||
strategy=$1
|
||||
;;
|
||||
-clock_recipe_a ) shift
|
||||
clock_recipe_a=$1
|
||||
;;
|
||||
-clock_recipe_b ) shift
|
||||
clock_recipe_b=$1
|
||||
;;
|
||||
-clock_recipe_c ) shift
|
||||
clock_recipe_c=$1
|
||||
;;
|
||||
-uram_option ) shift
|
||||
uram_option=$1
|
||||
;;
|
||||
-vdefine ) shift
|
||||
vdefine=$1
|
||||
;;
|
||||
-foreground ) foreground=1
|
||||
;;
|
||||
-notify ) notify=1
|
||||
;;
|
||||
-ignore_memory_requirement) ignore_memory_requirement=1
|
||||
;;
|
||||
-h | -H | -help ) usage
|
||||
exit
|
||||
;;
|
||||
* ) usage
|
||||
exit 1
|
||||
esac
|
||||
shift
|
||||
done
|
||||
|
||||
# Check that script exists
|
||||
if ! [ -f "$vivado_script" ]; then
|
||||
err_msg "$vivado_script doesn't exist."
|
||||
exit 1
|
||||
fi
|
||||
|
||||
# Check that strategy is valid
|
||||
shopt -s extglob
|
||||
if [[ $strategy != @(BASIC|DEFAULT|EXPLORE|TIMING|CONGESTION) ]]; then
|
||||
err_msg "$strategy isn't a valid strategy. Valid strategies are BASIC, DEFAULT, EXPLORE, TIMING and CONGESTION."
|
||||
exit 1
|
||||
fi
|
||||
|
||||
# Check that clock_recipe_a is valid
|
||||
shopt -s extglob
|
||||
if [[ $clock_recipe_a != @(A0|A1|A2) ]]; then
|
||||
err_msg "$clock_recipe_a isn't a valid Clock Group A recipe. Valid Clock Group A recipes are A0, A1, and A2."
|
||||
exit 1
|
||||
fi
|
||||
|
||||
# Check that clock_recipe_b is valid
|
||||
shopt -s extglob
|
||||
if [[ $clock_recipe_b != @(B0|B1|B2|B3|B4|B5) ]]; then
|
||||
err_msg "$clock_recipe_b isn't a valid Clock Group B recipe. Valid Clock Group B recipes are B0, B1, B2, B3, B4, and B5."
|
||||
exit 1
|
||||
fi
|
||||
|
||||
# Check that clock_recipe_c is valid
|
||||
shopt -s extglob
|
||||
if [[ $clock_recipe_c != @(C0|C1|C2|C3) ]]; then
|
||||
err_msg "$clock_recipe_c isn't a valid Clock Group C recipe. Valid Clock Group C recipes are C0, C1, C2, and C3."
|
||||
exit 1
|
||||
fi
|
||||
|
||||
# Check that uram_option is valid
|
||||
shopt -s extglob
|
||||
if [[ $uram_option != @(2|3|4) ]]; then
|
||||
err_msg "$uram_option isn't a valid URAM option. Valid URAM options are 2 (50%), 3 (75%), and 4 (100%)."
|
||||
exit 1
|
||||
fi
|
||||
# process vdefines
|
||||
info_msg "VDEFINE is : $vdefine"
|
||||
shopt -s extglob
|
||||
IFS=',' read -r -a vdefine_array <<< "$vdefine"
|
||||
|
||||
opt_vdefine=""
|
||||
|
||||
for index in "${!vdefine_array[@]}"
|
||||
do
|
||||
echo "$index ${vdefine_array[index]}"
|
||||
opt_vdefine+=" -verilog_define "
|
||||
opt_vdefine+=${vdefine_array[index]}
|
||||
done
|
||||
echo "$opt_vdefine"
|
||||
if [ $expected_memory_usage -gt `get_instance_memory` ]; then
|
||||
|
||||
output_message="YOUR INSTANCE has less memory than is necessary for certain builds. This means that your builds will take longer than expected. \nTo change to an instance type with more memory, please check our instance resize guide: http://docs.aws.amazon.com/AWSEC2/latest/UserGuide/ec2-instance-resize.html"
|
||||
|
||||
if [[ $ignore_memory_requirement == 0 ]]; then
|
||||
err_msg "$output_message"
|
||||
err_msg "To ignore this memory requirement, run this script again with -ignore_memory_requirement as an argument."
|
||||
exit 1
|
||||
else
|
||||
warn_msg "$output_message"
|
||||
fi
|
||||
fi
|
||||
|
||||
info_msg "Starting the design checkpoint build process"
|
||||
info_msg "Checking for proper environment variables and build directories"
|
||||
|
||||
if ! [ $HDK_SHELL_DIR ]
|
||||
then
|
||||
err_msg "HDK_SHELL_DIR environment variable is not set, try running hdk_setup.sh script from the root directory of AWS FPGA repository."
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if ! [ $CL_DIR ]
|
||||
then
|
||||
err_msg "CL_DIR environment variable is not set. Set CL_DIR to a valid directory."
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if ! [ $HDK_DIR ]
|
||||
then
|
||||
err_msg "HDK_DIR environment variable is not set, try running hdk_setup.sh script from the root directory of AWS FPGA repository."
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if ! [ -x $HDK_SHELL_DIR/build/scripts/prepare_build_environment.sh ]
|
||||
then
|
||||
info_msg "prepare_build_env.sh script is not eXecutable, trying to apply chmod +x"
|
||||
chmod +x $HDK_SHELL_DIR/build/scripts/prepare_build_environment.sh
|
||||
if ! [ -x $HDK_SHELL_DIR/build/scripts/prepare_build_environment.sh ]
|
||||
then
|
||||
err_msg "Failed to change prepare_build_environment.sh to eXecutable, aborting!"
|
||||
exit 1
|
||||
fi
|
||||
fi
|
||||
|
||||
$HDK_SHELL_DIR/build/scripts/prepare_build_environment.sh
|
||||
|
||||
if ! [[ $? -eq 0 ]]
|
||||
then
|
||||
err_msg "Missing environment variable or unable to create the needed build directories, aborting!"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
# Use timestamp for logs and output files
|
||||
timestamp=$(date +"%y_%m_%d-%H%M%S")
|
||||
logname=$timestamp.vivado.log
|
||||
ln -s -f $logname last_log
|
||||
|
||||
info_msg "Environment variables and directories are present. Checking for Vivado installation."
|
||||
|
||||
# Before going too far make sure Vivado is available
|
||||
vivado -version >/dev/null 2>&1 || { err_msg "Please install/enable Vivado." ; return 1; }
|
||||
|
||||
# Get the HDK Version
|
||||
hdk_version=$(grep 'HDK_VERSION' $HDK_DIR/hdk_version.txt | sed 's/=/ /g' | awk '{print $2}')
|
||||
|
||||
# Get the Shell Version
|
||||
shell_version=$(grep 'SHELL_VERSION' $HDK_SHELL_DIR/shell_version.txt | sed 's/=/ /g' | awk '{print $2}')
|
||||
|
||||
# Get the PCIe Device & Vendor ID from ID0
|
||||
id0_version=$(grep 'CL_SH_ID0' $CL_DIR/design/cl_id_defines.vh | grep 'define' | sed 's/_//g' | awk -F "h" '{print $2}')
|
||||
device_id="0x${id0_version:0:4}";
|
||||
vendor_id="0x${id0_version:4:4}";
|
||||
|
||||
# Get the PCIe Subsystem & Subsystem Vendor ID from ID1
|
||||
id1_version=$(grep 'CL_SH_ID1' $CL_DIR/design/cl_id_defines.vh | grep 'define' | sed 's/_//g' | awk -F "h" '{print $2}')
|
||||
subsystem_id="0x${id1_version:0:4}";
|
||||
subsystem_vendor_id="0x${id1_version:4:4}";
|
||||
|
||||
# Run vivado
|
||||
cmd="vivado -mode batch -nojournal -log $logname -source $vivado_script -tclargs $timestamp $strategy $hdk_version $shell_version $device_id $vendor_id $subsystem_id $subsystem_vendor_id $clock_recipe_a $clock_recipe_b $clock_recipe_c $uram_option $notify $opt_vdefine"
|
||||
if [[ "$foreground" == "0" ]]; then
|
||||
nohup $cmd > $timestamp.nohup.out 2>&1 &
|
||||
|
||||
info_msg "Build through Vivado is running as background process, this may take few hours."
|
||||
info_msg "Output is being redirected to $timestamp.nohup.out"
|
||||
info_msg "If you have set your EMAIL environment variable and -notify is specified, you will receive a notification when complete."
|
||||
info_msg " (See \$HDK_DIR/cl/examples/README.md for details)"
|
||||
else
|
||||
info_msg "Build through Vivado is running in the foreground, this may take a few hours."
|
||||
info_msg "The build may be terminated if the network connection to this terminal window is lost."
|
||||
$cmd
|
||||
fi
|
||||
|
|
@ -0,0 +1,369 @@
|
|||
# Amazon FPGA Hardware Development Kit
|
||||
#
|
||||
# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
#
|
||||
# Licensed under the Amazon Software License (the "License"). You may not use
|
||||
# this file except in compliance with the License. A copy of the License is
|
||||
# located at
|
||||
#
|
||||
# http://aws.amazon.com/asl/
|
||||
#
|
||||
# or in the "license" file accompanying this file. This file is distributed on
|
||||
# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
# implied. See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
package require tar
|
||||
|
||||
## Do not edit $TOP
|
||||
set TOP top_sp
|
||||
|
||||
## Replace with the name of your module
|
||||
set CL_MODULE cl_hello_world
|
||||
|
||||
#################################################
|
||||
## Command-line Arguments
|
||||
#################################################
|
||||
set timestamp [lindex $argv 0]
|
||||
set strategy [lindex $argv 1]
|
||||
set hdk_version [lindex $argv 2]
|
||||
set shell_version [lindex $argv 3]
|
||||
set device_id [lindex $argv 4]
|
||||
set vendor_id [lindex $argv 5]
|
||||
set subsystem_id [lindex $argv 6]
|
||||
set subsystem_vendor_id [lindex $argv 7]
|
||||
set clock_recipe_a [lindex $argv 8]
|
||||
set clock_recipe_b [lindex $argv 9]
|
||||
set clock_recipe_c [lindex $argv 10]
|
||||
set uram_option [lindex $argv 11]
|
||||
set notify_via_sns [lindex $argv 12]
|
||||
set VDEFINES [lindex $argv 13]
|
||||
##################################################
|
||||
## Flow control variables
|
||||
##################################################
|
||||
set cl.synth 1
|
||||
set implement 1
|
||||
|
||||
#################################################
|
||||
## Generate CL_routed.dcp (Done by User)
|
||||
#################################################
|
||||
puts "AWS FPGA Scripts";
|
||||
puts "Creating Design Checkpoint from Custom Logic source code";
|
||||
puts "HDK Version: $hdk_version";
|
||||
puts "Shell Version: $shell_version";
|
||||
puts "Vivado Script Name: $argv0";
|
||||
puts "Strategy: $strategy";
|
||||
puts "PCI Device ID $device_id";
|
||||
puts "PCI Vendor ID $vendor_id";
|
||||
puts "PCI Subsystem ID $subsystem_id";
|
||||
puts "PCI Subsystem Vendor ID $subsystem_vendor_id";
|
||||
puts "Clock Recipe A: $clock_recipe_a";
|
||||
puts "Clock Recipe B: $clock_recipe_b";
|
||||
puts "Clock Recipe C: $clock_recipe_c";
|
||||
puts "URAM option: $uram_option";
|
||||
puts "Notify when done: $notify_via_sns";
|
||||
|
||||
#checking if CL_DIR env variable exists
|
||||
if { [info exists ::env(CL_DIR)] } {
|
||||
set CL_DIR $::env(CL_DIR)
|
||||
puts "Using CL directory $CL_DIR";
|
||||
} else {
|
||||
puts "Error: CL_DIR environment variable not defined ! ";
|
||||
puts "Use export CL_DIR=Your_Design_Root_Directory"
|
||||
exit 2
|
||||
}
|
||||
|
||||
#checking if HDK_SHELL_DIR env variable exists
|
||||
if { [info exists ::env(HDK_SHELL_DIR)] } {
|
||||
set HDK_SHELL_DIR $::env(HDK_SHELL_DIR)
|
||||
puts "Using Shell directory $HDK_SHELL_DIR";
|
||||
} else {
|
||||
puts "Error: HDK_SHELL_DIR environment variable not defined ! ";
|
||||
puts "Run the hdk_setup.sh script from the root directory of aws-fpga";
|
||||
exit 2
|
||||
}
|
||||
|
||||
#checking if HDK_SHELL_DESIGN_DIR env variable exists
|
||||
if { [info exists ::env(HDK_SHELL_DESIGN_DIR)] } {
|
||||
set HDK_SHELL_DESIGN_DIR $::env(HDK_SHELL_DESIGN_DIR)
|
||||
puts "Using Shell design directory $HDK_SHELL_DESIGN_DIR";
|
||||
} else {
|
||||
puts "Error: HDK_SHELL_DESIGN_DIR environment variable not defined ! ";
|
||||
puts "Run the hdk_setup.sh script from the root directory of aws-fpga";
|
||||
exit 2
|
||||
}
|
||||
|
||||
##################################################
|
||||
### Output Directories used by step_user.tcl
|
||||
##################################################
|
||||
set implDir $CL_DIR/build/checkpoints
|
||||
set rptDir $CL_DIR/build/reports
|
||||
set cacheDir $HDK_SHELL_DESIGN_DIR/cache/ddr4_phy
|
||||
|
||||
puts "All reports and intermediate results will be time stamped with $timestamp";
|
||||
|
||||
set_msg_config -id {Chipscope 16-3} -suppress
|
||||
set_msg_config -string {AXI_QUAD_SPI} -suppress
|
||||
|
||||
# Suppress Warnings
|
||||
# These are to avoid warning messages that may not be real issues. A developer
|
||||
# may comment them out if they wish to see more information from warning
|
||||
# messages.
|
||||
set_msg_config -id {Common 17-55} -suppress
|
||||
set_msg_config -id {Vivado 12-4739} -suppress
|
||||
set_msg_config -id {Constraints 18-4866} -suppress
|
||||
set_msg_config -id {IP_Flow 19-2162} -suppress
|
||||
set_msg_config -id {Route 35-328} -suppress
|
||||
set_msg_config -id {Vivado 12-1008} -suppress
|
||||
set_msg_config -id {Vivado 12-508} -suppress
|
||||
set_msg_config -id {filemgmt 56-12} -suppress
|
||||
set_msg_config -id {DRC CKLD-1} -suppress
|
||||
set_msg_config -id {DRC CKLD-2} -suppress
|
||||
set_msg_config -id {IP_Flow 19-2248} -suppress
|
||||
set_msg_config -id {Vivado 12-1580} -suppress
|
||||
set_msg_config -id {Constraints 18-550} -suppress
|
||||
set_msg_config -id {Synth 8-3295} -suppress
|
||||
set_msg_config -id {Synth 8-3321} -suppress
|
||||
set_msg_config -id {Synth 8-3331} -suppress
|
||||
set_msg_config -id {Synth 8-3332} -suppress
|
||||
set_msg_config -id {Synth 8-6014} -suppress
|
||||
set_msg_config -id {Timing 38-436} -suppress
|
||||
set_msg_config -id {DRC REQP-1853} -suppress
|
||||
set_msg_config -id {Synth 8-350} -suppress
|
||||
set_msg_config -id {Synth 8-3848} -suppress
|
||||
set_msg_config -id {Synth 8-3917} -suppress
|
||||
set_msg_config -id {Opt 31-430} -suppress
|
||||
|
||||
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling the encrypt.tcl.";
|
||||
|
||||
# Check that an email address has been set, else unset notify_via_sns
|
||||
|
||||
if {[string compare $notify_via_sns "1"] == 0} {
|
||||
if {![info exists env(EMAIL)]} {
|
||||
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) EMAIL variable empty! Completition notification will *not* be sent!";
|
||||
set notify_via_sns 0;
|
||||
} else {
|
||||
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) EMAIL address for completion notification set to $env(EMAIL).";
|
||||
}
|
||||
}
|
||||
|
||||
##################################################
|
||||
### Strategy options
|
||||
##################################################
|
||||
switch $strategy {
|
||||
"BASIC" {
|
||||
puts "BASIC strategy."
|
||||
source $HDK_SHELL_DIR/build/scripts/strategy_BASIC.tcl
|
||||
}
|
||||
"EXPLORE" {
|
||||
puts "EXPLORE strategy."
|
||||
source $HDK_SHELL_DIR/build/scripts/strategy_EXPLORE.tcl
|
||||
}
|
||||
"TIMING" {
|
||||
puts "TIMING strategy."
|
||||
source $HDK_SHELL_DIR/build/scripts/strategy_TIMING.tcl
|
||||
}
|
||||
"CONGESTION" {
|
||||
puts "CONGESTION strategy."
|
||||
source $HDK_SHELL_DIR/build/scripts/strategy_CONGESTION.tcl
|
||||
}
|
||||
"DEFAULT" {
|
||||
puts "DEFAULT strategy."
|
||||
source $HDK_SHELL_DIR/build/scripts/strategy_DEFAULT.tcl
|
||||
}
|
||||
default {
|
||||
puts "$strategy is NOT a valid strategy. Defaulting to strategy DEFAULT."
|
||||
source $HDK_SHELL_DIR/build/scripts/strategy_DEFAULT.tcl
|
||||
}
|
||||
}
|
||||
|
||||
#Encrypt source code
|
||||
source encrypt.tcl
|
||||
|
||||
#Set the Device Type
|
||||
source $HDK_SHELL_DIR/build/scripts/device_type.tcl
|
||||
|
||||
#Procedure for running various implementation steps (impl_step)
|
||||
source $HDK_SHELL_DIR/build/scripts/step_user.tcl -notrace
|
||||
|
||||
########################################
|
||||
## Generate clocks based on Recipe
|
||||
########################################
|
||||
|
||||
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
|
||||
|
||||
source $HDK_SHELL_DIR/build/scripts/aws_gen_clk_constraints.tcl
|
||||
#################################################################
|
||||
#### Do not remove this setting. Need to workaround bug
|
||||
##################################################################
|
||||
set_param hd.clockRoutingWireReduction false
|
||||
##################################################
|
||||
### CL XPR OOC Synthesis
|
||||
##################################################
|
||||
if {${cl.synth}} {
|
||||
source -notrace ./synth_${CL_MODULE}.tcl
|
||||
set synth_dcp ${timestamp}.CL.post_synth.dcp
|
||||
}
|
||||
|
||||
##################################################
|
||||
### Implementation
|
||||
##################################################
|
||||
if {$implement} {
|
||||
|
||||
########################
|
||||
# Link Design
|
||||
########################
|
||||
if {$link} {
|
||||
####Create in-memory prjoect and setup IP cache location
|
||||
create_project -part [DEVICE_TYPE] -in_memory
|
||||
set_property IP_REPO_PATHS $cacheDir [current_project]
|
||||
puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Combining Shell and CL design checkpoints";
|
||||
add_files $HDK_SHELL_DIR/build/checkpoints/from_aws/SH_CL_BB_routed.dcp
|
||||
add_files $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp
|
||||
set_property SCOPED_TO_CELLS {WRAPPER_INST/CL} [get_files $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp]
|
||||
|
||||
#Read the constraints, note *DO NOT* read cl_clocks_aws (clocks originating from AWS shell)
|
||||
read_xdc [ list \
|
||||
$CL_DIR/build/constraints/cl_pnr_user.xdc
|
||||
]
|
||||
set_property PROCESSING_ORDER late [get_files cl_pnr_user.xdc]
|
||||
|
||||
puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running link_design";
|
||||
link_design -top $TOP -part [DEVICE_TYPE] -reconfig_partitions {WRAPPER_INST/SH WRAPPER_INST/CL}
|
||||
|
||||
puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - PLATFORM.IMPL==[get_property PLATFORM.IMPL [current_design]]";
|
||||
##################################################
|
||||
# Apply Clock Properties for Clock Table Recipes
|
||||
##################################################
|
||||
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Sourcing aws_clock_properties.tcl to apply properties to clocks. ";
|
||||
|
||||
# Apply properties to clocks
|
||||
source $HDK_SHELL_DIR/build/scripts/aws_clock_properties.tcl
|
||||
|
||||
# Write post-link checkpoint
|
||||
puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Writing post-link_design checkpoint ${timestamp}.post_link.dcp";
|
||||
write_checkpoint -force $CL_DIR/build/checkpoints/${timestamp}.post_link.dcp
|
||||
}
|
||||
|
||||
########################
|
||||
# CL Optimize
|
||||
########################
|
||||
set place_preHookTcl ""
|
||||
if {$opt} {
|
||||
puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running optimization";
|
||||
impl_step opt_design $TOP $opt_options $opt_directive $opt_preHookTcl $opt_postHookTcl
|
||||
if {$psip} {
|
||||
impl_step opt_design $TOP "-merge_equivalent_drivers -sweep"
|
||||
}
|
||||
}
|
||||
|
||||
########################
|
||||
# CL Place
|
||||
########################
|
||||
if {$place} {
|
||||
puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running placement";
|
||||
if {$psip} {
|
||||
append place_options " -fanout_opt"
|
||||
}
|
||||
impl_step place_design $TOP $place_options $place_directive $place_preHookTcl $place_postHookTcl
|
||||
}
|
||||
|
||||
##############################
|
||||
# CL Post-Place Optimization
|
||||
##############################
|
||||
if {$phys_opt} {
|
||||
puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running post-place optimization";
|
||||
impl_step phys_opt_design $TOP $phys_options $phys_directive $phys_preHookTcl $phys_postHookTcl
|
||||
}
|
||||
|
||||
########################
|
||||
# CL Route
|
||||
########################
|
||||
if {$route} {
|
||||
puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Routing design";
|
||||
impl_step route_design $TOP $route_options $route_directive $route_preHookTcl $route_postHookTcl
|
||||
}
|
||||
|
||||
##############################
|
||||
# CL Post-Route Optimization
|
||||
##############################
|
||||
set SLACK [get_property SLACK [get_timing_paths]]
|
||||
#Post-route phys_opt will not be run if slack is positive or greater than -200ps.
|
||||
if {$route_phys_opt && $SLACK > -0.400 && $SLACK < 0} {
|
||||
puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running post-route optimization";
|
||||
impl_step route_phys_opt_design $TOP $post_phys_options $post_phys_directive $post_phys_preHookTcl $post_phys_postHookTcl
|
||||
}
|
||||
|
||||
##############################
|
||||
# Final Implmentation Steps
|
||||
##############################
|
||||
# Report final timing
|
||||
report_timing_summary -file $CL_DIR/build/reports/${timestamp}.SH_CL_final_timing_summary.rpt
|
||||
|
||||
# This is what will deliver to AWS
|
||||
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Writing final DCP to to_aws directory.";
|
||||
|
||||
#writing unencrypted dcp for analysis to checkpoints dir.
|
||||
write_checkpoint -force $CL_DIR/build/checkpoints/${timestamp}.SH_CL_routed.dcp
|
||||
|
||||
#writing encrypted dcp which can be sent to AWS
|
||||
write_checkpoint -encrypt -force $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed.dcp
|
||||
|
||||
# Generate debug probes file
|
||||
write_debug_probes -force -no_partial_ltxfile -file $CL_DIR/build/checkpoints/${timestamp}.debug_probes.ltx
|
||||
|
||||
close_project
|
||||
}
|
||||
|
||||
# ################################################
|
||||
# Create Manifest and Tarball for delivery
|
||||
# ################################################
|
||||
|
||||
# Create a zipped tar file, that would be used for createFpgaImage EC2 API
|
||||
|
||||
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Compress files for sending to AWS. "
|
||||
|
||||
# Create manifest file
|
||||
set manifest_file [open "$CL_DIR/build/checkpoints/to_aws/${timestamp}.manifest.txt" w]
|
||||
set hash [lindex [split [exec sha256sum $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed.dcp] ] 0]
|
||||
set TOOL_VERSION $::env(VIVADO_TOOL_VERSION)
|
||||
set vivado_version [string range [version -short] 0 5]
|
||||
puts "vivado_version is $vivado_version\n"
|
||||
|
||||
puts $manifest_file "manifest_format_version=2\n"
|
||||
puts $manifest_file "pci_vendor_id=$vendor_id\n"
|
||||
puts $manifest_file "pci_device_id=$device_id\n"
|
||||
puts $manifest_file "pci_subsystem_id=$subsystem_id\n"
|
||||
puts $manifest_file "pci_subsystem_vendor_id=$subsystem_vendor_id\n"
|
||||
puts $manifest_file "dcp_hash=$hash\n"
|
||||
puts $manifest_file "shell_version=$shell_version\n"
|
||||
puts $manifest_file "dcp_file_name=${timestamp}.SH_CL_routed.dcp\n"
|
||||
puts $manifest_file "hdk_version=$hdk_version\n"
|
||||
puts $manifest_file "tool_version=v$vivado_version\n"
|
||||
puts $manifest_file "date=$timestamp\n"
|
||||
puts $manifest_file "clock_recipe_a=$clock_recipe_a\n"
|
||||
puts $manifest_file "clock_recipe_b=$clock_recipe_b\n"
|
||||
puts $manifest_file "clock_recipe_c=$clock_recipe_c\n"
|
||||
|
||||
close $manifest_file
|
||||
|
||||
# Delete old tar file with same name
|
||||
if { [file exists $CL_DIR/build/checkpoints/to_aws/${timestamp}.Developer_CL.tar] } {
|
||||
puts "Deleting old tar file with same name.";
|
||||
file delete -force $CL_DIR/build/checkpoints/to_aws/${timestamp}.Developer_CL.tar
|
||||
}
|
||||
|
||||
# Tar checkpoint to aws
|
||||
cd $CL_DIR/build/checkpoints
|
||||
tar::create to_aws/${timestamp}.Developer_CL.tar [glob to_aws/${timestamp}*]
|
||||
|
||||
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Finished creating final tar file in to_aws directory.";
|
||||
|
||||
if {[string compare $notify_via_sns "1"] == 0} {
|
||||
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Calling notification script to send e-mail to $env(EMAIL)";
|
||||
exec $env(AWS_FPGA_REPO_DIR)/shared/bin/scripts/notify_via_sns.py
|
||||
}
|
||||
|
||||
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Build complete.";
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
# Amazon FPGA Hardware Development Kit
|
||||
#
|
||||
# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
#
|
||||
# Licensed under the Amazon Software License (the "License"). You may not use
|
||||
# this file except in compliance with the License. A copy of the License is
|
||||
# located at
|
||||
#
|
||||
# http://aws.amazon.com/asl/
|
||||
#
|
||||
# or in the "license" file accompanying this file. This file is distributed on
|
||||
# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
# implied. See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
# TODO:
|
||||
# Add check if CL_DIR and HDK_SHELL_DIR directories exist
|
||||
# Add check if /build and /build/src_port_encryption directories exist
|
||||
# Add check if the vivado_keyfile exist
|
||||
|
||||
set HDK_SHELL_DIR $::env(HDK_SHELL_DIR)
|
||||
set HDK_SHELL_DESIGN_DIR $::env(HDK_SHELL_DESIGN_DIR)
|
||||
set CL_DIR $::env(CL_DIR)
|
||||
set TARGET_DIR $CL_DIR/build/src_post_encryption
|
||||
set UNUSED_TEMPLATES_DIR $HDK_SHELL_DESIGN_DIR/interfaces
|
||||
# Remove any previously encrypted files, that may no longer be used
|
||||
if {[llength [glob -nocomplain -dir $TARGET_DIR *]] != 0} {
|
||||
eval file delete -force [glob $TARGET_DIR/*]
|
||||
}
|
||||
|
||||
#---- Developr would replace this section with design files ----
|
||||
|
||||
## Change file names and paths below to reflect your CL area. DO NOT include AWS RTL files.
|
||||
file copy -force $CL_DIR/design/cl_hello_world_defines.vh $TARGET_DIR
|
||||
file copy -force $CL_DIR/design/cl_id_defines.vh $TARGET_DIR
|
||||
file copy -force $CL_DIR/design/cl_hello_world.sv $TARGET_DIR
|
||||
file copy -force $CL_DIR/../common/design/cl_common_defines.vh $TARGET_DIR
|
||||
file copy -force $UNUSED_TEMPLATES_DIR/unused_apppf_irq_template.inc $TARGET_DIR
|
||||
file copy -force $UNUSED_TEMPLATES_DIR/unused_cl_sda_template.inc $TARGET_DIR
|
||||
file copy -force $UNUSED_TEMPLATES_DIR/unused_ddr_a_b_d_template.inc $TARGET_DIR
|
||||
file copy -force $UNUSED_TEMPLATES_DIR/unused_ddr_c_template.inc $TARGET_DIR
|
||||
file copy -force $UNUSED_TEMPLATES_DIR/unused_dma_pcis_template.inc $TARGET_DIR
|
||||
file copy -force $UNUSED_TEMPLATES_DIR/unused_pcim_template.inc $TARGET_DIR
|
||||
file copy -force $UNUSED_TEMPLATES_DIR/unused_sh_bar1_template.inc $TARGET_DIR
|
||||
file copy -force $UNUSED_TEMPLATES_DIR/unused_flr_template.inc $TARGET_DIR
|
||||
|
||||
#---- End of section replaced by Developr ---
|
||||
|
||||
# Make sure files have write permissions for the encryption
|
||||
exec chmod +w {*}[glob $TARGET_DIR/*]
|
||||
|
||||
set TOOL_VERSION $::env(VIVADO_TOOL_VERSION)
|
||||
set vivado_version [string range [version -short] 0 5]
|
||||
puts "AWS FPGA: VIVADO_TOOL_VERSION $TOOL_VERSION"
|
||||
puts "vivado_version $vivado_version"
|
||||
|
||||
# encrypt .v/.sv/.vh/inc as verilog files
|
||||
encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile_2017_4.txt -lang verilog [glob -nocomplain -- $TARGET_DIR/*.{v,sv}] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc]
|
||||
# encrypt *vhdl files
|
||||
encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_vhdl_keyfile_2017_4.txt -lang vhdl -quiet [ glob -nocomplain -- $TARGET_DIR/*.vhd? ]
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
# Amazon FPGA Hardware Development Kit
|
||||
#
|
||||
# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
#
|
||||
# Licensed under the Amazon Software License (the "License"). You may not use
|
||||
# this file except in compliance with the License. A copy of the License is
|
||||
# located at
|
||||
#
|
||||
# http://aws.amazon.com/asl/
|
||||
#
|
||||
# or in the "license" file accompanying this file. This file is distributed on
|
||||
# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
# implied. See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
#Param needed to avoid clock name collisions
|
||||
set_param sta.enableAutoGenClkNamePersistence 0
|
||||
set CL_MODULE $CL_MODULE
|
||||
set VDEFINES $VDEFINES
|
||||
|
||||
create_project -in_memory -part [DEVICE_TYPE] -force
|
||||
|
||||
########################################
|
||||
## Generate clocks based on Recipe
|
||||
########################################
|
||||
|
||||
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
|
||||
|
||||
source $HDK_SHELL_DIR/build/scripts/aws_gen_clk_constraints.tcl
|
||||
|
||||
#############################
|
||||
## Read design files
|
||||
#############################
|
||||
|
||||
#Convenience to set the root of the RTL directory
|
||||
set ENC_SRC_DIR $CL_DIR/build/src_post_encryption
|
||||
|
||||
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's Custom Logic files post encryption.";
|
||||
|
||||
#---- User would replace this section -----
|
||||
|
||||
# Reading the .sv and .v files, as proper designs would not require
|
||||
# reading .v, .vh, nor .inc files
|
||||
|
||||
read_verilog -sv [glob $ENC_SRC_DIR/*.?v]
|
||||
|
||||
#---- End of section replaced by User ----
|
||||
|
||||
puts "AWS FPGA: Reading AWS Shell design";
|
||||
|
||||
#Read AWS Design files
|
||||
read_verilog -sv [ list \
|
||||
$HDK_SHELL_DESIGN_DIR/lib/lib_pipe.sv \
|
||||
$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sync.v \
|
||||
$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/flop_ccf.sv \
|
||||
$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/ccf_ctl.v \
|
||||
$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sh_ddr.sv \
|
||||
$HDK_SHELL_DESIGN_DIR/interfaces/cl_ports.vh
|
||||
]
|
||||
|
||||
puts "AWS FPGA: Reading IP blocks";
|
||||
|
||||
#Read IP for axi register slices
|
||||
read_ip [ list \
|
||||
$HDK_SHELL_DESIGN_DIR/ip/src_register_slice/src_register_slice.xci \
|
||||
$HDK_SHELL_DESIGN_DIR/ip/dest_register_slice/dest_register_slice.xci \
|
||||
$HDK_SHELL_DESIGN_DIR/ip/axi_register_slice/axi_register_slice.xci \
|
||||
$HDK_SHELL_DESIGN_DIR/ip/axi_register_slice_light/axi_register_slice_light.xci
|
||||
]
|
||||
|
||||
#Read IP for virtual jtag / ILA/VIO
|
||||
read_ip [ list \
|
||||
$HDK_SHELL_DESIGN_DIR/ip/ila_0/ila_0.xci\
|
||||
$HDK_SHELL_DESIGN_DIR/ip/cl_debug_bridge/cl_debug_bridge.xci \
|
||||
$HDK_SHELL_DESIGN_DIR/ip/ila_vio_counter/ila_vio_counter.xci \
|
||||
$HDK_SHELL_DESIGN_DIR/ip/vio_0/vio_0.xci
|
||||
]
|
||||
|
||||
# Additional IP's that might be needed if using the DDR
|
||||
#read_bd [ list \
|
||||
# $HDK_SHELL_DESIGN_DIR/ip/ddr4_core/ddr4_core.xci \
|
||||
# $HDK_SHELL_DESIGN_DIR/ip/cl_axi_interconnect/cl_axi_interconnect.bd
|
||||
#]
|
||||
|
||||
puts "AWS FPGA: Reading AWS constraints";
|
||||
|
||||
#Read all the constraints
|
||||
#
|
||||
# cl_clocks_aws.xdc - AWS auto-generated clock constraint. ***DO NOT MODIFY***
|
||||
# cl_ddr.xdc - AWS provided DDR pin constraints. ***DO NOT MODIFY***
|
||||
# cl_synth_user.xdc - Developer synthesis constraints.
|
||||
read_xdc [ list \
|
||||
$CL_DIR/build/constraints/cl_clocks_aws.xdc \
|
||||
$HDK_SHELL_DIR/build/constraints/cl_ddr.xdc \
|
||||
$HDK_SHELL_DIR/build/constraints/cl_synth_aws.xdc \
|
||||
$CL_DIR/build/constraints/cl_synth_user.xdc
|
||||
]
|
||||
|
||||
#Do not propagate local clock constraints for clocks generated in the SH
|
||||
set_property USED_IN {synthesis implementation OUT_OF_CONTEXT} [get_files cl_clocks_aws.xdc]
|
||||
set_property PROCESSING_ORDER EARLY [get_files cl_clocks_aws.xdc]
|
||||
|
||||
########################
|
||||
# CL Synthesis
|
||||
########################
|
||||
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Start design synthesis.";
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
puts "\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\]"
|
||||
eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS $VDEFINES -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
|
||||
|
||||
set failval [catch {exec grep "FAIL" failfast.csv}]
|
||||
if { $failval==0 } {
|
||||
puts "AWS FPGA: FATAL ERROR--Resource utilization error; check failfast.csv for details"
|
||||
exit 1
|
||||
}
|
||||
|
||||
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) writing post synth checkpoint.";
|
||||
write_checkpoint -force $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp
|
||||
|
||||
close_project
|
||||
#Set param back to default value
|
||||
set_param sta.enableAutoGenClkNamePersistence 1
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
# Ignore everything in this directory
|
||||
*
|
||||
# Except this file
|
||||
!.gitignore
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,33 @@
|
|||
// Amazon FPGA Hardware Development Kit
|
||||
//
|
||||
// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
//
|
||||
// Licensed under the Amazon Software License (the "License"). You may not use
|
||||
// this file except in compliance with the License. A copy of the License is
|
||||
// located at
|
||||
//
|
||||
// http://aws.amazon.com/asl/
|
||||
//
|
||||
// or in the "license" file accompanying this file. This file is distributed on
|
||||
// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
// implied. See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
// CL_SH_ID0
|
||||
// - PCIe Vendor/Device ID Values
|
||||
// 31:16: PCIe Device ID
|
||||
// 15: 0: PCIe Vendor ID
|
||||
// - A Vendor ID value of 0x8086 is not valid.
|
||||
// - If using a Vendor ID value of 0x1D0F (Amazon) then valid
|
||||
// values for Device ID's are in the range of 0xF000 - 0xF0FF.
|
||||
// - A Vendor/Device ID of 0 (zero) is not valid.
|
||||
`define CL_SH_ID0 32'hF000_1D0F
|
||||
|
||||
// CL_SH_ID1
|
||||
// - PCIe Subsystem/Subsystem Vendor ID Values
|
||||
// 31:16: PCIe Subsystem ID
|
||||
// 15: 0: PCIe Subsystem Vendor ID
|
||||
// - A PCIe Subsystem/Subsystem Vendor ID of 0 (zero) is not valid
|
||||
`define CL_SH_ID1 32'h1D51_FEDD
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,224 @@
|
|||
// Amazon FPGA Hardware Development Kit
|
||||
//
|
||||
// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
//
|
||||
// Licensed under the Amazon Software License (the "License"). You may not use
|
||||
// this file except in compliance with the License. A copy of the License is
|
||||
// located at
|
||||
//
|
||||
// http://aws.amazon.com/asl/
|
||||
//
|
||||
// or in the "license" file accompanying this file. This file is distributed on
|
||||
// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
// implied. See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
module cl_zcash
|
||||
|
||||
(
|
||||
`include "cl_ports.vh" // Fixed port definition
|
||||
|
||||
);
|
||||
|
||||
`include "cl_common_defines.vh" // CL Defines for all examples
|
||||
`include "cl_id_defines.vh" // Defines for ID0 and ID1 (PCI ID's)
|
||||
`include "cl_zcash_defines.vh" // CL Defines for cl_hello_world
|
||||
|
||||
logic rst_main_n_sync;
|
||||
|
||||
logic clk_if, clk_100, clk_200, clk_300;
|
||||
logic rst_if, rst_100, rst_200, rst_300;
|
||||
|
||||
if_axi_stream #(.DAT_BYTS(8), .CTL_BITS(1)) zcash_if_rx (clk_if);
|
||||
if_axi_stream #(.DAT_BYTS(8), .CTL_BITS(1)) zcash_if_tx (clk_if);
|
||||
|
||||
if_axi_lite #(.A_BITS(32)) zcash_axi_lite_if (clk_if);
|
||||
if_axi_lite #(.A_BITS(32)) rx_axi_lite_if (clk_if);
|
||||
if_axi4 #(.A_WIDTH(64), .D_WIDTH(512), .ID_WIDTH(6)) rx_axi4_if (clk_if);
|
||||
|
||||
//--------------------------------------------0
|
||||
// Start with Tie-Off of Unused Interfaces
|
||||
//---------------------------------------------
|
||||
// the developer should use the next set of `include
|
||||
// to properly tie-off any unused interface
|
||||
// The list is put in the top of the module
|
||||
// to avoid cases where developer may forget to
|
||||
// remove it from the end of the file
|
||||
|
||||
`include "unused_flr_template.inc"
|
||||
`include "unused_ddr_a_b_d_template.inc"
|
||||
`include "unused_ddr_c_template.inc"
|
||||
`include "unused_pcim_template.inc"
|
||||
//`include "unused_dma_pcis_template.inc"
|
||||
`include "unused_cl_sda_template.inc"
|
||||
`include "unused_sh_bar1_template.inc"
|
||||
`include "unused_apppf_irq_template.inc"
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// ID Values (cl_id_defines.vh)
|
||||
//-------------------------------------------------
|
||||
assign cl_sh_id0[31:0] = `CL_SH_ID0;
|
||||
assign cl_sh_id1[31:0] = `CL_SH_ID1;
|
||||
|
||||
//-------------------------------------------------
|
||||
// Reset Synchronization
|
||||
//-------------------------------------------------
|
||||
logic pre_sync_rst_n;
|
||||
|
||||
always_ff @(negedge rst_main_n or posedge clk_main_a0)
|
||||
if (!rst_main_n)
|
||||
begin
|
||||
pre_sync_rst_n <= 0;
|
||||
rst_main_n_sync <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
pre_sync_rst_n <= 1;
|
||||
rst_main_n_sync <= pre_sync_rst_n;
|
||||
end
|
||||
|
||||
//-------------------------------------------------
|
||||
// PCIe OCL AXI-L (SH to CL) Timing Flops
|
||||
//-------------------------------------------------
|
||||
|
||||
// Write address
|
||||
logic sh_ocl_awvalid_q;
|
||||
logic [31:0] sh_ocl_awaddr_q;
|
||||
logic ocl_sh_awready_q;
|
||||
|
||||
// Write data
|
||||
logic sh_ocl_wvalid_q;
|
||||
logic [31:0] sh_ocl_wdata_q;
|
||||
logic [ 3:0] sh_ocl_wstrb_q;
|
||||
logic ocl_sh_wready_q;
|
||||
|
||||
// Write response
|
||||
logic ocl_sh_bvalid_q;
|
||||
logic [ 1:0] ocl_sh_bresp_q;
|
||||
logic sh_ocl_bready_q;
|
||||
|
||||
// Read address
|
||||
logic sh_ocl_arvalid_q;
|
||||
logic [31:0] sh_ocl_araddr_q;
|
||||
logic ocl_sh_arready_q;
|
||||
|
||||
// Read data/response
|
||||
logic ocl_sh_rvalid_q;
|
||||
logic [31:0] ocl_sh_rdata_q;
|
||||
logic [ 1:0] ocl_sh_rresp_q;
|
||||
logic sh_ocl_rready_q;
|
||||
|
||||
axi_register_slice_light AXIL_OCL_REG_SLC (
|
||||
.aclk (clk_main_a0),
|
||||
.aresetn (rst_main_n_sync),
|
||||
.s_axi_awaddr (sh_ocl_awaddr),
|
||||
.s_axi_awprot (2'h0),
|
||||
.s_axi_awvalid (sh_ocl_awvalid),
|
||||
.s_axi_awready (ocl_sh_awready),
|
||||
.s_axi_wdata (sh_ocl_wdata),
|
||||
.s_axi_wstrb (sh_ocl_wstrb),
|
||||
.s_axi_wvalid (sh_ocl_wvalid),
|
||||
.s_axi_wready (ocl_sh_wready),
|
||||
.s_axi_bresp (ocl_sh_bresp),
|
||||
.s_axi_bvalid (ocl_sh_bvalid),
|
||||
.s_axi_bready (sh_ocl_bready),
|
||||
.s_axi_araddr (sh_ocl_araddr),
|
||||
.s_axi_arvalid (sh_ocl_arvalid),
|
||||
.s_axi_arready (ocl_sh_arready),
|
||||
.s_axi_rdata (ocl_sh_rdata),
|
||||
.s_axi_rresp (ocl_sh_rresp),
|
||||
.s_axi_rvalid (ocl_sh_rvalid),
|
||||
.s_axi_rready (sh_ocl_rready),
|
||||
.m_axi_awaddr (rx_axi_lite_if.awaddr),
|
||||
.m_axi_awprot (),
|
||||
.m_axi_awvalid (rx_axi_lite_if.awvalid),
|
||||
.m_axi_awready (rx_axi_lite_if.awready),
|
||||
.m_axi_wdata (rx_axi_lite_if.wdata),
|
||||
.m_axi_wstrb (rx_axi_lite_if.wstrb),
|
||||
.m_axi_wvalid (rx_axi_lite_if.wvalid),
|
||||
.m_axi_wready (rx_axi_lite_if.wready),
|
||||
.m_axi_bresp (rx_axi_lite_if.bresp),
|
||||
.m_axi_bvalid (rx_axi_lite_if.bvalid),
|
||||
.m_axi_bready (rx_axi_lite_if.bready),
|
||||
.m_axi_araddr (rx_axi_lite_if.araddr),
|
||||
.m_axi_arvalid (rx_axi_lite_if.arvalid),
|
||||
.m_axi_arready (rx_axi_lite_if.arready),
|
||||
.m_axi_rdata (rx_axi_lite_if.rdata),
|
||||
.m_axi_rresp (rx_axi_lite_if.rresp),
|
||||
.m_axi_rvalid (rx_axi_lite_if.rvalid),
|
||||
.m_axi_rready (rx_axi_lite_if.rready)
|
||||
);
|
||||
|
||||
always_comb begin
|
||||
clk_if = clk_main_a0;
|
||||
clk_100 = clk_main_a0; // 125MHz
|
||||
clk_200 = clk_main_a0; // 187MHz
|
||||
clk_300 = clk_extra_b0; // 300MHz
|
||||
end
|
||||
|
||||
always_ff @(posedge clk_if) rst_if <= !rst_main_n;
|
||||
always_ff @(posedge clk_100) rst_100 <= !rst_main_n;
|
||||
always_ff @(posedge clk_200) rst_200 <= !rst_main_n;
|
||||
always_ff @(posedge clk_300) rst_300 <= !rst_main_n;
|
||||
|
||||
always_comb begin
|
||||
rx_axi4_if.awid = sh_cl_dma_pcis_awid;
|
||||
rx_axi4_if.awaddr = sh_cl_dma_pcis_awaddr;
|
||||
rx_axi4_if.awlen = sh_cl_dma_pcis_awlen;
|
||||
rx_axi4_if.awsize = sh_cl_dma_pcis_awsize;
|
||||
rx_axi4_if.awvalid = sh_cl_dma_pcis_awvalid;
|
||||
cl_sh_dma_pcis_awready = rx_axi4_if.awready;
|
||||
rx_axi4_if.wdata = sh_cl_dma_pcis_wdata;
|
||||
rx_axi4_if.wstrb = sh_cl_dma_pcis_wstrb;
|
||||
rx_axi4_if.wlast = sh_cl_dma_pcis_wlast;
|
||||
rx_axi4_if.wvalid = sh_cl_dma_pcis_wvalid;
|
||||
cl_sh_dma_pcis_wready = rx_axi4_if.wready;
|
||||
cl_sh_dma_pcis_bid = rx_axi4_if.bid;
|
||||
cl_sh_dma_pcis_bresp = rx_axi4_if.bresp;
|
||||
cl_sh_dma_pcis_bvalid = rx_axi4_if.bvalid;
|
||||
rx_axi4_if.bready = sh_cl_dma_pcis_bready;
|
||||
rx_axi4_if.arid = sh_cl_dma_pcis_arid;
|
||||
rx_axi4_if.araddr = sh_cl_dma_pcis_araddr;
|
||||
rx_axi4_if.arlen = sh_cl_dma_pcis_arlen;
|
||||
rx_axi4_if.arsize = sh_cl_dma_pcis_arsize;
|
||||
rx_axi4_if.arvalid = sh_cl_dma_pcis_arvalid;
|
||||
cl_sh_dma_pcis_arready = rx_axi4_if.arready;
|
||||
cl_sh_dma_pcis_rid = rx_axi4_if.rid;
|
||||
cl_sh_dma_pcis_rdata = rx_axi4_if.rdata;
|
||||
cl_sh_dma_pcis_rresp = rx_axi4_if.rresp;
|
||||
cl_sh_dma_pcis_rlast = rx_axi4_if.rlast;
|
||||
cl_sh_dma_pcis_rvalid = rx_axi4_if.rvalid;
|
||||
rx_axi4_if.rready = sh_cl_dma_pcis_rready;
|
||||
end
|
||||
|
||||
cl_zcash_aws_wrapper cl_zcash_aws_wrapper (
|
||||
.i_rst ( rst_if ),
|
||||
.i_clk ( clk_if ),
|
||||
.rx_axi_lite_if ( rx_axi_lite_if ),
|
||||
.rx_axi4_if ( rx_axi4_if ),
|
||||
.zcash_axi_lite_if ( zcash_axi_lite_if ),
|
||||
.rx_zcash_if ( zcash_if_tx ),
|
||||
.tx_zcash_if ( zcash_if_rx )
|
||||
);
|
||||
|
||||
|
||||
zcash_fpga_top #(
|
||||
.DAT_BYTS ( 8 )
|
||||
)
|
||||
zcash_fpga_top (
|
||||
// Clocks and resets
|
||||
.i_clk_100 ( clk_100 ),
|
||||
.i_rst_100 ( rst_100 ),
|
||||
.i_clk_200 ( clk_200 ),
|
||||
.i_rst_200 ( rst_200 ),
|
||||
.i_clk_300 ( clk_300 ),
|
||||
.i_rst_300 ( rst_300 ),
|
||||
.i_clk_if ( clk_if ),
|
||||
.i_rst_if ( rst_if ),
|
||||
.rx_if ( zcash_if_rx ),
|
||||
.tx_if ( zcash_if_tx ),
|
||||
.axi_lite_if (zcash_axi_lite_if)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,236 @@
|
|||
/*
|
||||
Takes in PCIs and OCL connections and converts to interfaces for use in the zcash FPGA project.
|
||||
|
||||
Copyright (C) 2019 Benjamin Devlin and Zcash Foundation
|
||||
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
module cl_zcash_aws_wrapper (
|
||||
input i_rst,
|
||||
input i_clk,
|
||||
// AWS facing interfaces
|
||||
if_axi_lite.sink rx_axi_lite_if, // OCL interface
|
||||
if_axi4.sink rx_axi4_if, // PCIS interface
|
||||
// Zcash interfaces
|
||||
if_axi_lite.source zcash_axi_lite_if,
|
||||
if_axi_stream.sink rx_zcash_if,
|
||||
if_axi_stream.source tx_zcash_if
|
||||
);
|
||||
|
||||
`include "cl_zcash_defines.vh"
|
||||
|
||||
if_axi_lite #(.A_BITS(32)) axi_fifo_if (i_clk);
|
||||
|
||||
if_axi_stream #(.DAT_BYTS(64), .CTL_BITS(1)) rx_aws_if (i_clk);
|
||||
if_axi_stream #(.DAT_BYTS(64), .CTL_BITS(1)) tx_aws_if (i_clk);
|
||||
|
||||
logic [7:0] rx_zcash_if_keep, tx_zcash_if_keep;
|
||||
|
||||
always_comb begin
|
||||
rx_zcash_if_keep = rx_zcash_if.get_keep_from_mod();
|
||||
tx_zcash_if.set_mod_from_keep( tx_zcash_if_keep );
|
||||
end
|
||||
|
||||
always_ff @ (posedge i_clk) begin
|
||||
if (i_rst) begin
|
||||
tx_zcash_if.ctl <= 0;
|
||||
tx_zcash_if.err <= 0;
|
||||
tx_zcash_if.sop <= 1;
|
||||
tx_aws_if.ctl <= 0;
|
||||
tx_aws_if.err <= 0;
|
||||
tx_aws_if.sop <= 1;
|
||||
end else begin
|
||||
if (tx_zcash_if.val && tx_zcash_if.rdy) tx_zcash_if.sop <= tx_zcash_if.eop;
|
||||
if (tx_aws_if.val && tx_aws_if.rdy) tx_aws_if.sop <= tx_aws_if.eop;
|
||||
end
|
||||
end
|
||||
|
||||
// Map the AXI-lite signals
|
||||
logic wr_active;
|
||||
logic [31:0] wr_addr, araddr;
|
||||
|
||||
logic axi_fifo_dec;
|
||||
logic zcash_dec;
|
||||
|
||||
always_comb begin
|
||||
zcash_dec = (wr_addr >= `ZCASH_OFFSET && wr_addr < (`ZCASH_OFFSET + `AXI_MEMORY_SIZE)) ||
|
||||
(araddr >= `ZCASH_OFFSET && araddr < (`ZCASH_OFFSET + `AXI_MEMORY_SIZE));
|
||||
|
||||
axi_fifo_dec = (wr_addr >= `AXI_FIFO_OFFSET && wr_addr < (`AXI_FIFO_OFFSET + `AXI_MEMORY_SIZE)) ||
|
||||
(araddr >= `AXI_FIFO_OFFSET && araddr < (`AXI_FIFO_OFFSET + `AXI_MEMORY_SIZE));
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
zcash_axi_lite_if.awvalid = rx_axi_lite_if.awvalid && zcash_dec;
|
||||
zcash_axi_lite_if.awaddr = rx_axi_lite_if.awaddr;
|
||||
zcash_axi_lite_if.wvalid = rx_axi_lite_if.wvalid;
|
||||
zcash_axi_lite_if.wdata = rx_axi_lite_if.wdata;
|
||||
zcash_axi_lite_if.wstrb = rx_axi_lite_if.wstrb;
|
||||
zcash_axi_lite_if.bready = rx_axi_lite_if.bready;
|
||||
zcash_axi_lite_if.arvalid = rx_axi_lite_if.arvalid;
|
||||
zcash_axi_lite_if.rready = rx_axi_lite_if.rready;
|
||||
zcash_axi_lite_if.araddr = rx_axi_lite_if.araddr;
|
||||
zcash_axi_lite_if.arvalid = rx_axi_lite_if.arvalid;
|
||||
|
||||
axi_fifo_if.awvalid = rx_axi_lite_if.awvalid && axi_fifo_dec;
|
||||
axi_fifo_if.awaddr = rx_axi_lite_if.awaddr;
|
||||
axi_fifo_if.wvalid = rx_axi_lite_if.wvalid;
|
||||
axi_fifo_if.wdata = rx_axi_lite_if.wdata;
|
||||
axi_fifo_if.wstrb = rx_axi_lite_if.wstrb;
|
||||
axi_fifo_if.bready = rx_axi_lite_if.bready;
|
||||
axi_fifo_if.arvalid = rx_axi_lite_if.arvalid;
|
||||
axi_fifo_if.rready = rx_axi_lite_if.rready;
|
||||
axi_fifo_if.araddr = rx_axi_lite_if.araddr;
|
||||
axi_fifo_if.arvalid = rx_axi_lite_if.arvalid;
|
||||
|
||||
|
||||
rx_axi_lite_if.awready = zcash_dec ? zcash_axi_lite_if.awready : axi_fifo_if.awready;
|
||||
rx_axi_lite_if.wready = zcash_dec ? zcash_axi_lite_if.wready : axi_fifo_if.wready;
|
||||
rx_axi_lite_if.bvalid = zcash_dec ? zcash_axi_lite_if.bvalid : axi_fifo_if.bvalid;
|
||||
rx_axi_lite_if.bresp = 0;
|
||||
rx_axi_lite_if.arready = zcash_dec ? zcash_axi_lite_if.arready : axi_fifo_if.arready;
|
||||
rx_axi_lite_if.rvalid = zcash_dec ? zcash_axi_lite_if.rvalid : axi_fifo_if.rvalid;
|
||||
rx_axi_lite_if.rdata = zcash_dec ? zcash_axi_lite_if.rdata : axi_fifo_if.rdata;
|
||||
rx_axi_lite_if.rresp = 0;
|
||||
end
|
||||
|
||||
// Write Request
|
||||
always_ff @(posedge i_clk) begin
|
||||
if (i_rst) begin
|
||||
wr_active <= 0;
|
||||
wr_addr <= 0;
|
||||
end else begin
|
||||
wr_active <= wr_active && rx_axi_lite_if.bvalid && rx_axi_lite_if.bready ? 1'b0 :
|
||||
~wr_active && rx_axi_lite_if.awvalid ? 1'b1 :
|
||||
wr_active;
|
||||
wr_addr <= rx_axi_lite_if.awvalid && ~wr_active ? rx_axi_lite_if.awaddr : wr_addr;
|
||||
end
|
||||
end
|
||||
|
||||
// Read Request
|
||||
always_ff @(posedge i_clk) begin
|
||||
if (i_rst) begin
|
||||
araddr <= 0;
|
||||
end else begin
|
||||
araddr <= rx_axi_lite_if.arvalid ? rx_axi_lite_if.araddr : araddr;
|
||||
end
|
||||
end
|
||||
|
||||
// Convert 8 bytes to 64 bytes
|
||||
axis_dwidth_converter_8_to_64 converter_8_to_64 (
|
||||
.aclk ( i_clk ),
|
||||
.aresetn( ~i_rst ),
|
||||
.s_axis_tvalid( rx_zcash_if.val ),
|
||||
.s_axis_tready( rx_zcash_if.rdy ),
|
||||
.s_axis_tdata ( rx_zcash_if.dat ),
|
||||
.s_axis_tlast ( rx_zcash_if.eop ),
|
||||
.s_axis_tkeep ( rx_zcash_if_keep ),
|
||||
.m_axis_tvalid( tx_aws_if.val ),
|
||||
.m_axis_tready( tx_aws_if.rdy ),
|
||||
.m_axis_tdata ( tx_aws_if.dat ),
|
||||
.m_axis_tlast ( tx_aws_if.eop ),
|
||||
.m_axis_tkeep ()
|
||||
);
|
||||
|
||||
// Convert 64 bytes to 8 bytes
|
||||
axis_dwidth_converter_64_to_8 converter_64_to_8 (
|
||||
.aclk ( i_clk ),
|
||||
.aresetn( ~i_rst ),
|
||||
.s_axis_tvalid( rx_aws_if.val ),
|
||||
.s_axis_tready( rx_aws_if.rdy ),
|
||||
.s_axis_tdata ( rx_aws_if.dat ),
|
||||
.s_axis_tlast ( rx_aws_if.eop ),
|
||||
.s_axis_tkeep (0),
|
||||
.m_axis_tvalid( tx_zcash_if.val ),
|
||||
.m_axis_tready( tx_zcash_if.rdy ),
|
||||
.m_axis_tdata ( tx_zcash_if.dat ),
|
||||
.m_axis_tlast ( tx_zcash_if.eop ),
|
||||
.m_axis_tkeep ()
|
||||
);
|
||||
|
||||
|
||||
// Convert our AXI stream interfaces into AXI4 on PCIS
|
||||
axi_fifo_mm_s_0 axi_fifo_mm_s_0 (
|
||||
.interrupt(),
|
||||
.s_axi_aclk ( i_clk ),
|
||||
.s_axi_aresetn ( ~i_rst ),
|
||||
|
||||
.s_axi_awaddr ( axi_fifo_if.awaddr ),
|
||||
.s_axi_awvalid ( axi_fifo_if.awvalid ),
|
||||
.s_axi_awready ( axi_fifo_if.awready ),
|
||||
.s_axi_wdata ( axi_fifo_if.wdata ),
|
||||
.s_axi_wstrb ( axi_fifo_if.wstrb ),
|
||||
.s_axi_wvalid ( axi_fifo_if.wvalid ),
|
||||
.s_axi_wready ( axi_fifo_if.wready ),
|
||||
.s_axi_bresp ( axi_fifo_if.bresp ),
|
||||
.s_axi_bvalid ( axi_fifo_if.bvalid ),
|
||||
.s_axi_bready ( axi_fifo_if.bready ),
|
||||
.s_axi_araddr ( axi_fifo_if.araddr ),
|
||||
.s_axi_arvalid ( axi_fifo_if.arvalid ),
|
||||
.s_axi_arready ( axi_fifo_if.arready ),
|
||||
.s_axi_rdata ( axi_fifo_if.rdata ),
|
||||
.s_axi_rresp ( axi_fifo_if.rresp ),
|
||||
.s_axi_rvalid ( axi_fifo_if.rvalid ),
|
||||
.s_axi_rready ( axi_fifo_if.rready ),
|
||||
|
||||
.s_axi4_awid ( rx_axi4_if.awid ),
|
||||
.s_axi4_awaddr ( rx_axi4_if.awaddr ),
|
||||
.s_axi4_awlen ( rx_axi4_if.awlen ),
|
||||
.s_axi4_awsize ( rx_axi4_if.awsize ),
|
||||
.s_axi4_awburst( rx_axi4_if.awburst ),
|
||||
.s_axi4_awlock ( rx_axi4_if.awlock ),
|
||||
.s_axi4_awcache( rx_axi4_if.awcache ),
|
||||
.s_axi4_awprot ( rx_axi4_if.awprot ),
|
||||
.s_axi4_awvalid( rx_axi4_if.awvalid ),
|
||||
.s_axi4_awready( rx_axi4_if.awready ),
|
||||
.s_axi4_wdata ( rx_axi4_if.wdata ),
|
||||
.s_axi4_wstrb ( rx_axi4_if.wstrb ),
|
||||
.s_axi4_wlast ( rx_axi4_if.wlast ),
|
||||
.s_axi4_wvalid ( rx_axi4_if.wvalid ),
|
||||
.s_axi4_wready ( rx_axi4_if.wready ),
|
||||
.s_axi4_bid ( rx_axi4_if.bid ),
|
||||
.s_axi4_bresp ( rx_axi4_if.bresp ),
|
||||
.s_axi4_bvalid ( rx_axi4_if.bvalid ),
|
||||
.s_axi4_bready ( rx_axi4_if.bready ),
|
||||
.s_axi4_arid ( rx_axi4_if.arid ),
|
||||
.s_axi4_araddr ( rx_axi4_if.araddr ),
|
||||
.s_axi4_arlen ( rx_axi4_if.arlen ),
|
||||
.s_axi4_arsize ( rx_axi4_if.arsize ),
|
||||
.s_axi4_arburst( rx_axi4_if.arburst ),
|
||||
.s_axi4_arlock ( rx_axi4_if.arlock ),
|
||||
.s_axi4_arcache( rx_axi4_if.arcache ),
|
||||
.s_axi4_arprot ( rx_axi4_if.arprot ),
|
||||
.s_axi4_arvalid( rx_axi4_if.arvalid ),
|
||||
.s_axi4_arready( rx_axi4_if.arready ),
|
||||
.s_axi4_rid ( rx_axi4_if.rid ),
|
||||
.s_axi4_rdata ( rx_axi4_if.rdata ),
|
||||
.s_axi4_rresp ( rx_axi4_if.rresp ),
|
||||
.s_axi4_rlast ( rx_axi4_if.rlast ),
|
||||
.s_axi4_rvalid ( rx_axi4_if.rvalid ),
|
||||
.s_axi4_rready ( rx_axi4_if.rready ),
|
||||
|
||||
.mm2s_prmry_reset_out_n(),
|
||||
.axi_str_txd_tvalid ( rx_aws_if.val ),
|
||||
.axi_str_txd_tready ( rx_aws_if.rdy ),
|
||||
.axi_str_txd_tlast ( rx_aws_if.eop ),
|
||||
.axi_str_txd_tdata ( rx_aws_if.dat ),
|
||||
|
||||
.s2mm_prmry_reset_out_n(),
|
||||
.axi_str_rxd_tvalid( tx_aws_if.val ),
|
||||
.axi_str_rxd_tready( tx_aws_if.rdy ),
|
||||
.axi_str_rxd_tlast ( tx_aws_if.eop ),
|
||||
.axi_str_rxd_tdata ( tx_aws_if.dat )
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
// Amazon FPGA Hardware Development Kit
|
||||
//
|
||||
// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
//
|
||||
// Licensed under the Amazon Software License (the "License"). You may not use
|
||||
// this file except in compliance with the License. A copy of the License is
|
||||
// located at
|
||||
//
|
||||
// http://aws.amazon.com/asl/
|
||||
//
|
||||
// or in the "license" file accompanying this file. This file is distributed on
|
||||
// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
// implied. See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
`ifndef CL_ZCASH_DEFINES
|
||||
`define CL_ZCASH_DEFINES
|
||||
|
||||
//Put module name of the CL design here. This is used to instantiate in top.sv
|
||||
`define CL_NAME cl_zcash
|
||||
|
||||
`define UNIMPLEMENTED_REG_VALUE 32'hffffffff
|
||||
`define AXI_MEMORY_SIZE 32'h1000
|
||||
`define AXI_FIFO_OFFSET 32'h0
|
||||
`define ZCASH_OFFSET 32'h1000
|
||||
|
||||
//Highly recommeneded. For lib FIFO block, uses less async reset (take advantage of
|
||||
// FPGA flop init capability). This will help with routing resources.
|
||||
`define FPGA_LESS_RST
|
||||
|
||||
// Uncomment to disable Virtual JTAG
|
||||
//`define DISABLE_VJTAG_DEBUG
|
||||
|
||||
`endif
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
/*
|
||||
!/*.xci
|
||||
!/.gitignore
|
||||
|
|
@ -0,0 +1,254 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>axi_fifo_mm_s_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_fifo_mm_s" spirit:version="4.2"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="ADDRBLOCK_RANGE.S_AXI.Mem0">4096</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="ADDRBLOCK_RANGE.S_AXI_FULL.Mem1">4096</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_S_AXI.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_RXD.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_RXD.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_RXD.HAS_TKEEP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_RXD.HAS_TLAST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_RXD.HAS_TREADY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_RXD.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_RXD.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_RXD.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_RXD.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_RXD.TDATA_NUM_BYTES">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_RXD.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_RXD.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_RXD.TUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXC.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXC.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXC.HAS_TKEEP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXC.HAS_TLAST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXC.HAS_TREADY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXC.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXC.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXC.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXC.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXC.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXC.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXC.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXC.TUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXD.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXD.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXD.HAS_TKEEP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXD.HAS_TLAST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXD.HAS_TREADY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXD.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXD.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXD.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXD.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXD.TDATA_NUM_BYTES">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXD.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXD.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXD.TUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT_INTF.PortWidth">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST_AXI_STR_RXD.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST_AXI_STR_TXC.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST_AXI_STR_TXD.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST_S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.DATA_WIDTH">512</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.HAS_BURST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.HAS_CACHE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.HAS_LOCK">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.HAS_PROT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.HAS_WSTRB">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.ID_WIDTH">6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.MAX_BURST_LENGTH">256</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.PROTOCOL">AXI4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.SUPPORTS_NARROW_BURST">1</spirit:configurableElementValue>
|
||||
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_INTERFACE_TYPE">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HIGHADDR">0x00000FFF</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI4_DATA_WIDTH">512</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ID_WIDTH">6</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_FIFO_PE_THRESHOLD">5</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_FIFO_PF_THRESHOLD">507</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RX_DATA">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TX_CTRL">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TX_CUT_THROUGH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TX_DATA">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXI4_BASEADDR">0x00001000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXI4_HIGHADDR">0x00002FFF</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXIS_TDEST_WIDTH">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXIS_TID_WIDTH">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXIS_TUSER_WIDTH">64</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXI_STR_RXD_PROTOCOL">XIL_AXI_STREAM_ETH_DATA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXI_STR_RXD_TDATA_WIDTH">32</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXI_STR_TXC_PROTOCOL">XIL_AXI_STREAM_ETH_CTRL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXI_STR_TXC_TDATA_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXI_STR_TXD_PROTOCOL">XIL_AXI_STREAM_ETH_DATA</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXI_STR_TXD_TDATA_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BASEADDR">0x00000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DATA_INTERFACE_TYPE">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_HAS_AXIS_TDEST">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_HAS_AXIS_TID">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_HAS_AXIS_TKEEP">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_HAS_AXIS_TSTRB">false</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_HAS_AXIS_TUSER">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_HIGHADDR">0x80000FFF</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_RX_FIFO_DEPTH">512</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_RX_FIFO_PE_THRESHOLD">5</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_RX_FIFO_PF_THRESHOLD">507</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI4_DATA_WIDTH">512</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_ID_WIDTH">6</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_PROTOCOL">AXI4LITE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TX_FIFO_DEPTH">512</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TX_FIFO_PE_THRESHOLD">5</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TX_FIFO_PF_THRESHOLD">507</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_RX_CUT_THROUGH">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_RX_DATA">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_TX_CTRL">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_TX_CUT_THROUGH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_TX_DATA">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axi_fifo_mm_s_0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcvu9p</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">flgb2104</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
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<spirit:vendorExtensions>
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<xilinx:componentInstanceExtensions>
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<xilinx:configElementInfos>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_STR_RXD.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXC.HAS_TREADY" xilinx:valueSource="auto"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXD.HAS_TLAST" xilinx:valueSource="auto"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXD.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.BUSER_WIDTH" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.DATA_WIDTH" xilinx:valueSource="auto"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.HAS_QOS" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.HAS_REGION" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.ID_WIDTH" xilinx:valueSource="auto"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.RUSER_WIDTH" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.WUSER_WIDTH" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AXIS_TUSER_WIDTH" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_DATA_INTERFACE_TYPE" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_S_AXI4_DATA_WIDTH" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_S_AXI_ID_WIDTH" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_TX_CTRL" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_TX_CUT_THROUGH" xilinx:valueSource="user"/>
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||||
</spirit:design>
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||||
|
|
@ -0,0 +1,104 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:componentInstances>
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<spirit:componentInstance>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_SIGNAL_SET">0b00000000000000000000000000010011</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">virtexuplus</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_TDATA_WIDTH">64</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_TUSER_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TLAST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TREADY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_TDATA_NUM_BYTES">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_TDATA_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcvu9p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">flgb2104</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2018.2.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_MI_TKEEP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_TKEEP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_TLAST" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M_TDATA_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S_TDATA_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
# Amazon FPGA Hardware Development Kit
|
||||
#
|
||||
# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
#
|
||||
# Licensed under the Amazon Software License (the "License"). You may not use
|
||||
# this file except in compliance with the License. A copy of the License is
|
||||
# located at
|
||||
#
|
||||
# http://aws.amazon.com/asl/
|
||||
#
|
||||
# or in the "license" file accompanying this file. This file is distributed on
|
||||
# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
# implied. See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
VPATH = src:include:$(HDK_DIR)/common/software/src:$(HDK_DIR)/common/software/include
|
||||
|
||||
INCLUDES = -I$(SDK_DIR)/userspace/include
|
||||
INCLUDES += -I $(HDK_DIR)/common/software/include
|
||||
INCLUDES += -I ./include
|
||||
|
||||
CC = gcc
|
||||
CFLAGS = -DCONFIG_LOGLEVEL=4 -g -Wall $(INCLUDES)
|
||||
|
||||
LDLIBS = -lfpga_mgmt -lrt -lpthread
|
||||
|
||||
SRC = ${SDK_DIR}/userspace/utils/sh_dpi_tasks.c test_hello_world.c
|
||||
OBJ = $(SRC:.c=.o)
|
||||
BIN = test_hello_world
|
||||
|
||||
all: $(BIN) check_env
|
||||
|
||||
$(BIN): $(OBJ)
|
||||
$(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) $(LDLIBS)
|
||||
|
||||
clean:
|
||||
rm -f *.o $(BIN)
|
||||
|
||||
check_env:
|
||||
ifndef SDK_DIR
|
||||
$(error SDK_DIR is undefined. Try "source sdk_setup.sh" to set the software environment)
|
||||
endif
|
||||
|
|
@ -0,0 +1,288 @@
|
|||
// Amazon FPGA Hardware Development Kit
|
||||
//
|
||||
// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
//
|
||||
// Licensed under the Amazon Software License (the "License"). You may not use
|
||||
// this file except in compliance with the License. A copy of the License is
|
||||
// located at
|
||||
//
|
||||
// http://aws.amazon.com/asl/
|
||||
//
|
||||
// or in the "license" file accompanying this file. This file is distributed on
|
||||
// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
// implied. See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdarg.h>
|
||||
#include <assert.h>
|
||||
#include <string.h>
|
||||
|
||||
#ifdef SV_TEST
|
||||
#include "fpga_pci_sv.h"
|
||||
#else
|
||||
#include <fpga_pci.h>
|
||||
#include <fpga_mgmt.h>
|
||||
#include <utils/lcd.h>
|
||||
#endif
|
||||
|
||||
#include <utils/sh_dpi_tasks.h>
|
||||
|
||||
/* Constants determined by the CL */
|
||||
/* a set of register offsets; this CL has only one */
|
||||
/* these register addresses should match the addresses in */
|
||||
/* /aws-fpga/hdk/cl/examples/common/cl_common_defines.vh */
|
||||
/* SV_TEST macro should be set if SW/HW co-simulation should be enabled */
|
||||
|
||||
#define HELLO_WORLD_REG_ADDR UINT64_C(0x500)
|
||||
#define VLED_REG_ADDR UINT64_C(0x504)
|
||||
|
||||
/* use the stdout logger for printing debug information */
|
||||
#ifndef SV_TEST
|
||||
const struct logger *logger = &logger_stdout;
|
||||
/*
|
||||
* pci_vendor_id and pci_device_id values below are Amazon's and avaliable to use for a given FPGA slot.
|
||||
* Users may replace these with their own if allocated to them by PCI SIG
|
||||
*/
|
||||
static uint16_t pci_vendor_id = 0x1D0F; /* Amazon PCI Vendor ID */
|
||||
static uint16_t pci_device_id = 0xF000; /* PCI Device ID preassigned by Amazon for F1 applications */
|
||||
|
||||
/*
|
||||
* check if the corresponding AFI for hello_world is loaded
|
||||
*/
|
||||
int check_afi_ready(int slot_id);
|
||||
/*
|
||||
* An example to attach to an arbitrary slot, pf, and bar with register access.
|
||||
*/
|
||||
int peek_poke_example(uint32_t value, int slot_id, int pf_id, int bar_id);
|
||||
|
||||
void usage(char* program_name) {
|
||||
printf("usage: %s [--slot <slot-id>][<poke-value>]\n", program_name);
|
||||
}
|
||||
|
||||
uint32_t byte_swap(uint32_t value);
|
||||
|
||||
#endif
|
||||
|
||||
uint32_t byte_swap(uint32_t value) {
|
||||
uint32_t swapped_value = 0;
|
||||
int b;
|
||||
for (b = 0; b < 4; b++) {
|
||||
swapped_value |= ((value >> (b * 8)) & 0xff) << (8 * (3-b));
|
||||
}
|
||||
return swapped_value;
|
||||
}
|
||||
|
||||
#ifdef SV_TEST
|
||||
//For cadence and questa simulators the main has to return some value
|
||||
#ifdef INT_MAIN
|
||||
int test_main(uint32_t *exit_code) {
|
||||
#else
|
||||
void test_main(uint32_t *exit_code) {
|
||||
#endif
|
||||
#else
|
||||
int main(int argc, char **argv) {
|
||||
#endif
|
||||
//The statements within SCOPE ifdef below are needed for HW/SW co-simulation with VCS
|
||||
#ifdef SCOPE
|
||||
svScope scope;
|
||||
scope = svGetScopeFromName("tb");
|
||||
svSetScope(scope);
|
||||
#endif
|
||||
|
||||
uint32_t value = 0xefbeadde;
|
||||
int slot_id = 0;
|
||||
int rc;
|
||||
|
||||
#ifndef SV_TEST
|
||||
// Process command line args
|
||||
{
|
||||
int i;
|
||||
int value_set = 0;
|
||||
for (i = 1; i < argc; i++) {
|
||||
if (!strcmp(argv[i], "--slot")) {
|
||||
i++;
|
||||
if (i >= argc) {
|
||||
printf("error: missing slot-id\n");
|
||||
usage(argv[0]);
|
||||
return 1;
|
||||
}
|
||||
sscanf(argv[i], "%d", &slot_id);
|
||||
} else if (!value_set) {
|
||||
sscanf(argv[i], "%x", &value);
|
||||
value_set = 1;
|
||||
} else {
|
||||
printf("error: Invalid arg: %s", argv[i]);
|
||||
usage(argv[0]);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* initialize the fpga_pci library so we could have access to FPGA PCIe from this applications */
|
||||
rc = fpga_pci_init();
|
||||
fail_on(rc, out, "Unable to initialize the fpga_pci library");
|
||||
|
||||
#ifndef SV_TEST
|
||||
rc = check_afi_ready(slot_id);
|
||||
fail_on(rc, out, "AFI not ready");
|
||||
#endif
|
||||
|
||||
|
||||
/* Accessing the CL registers via AppPF BAR0, which maps to sh_cl_ocl_ AXI-Lite bus between AWS FPGA Shell and the CL*/
|
||||
|
||||
printf("===== Starting with peek_poke_example =====\n");
|
||||
rc = peek_poke_example(value, slot_id, FPGA_APP_PF, APP_PF_BAR0);
|
||||
fail_on(rc, out, "peek-poke example failed");
|
||||
|
||||
printf("Developers are encouraged to modify the Virtual DIP Switch by calling the linux shell command to demonstrate how AWS FPGA Virtual DIP switches can be used to change a CustomLogic functionality:\n");
|
||||
printf("$ fpga-set-virtual-dip-switch -S (slot-id) -D (16 digit setting)\n\n");
|
||||
printf("In this example, setting a virtual DIP switch to zero clears the corresponding LED, even if the peek-poke example would set it to 1.\nFor instance:\n");
|
||||
|
||||
printf(
|
||||
"# sudo fpga-set-virtual-dip-switch -S 0 -D 1111111111111111\n"
|
||||
"# sudo fpga-get-virtual-led -S 0\n"
|
||||
"FPGA slot id 0 have the following Virtual LED:\n"
|
||||
"1010-1101-1101-1110\n"
|
||||
"# sudo fpga-set-virtual-dip-switch -S 0 -D 0000000000000000\n"
|
||||
"# sudo fpga-get-virtual-led -S 0\n"
|
||||
"FPGA slot id 0 have the following Virtual LED:\n"
|
||||
"0000-0000-0000-0000\n"
|
||||
);
|
||||
|
||||
#ifndef SV_TEST
|
||||
return rc;
|
||||
|
||||
out:
|
||||
return 1;
|
||||
#else
|
||||
|
||||
out:
|
||||
#ifdef INT_MAIN
|
||||
*exit_code = 0;
|
||||
return 0;
|
||||
#else
|
||||
*exit_code = 0;
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
/* As HW simulation test is not run on a AFI, the below function is not valid */
|
||||
#ifndef SV_TEST
|
||||
|
||||
int check_afi_ready(int slot_id) {
|
||||
struct fpga_mgmt_image_info info = {0};
|
||||
int rc;
|
||||
|
||||
/* get local image description, contains status, vendor id, and device id. */
|
||||
rc = fpga_mgmt_describe_local_image(slot_id, &info,0);
|
||||
fail_on(rc, out, "Unable to get AFI information from slot %d. Are you running as root?",slot_id);
|
||||
|
||||
/* check to see if the slot is ready */
|
||||
if (info.status != FPGA_STATUS_LOADED) {
|
||||
rc = 1;
|
||||
fail_on(rc, out, "AFI in Slot %d is not in READY state !", slot_id);
|
||||
}
|
||||
|
||||
printf("AFI PCI Vendor ID: 0x%x, Device ID 0x%x\n",
|
||||
info.spec.map[FPGA_APP_PF].vendor_id,
|
||||
info.spec.map[FPGA_APP_PF].device_id);
|
||||
|
||||
/* confirm that the AFI that we expect is in fact loaded */
|
||||
if (info.spec.map[FPGA_APP_PF].vendor_id != pci_vendor_id ||
|
||||
info.spec.map[FPGA_APP_PF].device_id != pci_device_id) {
|
||||
printf("AFI does not show expected PCI vendor id and device ID. If the AFI "
|
||||
"was just loaded, it might need a rescan. Rescanning now.\n");
|
||||
|
||||
rc = fpga_pci_rescan_slot_app_pfs(slot_id);
|
||||
fail_on(rc, out, "Unable to update PF for slot %d",slot_id);
|
||||
/* get local image description, contains status, vendor id, and device id. */
|
||||
rc = fpga_mgmt_describe_local_image(slot_id, &info,0);
|
||||
fail_on(rc, out, "Unable to get AFI information from slot %d",slot_id);
|
||||
|
||||
printf("AFI PCI Vendor ID: 0x%x, Device ID 0x%x\n",
|
||||
info.spec.map[FPGA_APP_PF].vendor_id,
|
||||
info.spec.map[FPGA_APP_PF].device_id);
|
||||
|
||||
/* confirm that the AFI that we expect is in fact loaded after rescan */
|
||||
if (info.spec.map[FPGA_APP_PF].vendor_id != pci_vendor_id ||
|
||||
info.spec.map[FPGA_APP_PF].device_id != pci_device_id) {
|
||||
rc = 1;
|
||||
fail_on(rc, out, "The PCI vendor id and device of the loaded AFI are not "
|
||||
"the expected values.");
|
||||
}
|
||||
}
|
||||
|
||||
return rc;
|
||||
out:
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* An example to attach to an arbitrary slot, pf, and bar with register access.
|
||||
*/
|
||||
int peek_poke_example(uint32_t value, int slot_id, int pf_id, int bar_id) {
|
||||
int rc;
|
||||
/* pci_bar_handle_t is a handler for an address space exposed by one PCI BAR on one of the PCI PFs of the FPGA */
|
||||
|
||||
pci_bar_handle_t pci_bar_handle = PCI_BAR_HANDLE_INIT;
|
||||
|
||||
|
||||
/* attach to the fpga, with a pci_bar_handle out param
|
||||
* To attach to multiple slots or BARs, call this function multiple times,
|
||||
* saving the pci_bar_handle to specify which address space to interact with in
|
||||
* other API calls.
|
||||
* This function accepts the slot_id, physical function, and bar number
|
||||
*/
|
||||
#ifndef SV_TEST
|
||||
rc = fpga_pci_attach(slot_id, pf_id, bar_id, 0, &pci_bar_handle);
|
||||
fail_on(rc, out, "Unable to attach to the AFI on slot id %d", slot_id);
|
||||
#endif
|
||||
|
||||
/* write a value into the mapped address space */
|
||||
uint32_t expected = byte_swap(value);
|
||||
printf("Writing 0x%08x to HELLO_WORLD register (0x%016lx)\n", value, HELLO_WORLD_REG_ADDR);
|
||||
rc = fpga_pci_poke(pci_bar_handle, HELLO_WORLD_REG_ADDR, value);
|
||||
|
||||
fail_on(rc, out, "Unable to write to the fpga !");
|
||||
|
||||
/* read it back and print it out; you should expect the byte order to be
|
||||
* reversed (That's what this CL does) */
|
||||
rc = fpga_pci_peek(pci_bar_handle, HELLO_WORLD_REG_ADDR, &value);
|
||||
fail_on(rc, out, "Unable to read read from the fpga !");
|
||||
printf("===== Entering peek_poke_example =====\n");
|
||||
printf("register: 0x%x\n", value);
|
||||
if(value == expected) {
|
||||
printf("TEST PASSED");
|
||||
printf("Resulting value matched expected value 0x%x. It worked!\n", expected);
|
||||
}
|
||||
else{
|
||||
printf("TEST FAILED");
|
||||
printf("Resulting value did not match expected value 0x%x. Something didn't work.\n", expected);
|
||||
}
|
||||
out:
|
||||
/* clean up */
|
||||
if (pci_bar_handle >= 0) {
|
||||
rc = fpga_pci_detach(pci_bar_handle);
|
||||
if (rc) {
|
||||
printf("Failure while detaching from the fpga.\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* if there is an error code, exit with status 1 */
|
||||
return (rc != 0 ? 1 : 0);
|
||||
}
|
||||
|
||||
#ifdef SV_TEST
|
||||
/*This function is used transfer string buffer from SV to C.
|
||||
This function currently returns 0 but can be used to update a buffer on the 'C' side.*/
|
||||
int send_rdbuf_to_c(char* rd_buf)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
# Amazon FPGA Hardware Development Kit
|
||||
#
|
||||
# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
#
|
||||
# Licensed under the Amazon Software License (the "License"). You may not use
|
||||
# this file except in compliance with the License. A copy of the License is
|
||||
# located at
|
||||
#
|
||||
# http://aws.amazon.com/asl/
|
||||
#
|
||||
# or in the "license" file accompanying this file. This file is distributed on
|
||||
# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
# implied. See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
|
||||
VPATH = src:include:$(HDK_DIR)/common/software/src:$(HDK_DIR)/common/software/include
|
||||
|
||||
C_SRCS := test_hello_world.c pcie_utils.c cl_utils.c main.c
|
||||
C_OBJS := $(C_SRCS:.c=.o)
|
||||
|
||||
CC = gcc
|
||||
CFLAGS = -I ./include
|
||||
CFLAGS += -I $(HDK_DIR)/common/software/include
|
||||
all: test_hello_world
|
||||
|
||||
test_hello_world: $(C_SRCS)
|
||||
$(CC) $(CFLAGS) -o $@ $^
|
||||
|
||||
clean:
|
||||
rm test_hello_world
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
// Amazon FPGA Hardware Development Kit
|
||||
//
|
||||
// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
//
|
||||
// Licensed under the Amazon Software License (the "License"). You may not use
|
||||
// this file except in compliance with the License. A copy of the License is
|
||||
// located at
|
||||
//
|
||||
// http://aws.amazon.com/asl/
|
||||
//
|
||||
// or in the "license" file accompanying this file. This file is distributed on
|
||||
// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
// implied. See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef SH_DPI_TASKS
|
||||
#define SH_DPI_TASKS
|
||||
|
||||
#include <stdarg.h>
|
||||
|
||||
extern void sv_printf(char *msg);
|
||||
extern void sv_map_host_memory(uint8_t *memory);
|
||||
|
||||
extern void cl_peek(uint64_t addr, uint32_t *data);
|
||||
extern void cl_poke(uint64_t addr, uint32_t data);
|
||||
extern void sv_int_ack(uint32_t int_num);
|
||||
extern void sv_pause(uint32_t x);
|
||||
|
||||
void test_main(uint32_t *exit_code);
|
||||
|
||||
void host_memory_putc(uint64_t addr, uint8_t data)
|
||||
{
|
||||
*(uint8_t *)addr = data;
|
||||
}
|
||||
|
||||
//void host_memory_getc(uint64_t addr, uint8_t *data)
|
||||
uint8_t host_memory_getc(uint64_t addr)
|
||||
{
|
||||
return *(uint8_t *)addr;
|
||||
}
|
||||
|
||||
void log_printf(const char *format, ...)
|
||||
{
|
||||
static char sv_msg_buffer[256];
|
||||
va_list args;
|
||||
|
||||
va_start(args, format);
|
||||
vsprintf(sv_msg_buffer, format, args);
|
||||
sv_printf(sv_msg_buffer);
|
||||
|
||||
va_end(args);
|
||||
}
|
||||
|
||||
void int_handler(uint32_t int_num)
|
||||
{
|
||||
// Vivado does not support svGetScopeFromName
|
||||
#ifndef VIVADO_SIM
|
||||
svScope scope;
|
||||
scope = svGetScopeFromName("tb");
|
||||
svSetScope(scope);
|
||||
#endif
|
||||
|
||||
log_printf("Received interrupt %2d", int_num);
|
||||
sv_int_ack(int_num);
|
||||
}
|
||||
|
||||
#define LOW_32b(a) ((uint32_t)((uint64_t)(a) & 0xffffffff))
|
||||
#define HIGH_32b(a) ((uint32_t)(((uint64_t)(a)) >> 32L))
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
// Amazon FPGA Hardware Development Kit
|
||||
//
|
||||
// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
//
|
||||
// Licensed under the Amazon Software License (the "License"). You may not use
|
||||
// this file except in compliance with the License. A copy of the License is
|
||||
// located at
|
||||
//
|
||||
// http://aws.amazon.com/asl/
|
||||
//
|
||||
// or in the "license" file accompanying this file. This file is distributed on
|
||||
// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
// implied. See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
|
||||
// Vivado does not support svGetScopeFromName
|
||||
//#ifdef INCLUDE_DPI_CALLS
|
||||
#ifndef VIVADO_SIM
|
||||
#include "svdpi.h"
|
||||
#endif
|
||||
//#endif
|
||||
|
||||
#include "sh_dpi_tasks.h"
|
||||
|
||||
#define HELLO_WORLD_REG_ADDR UINT64_C(0x500)
|
||||
|
||||
void test_main(uint32_t *exit_code) {
|
||||
|
||||
// Vivado does not support svGetScopeFromName
|
||||
//#ifdef INCLUDE_DPI_CALLS
|
||||
#ifndef VIVADO_SIM
|
||||
svScope scope;
|
||||
#endif
|
||||
//#endif
|
||||
|
||||
uint32_t rdata;
|
||||
|
||||
// Vivado does not support svGetScopeFromName
|
||||
//#ifdef INCLUDE_DPI_CALLS
|
||||
#ifndef VIVADO_SIM
|
||||
scope = svGetScopeFromName("tb");
|
||||
svSetScope(scope);
|
||||
#endif
|
||||
//#endif
|
||||
|
||||
log_printf("Writing 0xDEAD_BEEF to address 0x%x", HELLO_WORLD_REG_ADDR);
|
||||
cl_poke(HELLO_WORLD_REG_ADDR, 0xDEADBEEF);
|
||||
cl_peek(HELLO_WORLD_REG_ADDR, &rdata);
|
||||
|
||||
log_printf("Reading 0x%x from address 0x%x", rdata, HELLO_WORLD_REG_ADDR);
|
||||
|
||||
if (rdata == 0xEFBEADDE) {
|
||||
log_printf("Test PASSED");
|
||||
} else {
|
||||
log_printf("Test FAILED");
|
||||
}
|
||||
|
||||
*exit_code = 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
// Amazon FPGA Hardware Development Kit
|
||||
//
|
||||
// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
//
|
||||
// Licensed under the Amazon Software License (the "License"). You may not use
|
||||
// this file except in compliance with the License. A copy of the License is
|
||||
// located at
|
||||
//
|
||||
// http://aws.amazon.com/asl/
|
||||
//
|
||||
// or in the "license" file accompanying this file. This file is distributed on
|
||||
// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
// implied. See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
|
||||
// Vivado does not support svGetScopeFromName
|
||||
#ifdef INCLUDE_DPI_CALLS
|
||||
#ifndef VIVADO_SIM
|
||||
#include "svdpi.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#include "sh_dpi_tasks.h"
|
||||
|
||||
void test_main(uint32_t *exit_code) {
|
||||
|
||||
// NULL Test
|
||||
|
||||
*exit_code = 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
This readme provides information about the simulation environment for the cl_hello_world example. For more details about overall HDK simulation environment and CL bringup in simulation please refer to [RTL_Simulating_CL_Designs](../../../../docs/RTL_Simulating_CL_Designs.md)
|
||||
|
||||
# Hello World CL Example Simulation
|
||||
|
||||
The test can be run from the [verif/scripts](scripts) directory with all supported simulators:
|
||||
|
||||
```
|
||||
$ make TEST=test_hello_world (Runs with XSIM by default)
|
||||
$ make TEST=test_hello_world IES=1
|
||||
$ make TEST=test_hello_world VCS=1
|
||||
$ make TEST=test_hello_world QUESTA=1
|
||||
```
|
||||
|
||||
The HW/SW co-simulation test can be run from the [verif/scripts](scripts) directory with all supported simulators:
|
||||
|
||||
```
|
||||
$ make C_TEST=test_hello_world (Runs with XSIM by default)
|
||||
$ make C_TEST=test_hello_world VCS=1
|
||||
$ make C_TEST=test_hello_world QUESTA=1
|
||||
$ make C_TEST=test_hello_world IES=1
|
||||
```
|
||||
|
||||
Note that the appropriate simulators must be installed.
|
||||
|
||||
# Dump Waves
|
||||
|
||||
For information about how to dump waves with XSIM, please refer to the section [debugging-custom-logic-using-the-aws-hdk](../../../../docs/RTL_Simulating_CL_Designs.md#debugging-custom-logic-using-the-aws-hdk)
|
||||
|
||||
# System Verliog Tests
|
||||
|
||||
The system verilog tests can be found at [verif/tests](tests). Below is the information about each test.
|
||||
|
||||
## test_gl_cntr.sv
|
||||
|
||||
Global counter test. Test programs and checks different global counter values.
|
||||
|
||||
## test_hello_world.sv
|
||||
|
||||
A basic test that exercises the Hello World Register as well as the Virtual LED Register. It also includes a test that programs global counter in shell model. The test writes a value to the Hello World Register and then reads it back. Additionally, it reads the Virtual LED register.
|
||||
|
||||
## test_null.sv
|
||||
|
||||
test_null is not a test. This is a system verilog module needed for HW/SW co-simulation.
|
||||
|
||||
# HW/SW co-simulation Test
|
||||
|
||||
The software test with HW/SW co-simulation support [test_hello_world.c](../software/runtime/test_hello_world.c) can be found at [software/runtime](../software/runtime). For Information about how HW/SW co-simulation support can be added to a software test please refer to "Code changes to enable HW/SW co-simulation" section in [RTL_Simulating_CL_Designs](../../../../docs/RTL_Simulating_CL_Designs.md).
|
||||
|
||||
# Using IPI to run simulations in cl_hello_world example
|
||||
|
||||
Xilinx IPI can also be used to simulate cl_hello_world. For information about how to use IPI to simulate cl_hello_world example, please refer to [IPI_GUI_cl_hello_world_example](../../cl_hello_world_hlx/README.md)
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
# Amazon FPGA Hardware Development Kit
|
||||
#
|
||||
# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
#
|
||||
# Licensed under the Amazon Software License (the "License"). You may not use
|
||||
# this file except in compliance with the License. A copy of the License is
|
||||
# located at
|
||||
#
|
||||
# http://aws.amazon.com/asl/
|
||||
#
|
||||
# or in the "license" file accompanying this file. This file is distributed on
|
||||
# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
# implied. See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
ifndef VIVADO_TOOL_VERSION
|
||||
$(error Environment variable VIVADO_TOOL_VERSION not set. please source hdk_setup.sh)
|
||||
else
|
||||
$(info VIVADO_TOOL_VERSION = $(VIVADO_TOOL_VERSION))
|
||||
endif
|
||||
|
||||
export TEST ?= test_null
|
||||
export C_TEST ?= test_null
|
||||
|
||||
export CL_ROOT = $(PWD)/../..
|
||||
export SDK_DIR = $(AWS_FPGA_REPO_DIR)/sdk
|
||||
|
||||
export C_COMMON_DIR = $(HDK_COMMON_DIR)/software
|
||||
export C_SDK_USR_INC_DIR = $(SDK_DIR)/userspace/include
|
||||
export C_SDK_USR_UTILS_DIR = $(SDK_DIR)/userspace/utils
|
||||
export C_INC_DIR = $(CL_ROOT)/software/runtime
|
||||
export C_SRC_DIR = $(CL_ROOT)/software/runtime
|
||||
|
||||
export TEST_NAME = $(CL_ROOT)/verif/tests/$(TEST).sv
|
||||
|
||||
ifeq ($(C_TEST),test_null)
|
||||
export C_TEST_NAME = $(HDK_COMMON_DIR)/software/src/$(C_TEST).c
|
||||
else
|
||||
export C_TEST_NAME = $(C_SRC_DIR)/$(C_TEST).c
|
||||
endif
|
||||
|
||||
export SIM_ROOT = $(CL_ROOT)/verif/sim/$(SIMULATOR)
|
||||
|
||||
ifeq ($(C_TEST),test_null)
|
||||
export SIM_DIR = $(SIM_ROOT)/$(TEST)
|
||||
else
|
||||
export SIM_DIR = $(SIM_ROOT)/$(C_TEST)_c
|
||||
endif
|
||||
|
||||
|
||||
export SCRIPTS_DIR = $(PWD)
|
||||
export XILINX_IP = $(HDK_SHELL_DESIGN_DIR)/ip
|
||||
export SH_LIB_DIR = $(HDK_SHELL_DESIGN_DIR)/lib
|
||||
export SH_INF_DIR = $(HDK_SHELL_DESIGN_DIR)/interfaces
|
||||
export SH_SH_DIR = $(HDK_SHELL_DESIGN_DIR)/sh_ddr/sim
|
||||
|
||||
SV_TEST_LIST = test_hello_world
|
||||
C_FILES = $(C_TEST_NAME) $(C_SDK_USR_UTILS_DIR)/sh_dpi_tasks.c $(C_COMMON_DIR)/src/fpga_pci_sv.c
|
||||
|
||||
ifeq ($(XCHK), 1)
|
||||
all: make_sim_dir compile_chk run
|
||||
else
|
||||
all: make_sim_dir compile run
|
||||
endif
|
||||
comp: make_sim_dir compile
|
||||
|
||||
include $(HDK_COMMON_DIR)/verif/tb/scripts/Makefile.common.inc
|
||||
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
# Amazon FPGA Hardware Development Kit
|
||||
#
|
||||
# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
#
|
||||
# Licensed under the Amazon Software License (the "License"). You may not use
|
||||
# this file except in compliance with the License. A copy of the License is
|
||||
# located at
|
||||
#
|
||||
# http://aws.amazon.com/asl/
|
||||
#
|
||||
# or in the "license" file accompanying this file. This file is distributed on
|
||||
# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
# implied. See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
|
||||
##################################################################
|
||||
## Makefile For IES compiles and simulations
|
||||
## Step to run :
|
||||
## 1. make create_libs IES=1 -> To generate xilinx compile
|
||||
## libraries. This is a one time step
|
||||
## 2. make all IES=1 -> Runs the test
|
||||
##################################################################
|
||||
|
||||
compile: $(COMPLIB_DIR)
|
||||
mkdir -p $(SIM_DIR)
|
||||
cd $(SIM_DIR) && ln -s -f ../ies_complib/cds.lib
|
||||
cd $(SIM_DIR) && ln -s -f ../ies_complib/hdl.var
|
||||
cd $(SIM_DIR) && gcc -fPIC -g -shared -I$(C_SDK_USR_INC_DIR) -I$(C_SDK_USR_UTILS_DIR) -I$(C_COMMON_DIR)/include -I$(C_COMMON_DIR)/src -I$(C_INC_DIR) -DSV_TEST -DSCOPE -DIES_SIM -DINT_MAIN -o libdpi.so $(C_FILES) -I/`ncroot`/tools/include
|
||||
cd $(SIM_DIR) && irun -64bit -elaborate +libext+.v+.sv -disable_sem2009 -l compile.ies.log -I$(C_SDK_USR_INC_DIR) -I$(C_SDK_USR_UTILS_DIR) -I$(C_COMMON_DIR) -define SV_TEST -define SCOPE -define IES_SIM -define NO_DMA -I$(C_INC_DIR) -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f -top tb -top glbl -top $(TEST) -define SV_TEST -define SCOPE -define IES_SIM $(DEFINES) $(DEFINES) $(TEST_NAME) -timescale 1ps/1ps
|
||||
|
||||
run:
|
||||
|
||||
ifeq ($(TEST),test_null)
|
||||
cd $(SIM_DIR) && irun -R -access +rwc -timescale 1ps/1ps -l $(C_TEST).log $(PLUSARGS) +vpdfile+$(TEST).vpd
|
||||
else
|
||||
cd $(SIM_DIR) && irun -R -access +rwc -timescale 1ps/1ps -l $(TEST).log $(PLUSARGS) +vpdfile+$(TEST).vpd
|
||||
endif
|
||||
|
||||
$(COMPLIB_DIR):
|
||||
cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl
|
||||
cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl
|
||||
cd $(SIM_ROOT) && rm -rf create_libs.tcl
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
# Amazon FPGA Hardware Development Kit
|
||||
#
|
||||
# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
#
|
||||
# Licensed under the Amazon Software License (the "License"). You may not use
|
||||
# this file except in compliance with the License. A copy of the License is
|
||||
# located at
|
||||
#
|
||||
# http://aws.amazon.com/asl/
|
||||
#
|
||||
# or in the "license" file accompanying this file. This file is distributed on
|
||||
# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
# implied. See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
|
||||
##################################################################
|
||||
## Makefile For Questa compiles and simulations
|
||||
## Step to run :
|
||||
## 1. make create_libs QUESTA=1 -> To generate xilinx compile
|
||||
## libraries. This is a one time step
|
||||
## 2. make all QUESTA=1 -> Runs the test
|
||||
##################################################################
|
||||
|
||||
compile: $(COMPLIB_DIR)
|
||||
mkdir -p $(SIM_DIR)
|
||||
cd ${SIM_DIR} && ln -s -f ../questa_complib/modelsim.ini
|
||||
cd $(SIM_DIR) && vlog $(C_FILES) -ccflags "-I$(C_SDK_USR_INC_DIR)" -ccflags "-I$(C_SDK_USR_UTILS_DIR)" -ccflags "-I$(C_COMMON_DIR)/include" -ccflags "-I$(C_COMMON_DIR)/src" -ccflags "-DSV_TEST" -ccflags "-DSCOPE" -ccflags "-DQUESTA_SIM" -ccflags "-DINT_MAIN" -ccflags "-I$(C_INC_DIR)"
|
||||
cd $(SIM_DIR) && vlog -mfcu -sv -64 -timescale 1ps/1ps -93 -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/secureip -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f
|
||||
|
||||
run:
|
||||
ifeq ($(VIVADO_TOOL_VERSION), v2017.4)
|
||||
ifeq ($(TEST),test_null)
|
||||
cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_15 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_16 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_14 -L $(COMPLIB_DIR)/fifo_generator_v13_2_1 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_14 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(C_TEST).log -do "run -all; quit -f" tb glbl $(TEST)
|
||||
else
|
||||
cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_15 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_16 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_14 -L $(COMPLIB_DIR)/fifo_generator_v13_2_1 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_14 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(TEST).log -do "run -all; quit -f" tb glbl $(TEST)
|
||||
endif
|
||||
else ifeq ($(VIVADO_TOOL_VERSION), v2018.3)
|
||||
ifeq ($(TEST),test_null)
|
||||
cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_18 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_19 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_17 -L $(COMPLIB_DIR)/fifo_generator_v13_2_3 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_17 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(C_TEST).log -do "run -all; quit -f" tb glbl $(TEST)
|
||||
else
|
||||
cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_18 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_19 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_17 -L $(COMPLIB_DIR)/fifo_generator_v13_2_3 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_17 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(TEST).log -do "run -all; quit -f" tb glbl $(TEST)
|
||||
endif
|
||||
else
|
||||
ifeq ($(TEST),test_null)
|
||||
cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_17 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_18 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_16 -L $(COMPLIB_DIR)/fifo_generator_v13_2_2 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_16 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(C_TEST).log -do "run -all; quit -f" tb glbl $(TEST)
|
||||
else
|
||||
cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_17 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_18 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_16 -L $(COMPLIB_DIR)/fifo_generator_v13_2_2 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_16 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(TEST).log -do "run -all; quit -f" tb glbl $(TEST)
|
||||
endif
|
||||
endif
|
||||
|
||||
$(COMPLIB_DIR):
|
||||
cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl
|
||||
cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl
|
||||
cd $(SIM_ROOT) && rm -rf create_libs.tcl
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
# Amazon FPGA Hardware Development Kit
|
||||
#
|
||||
# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
#
|
||||
# Licensed under the Amazon Software License (the "License"). You may not use
|
||||
# this file except in compliance with the License. A copy of the License is
|
||||
# located at
|
||||
#
|
||||
# http://aws.amazon.com/asl/
|
||||
#
|
||||
# or in the "license" file accompanying this file. This file is distributed on
|
||||
# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
# implied. See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
|
||||
##################################################################
|
||||
## Makefile For VCS compiles and simulations
|
||||
## Step to run :
|
||||
## 1. make create_libs VCS=1 -> To generate xilinx compile
|
||||
## libraries. This is a one time step
|
||||
## 2. make all VCS=1 -> Runs the test
|
||||
##################################################################
|
||||
|
||||
compile: $(COMPLIB_DIR)
|
||||
mkdir -p $(SIM_DIR)
|
||||
cd ${SIM_DIR} && ln -s -f ../vcs_complib/synopsys_sim.setup
|
||||
cd $(SIM_DIR) && vlogan -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -lca -v2005 +v2k -l compile.vlogan.log -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS $(DEFINES) +lint=TFIPC-L
|
||||
cd $(SIM_DIR) && vcs tb $(TEST) $(C_FILES) -CFLAGS "-I$(C_SDK_USR_INC_DIR)" -CFLAGS "-I$(C_SDK_USR_UTILS_DIR)" -CFLAGS "-I$(C_COMMON_DIR)/include" -CFLAGS "-I$(C_COMMON_DIR)/src" -CFLAGS "-DSV_TEST" -CFLAGS "-DSCOPE" -CFLAGS "-I$(C_INC_DIR)" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log
|
||||
|
||||
run:
|
||||
|
||||
ifeq ($(TEST),test_null)
|
||||
cd $(SIM_DIR) && ./simv -l $(C_TEST).log $(PLUSARGS) +ntb_random_seed_automatic +vpdfile+$(TEST).vpd
|
||||
else
|
||||
cd $(SIM_DIR) && ./simv -l $(TEST).log $(PLUSARGS) +ntb_random_seed_automatic +vpdfile+$(TEST).vpd
|
||||
endif
|
||||
|
||||
$(COMPLIB_DIR):
|
||||
cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl
|
||||
cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl
|
||||
cd $(SIM_ROOT) && rm -rf create_libs.tcl
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
# Amazon FPGA Hardware Development Kit
|
||||
#
|
||||
# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
#
|
||||
# Licensed under the Amazon Software License (the "License"). You may not use
|
||||
# this file except in compliance with the License. A copy of the License is
|
||||
# located at
|
||||
#
|
||||
# http://aws.amazon.com/asl/
|
||||
#
|
||||
# or in the "license" file accompanying this file. This file is distributed on
|
||||
# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
# implied. See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
##################################################################
|
||||
## Makefile For Vivado compiles and simulations
|
||||
##################################################################
|
||||
|
||||
compile:
|
||||
mkdir -p $(SIM_DIR)
|
||||
cd $(SIM_DIR) && xsc $(C_FILES) --additional_option "-I$(C_SDK_USR_INC_DIR)" --additional_option "-I$(C_SDK_USR_UTILS_DIR)" --additional_option "-I$(C_COMMON_DIR)/include" --additional_option "-I$(C_COMMON_DIR)/src" --additional_option "-I$(C_INC_DIR)" --additional_option "-DVIVADO_SIM" --additional_option "-DSV_TEST"
|
||||
cd $(SIM_DIR) && xvlog --sv -m64 --initfile $(XILINX_VIVADO)/data/xsim/ip/xsim_ip.ini --work xil_defaultlib --relax -f $(SCRIPTS_DIR)/top.vivado.f
|
||||
cd $(SIM_DIR) && xvhdl -m64 --initfile $(XILINX_VIVADO)/data/xsim/ip/xsim_ip.ini --work xil_defaultlib --relax -f $(SCRIPTS_DIR)/top_vhdl.vivado.f
|
||||
cd $(SIM_DIR) && xelab -m64 --initfile $(XILINX_VIVADO)/data/xsim/ip/xsim_ip.ini --timescale 1ps/1ps --debug typical --relax --mt 8 -L axi_clock_converter_v2_1_11 -L generic_baseblocks_v2_1_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_15 -L axi_register_slice_v2_1_12 -L fifo_generator_v13_2_1 -L fifo_generator_v13_1_4 -L axi_data_fifo_v2_1_11 -L axi_crossbar_v2_1_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -sv_lib dpi --snapshot tb xil_defaultlib.tb xil_defaultlib.glbl xil_defaultlib.$(TEST)
|
||||
|
||||
compile_chk:
|
||||
mkdir -p $(SIM_DIR)
|
||||
cd $(SIM_DIR) && xsc $(C_FILES) --additional_option "-I$(C_SDK_USR_INC_DIR)" --additional_option "-I$(C_SDK_USR_UTILS_DIR)" --additional_option "-I$(C_COMMON_DIR)/include" --additional_option "-I$(C_COMMON_DIR)/src" --additional_option "-I$(C_INC_DIR)" --additional_option "-DVIVADO_SIM" --additional_option "-DSV_TEST"
|
||||
cd $(SIM_DIR) && xvlog --sv -m64 -d ENABLE_PROTOCOL_CHK --initfile $(XILINX_VIVADO)/data/xsim/ip/xsim_ip.ini --work xil_defaultlib --relax -f $(SCRIPTS_DIR)/top.vivado.f
|
||||
cd $(SIM_DIR) && xelab -m64 -d ENABLE_PROTOCOL_CHK --initfile $(XILINX_VIVADO)/data/xsim/ip/xsim_ip.ini --timescale 1ps/1ps --debug typical --relax --mt 8 -L axi_protocol_checker_v1_1_12 -L axi_clock_converter_v2_1_11 -L generic_baseblocks_v2_1_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_12 -L fifo_generator_v13_1_4 -L axi_data_fifo_v2_1_11 -L axi_crossbar_v2_1_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -sv_lib dpi --snapshot tb xil_defaultlib.tb xil_defaultlib.glbl xil_defaultlib.$(TEST)
|
||||
|
||||
run:
|
||||
|
||||
ifeq ($(TEST),test_null)
|
||||
cd $(SIM_DIR) && xsim -R -log $(C_TEST).log -tclbatch $(SCRIPTS_DIR)/waves.tcl tb
|
||||
else
|
||||
cd $(SIM_DIR) && xsim -R -log $(TEST).log -tclbatch $(SCRIPTS_DIR)/waves.tcl tb
|
||||
endif
|
||||
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
# Amazon FPGA Hardware Development Kit
|
||||
#
|
||||
# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
#
|
||||
# Licensed under the Amazon Software License (the "License"). You may not use
|
||||
# this file except in compliance with the License. A copy of the License is
|
||||
# located at
|
||||
#
|
||||
# http://aws.amazon.com/asl/
|
||||
#
|
||||
# or in the "license" file accompanying this file. This file is distributed on
|
||||
# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
# implied. See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
+define+VCS_SIM
|
||||
+define+CARD_1=card
|
||||
+libext+.v
|
||||
+libext+.sv
|
||||
+libext+.svh
|
||||
|
||||
-y ${CL_ROOT}/../common/design
|
||||
-y ${CL_ROOT}/design
|
||||
-y ${CL_ROOT}/verif/sv
|
||||
-y ${SH_LIB_DIR}
|
||||
-y ${SH_INF_DIR}
|
||||
-y ${SH_SH_DIR}
|
||||
-y ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/hdl
|
||||
-y ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/sim
|
||||
|
||||
+incdir+${CL_ROOT}/../common/design
|
||||
+incdir+${CL_ROOT}/design
|
||||
+incdir+${CL_ROOT}/verif/sv
|
||||
+incdir+${SH_LIB_DIR}
|
||||
+incdir+${SH_INF_DIR}
|
||||
+incdir+${SH_SH_DIR}
|
||||
+incdir+${HDK_COMMON_DIR}/verif/include
|
||||
+incdir+${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/sim
|
||||
+incdir+${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog
|
||||
+incdir+${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/sim
|
||||
+incdir+${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/hdl
|
||||
+incdir+${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl
|
||||
|
||||
${CL_ROOT}/../common/design/cl_common_defines.vh
|
||||
${CL_ROOT}/design/cl_hello_world_defines.vh
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/ila_vio_counter/sim/ila_vio_counter.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/ila_0/sim/ila_0.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/sim/bd_a493.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/sim/bd_a493_xsdbm_0.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/xsdbm_v3_0_vl_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/ltlib_v1_0_vl_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_1/sim/bd_a493_lut_buffer_0.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_1/hdl/lut_buffer_v2_0_vl_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/hdl/bd_a493_wrapper.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/sim/cl_debug_bridge.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/vio_0/sim/vio_0.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/sim/axi_register_slice_light.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_register_slice_v2_1_vl_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_vl_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/sim/axi_register_slice.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/simulation/fifo_generator_vlog_beh.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/fifo_generator_v13_2_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/sim/axi_clock_converter_0.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/axi_clock_converter_v2_1_vl_rfs.v
|
||||
|
||||
${CL_ROOT}/design/cl_hello_world.sv
|
||||
|
||||
-f ${HDK_COMMON_DIR}/verif/tb/filelists/tb.${SIMULATOR}.f
|
||||
|
||||
${TEST_NAME}
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
# Amazon FPGA Hardware Development Kit
|
||||
#
|
||||
# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
#
|
||||
# Licensed under the Amazon Software License (the "License"). You may not use
|
||||
# this file except in compliance with the License. A copy of the License is
|
||||
# located at
|
||||
#
|
||||
# http://aws.amazon.com/asl/
|
||||
#
|
||||
# or in the "license" file accompanying this file. This file is distributed on
|
||||
# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
# implied. See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
+define+QUESTA_SIM
|
||||
+define+CARD_1=card
|
||||
+libext+.v
|
||||
+libext+.sv
|
||||
+libext+.svh
|
||||
|
||||
-y ${CL_ROOT}/../common/design
|
||||
-y ${CL_ROOT}/design
|
||||
-y ${CL_ROOT}/verif/sv
|
||||
-y ${SH_LIB_DIR}
|
||||
-y ${SH_INF_DIR}
|
||||
-y ${SH_SH_DIR}
|
||||
-y ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/hdl
|
||||
-y ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/sim
|
||||
|
||||
+incdir+${CL_ROOT}/../common/design
|
||||
+incdir+${CL_ROOT}/design
|
||||
+incdir+${CL_ROOT}/verif/sv
|
||||
+incdir+${SH_LIB_DIR}
|
||||
+incdir+${SH_INF_DIR}
|
||||
+incdir+${SH_SH_DIR}
|
||||
+incdir+${HDK_COMMON_DIR}/verif/include
|
||||
+incdir+${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/sim
|
||||
+incdir+${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog
|
||||
+incdir+${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/sim
|
||||
+incdir+${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/hdl
|
||||
+incdir+${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl
|
||||
|
||||
${CL_ROOT}/../common/design/cl_common_defines.vh
|
||||
${CL_ROOT}/design/cl_hello_world_defines.vh
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/ila_vio_counter/sim/ila_vio_counter.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/ila_0/sim/ila_0.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/sim/bd_a493.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/sim/bd_a493_xsdbm_0.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/xsdbm_v3_0_vl_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/ltlib_v1_0_vl_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_1/sim/bd_a493_lut_buffer_0.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_1/hdl/lut_buffer_v2_0_vl_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/hdl/bd_a493_wrapper.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/sim/cl_debug_bridge.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/vio_0/sim/vio_0.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/sim/axi_register_slice_light.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_register_slice_v2_1_vl_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_vl_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/sim/axi_register_slice.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/simulation/fifo_generator_vlog_beh.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/fifo_generator_v13_2_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/sim/axi_clock_converter_0.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/axi_clock_converter_v2_1_vl_rfs.v
|
||||
|
||||
${CL_ROOT}/design/cl_hello_world.sv
|
||||
|
||||
-f ${HDK_COMMON_DIR}/verif/tb/filelists/tb.${SIMULATOR}.f
|
||||
|
||||
${TEST_NAME}
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
# Amazon FPGA Hardware Development Kit
|
||||
#
|
||||
# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
#
|
||||
# Licensed under the Amazon Software License (the "License"). You may not use
|
||||
# this file except in compliance with the License. A copy of the License is
|
||||
# located at
|
||||
#
|
||||
# http://aws.amazon.com/asl/
|
||||
#
|
||||
# or in the "license" file accompanying this file. This file is distributed on
|
||||
# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
# implied. See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
+define+VCS_SIM
|
||||
+define+CARD_1=card
|
||||
+libext+.v
|
||||
+libext+.sv
|
||||
+libext+.svh
|
||||
|
||||
-y ${CL_ROOT}/../common/design
|
||||
-y ${CL_ROOT}/design
|
||||
-y ${CL_ROOT}/verif/sv
|
||||
-y ${SH_LIB_DIR}
|
||||
-y ${SH_INF_DIR}
|
||||
-y ${SH_SH_DIR}
|
||||
-y ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/hdl
|
||||
-y ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/sim
|
||||
|
||||
+incdir+${CL_ROOT}/../common/design
|
||||
+incdir+${CL_ROOT}/design
|
||||
+incdir+${CL_ROOT}/verif/sv
|
||||
+incdir+${SH_LIB_DIR}
|
||||
+incdir+${SH_INF_DIR}
|
||||
+incdir+${SH_SH_DIR}
|
||||
+incdir+${HDK_COMMON_DIR}/verif/include
|
||||
+incdir+${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/sim
|
||||
+incdir+${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog
|
||||
+incdir+${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/hdl
|
||||
+incdir+${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl
|
||||
|
||||
${CL_ROOT}/../common/design/cl_common_defines.vh
|
||||
${CL_ROOT}/design/cl_hello_world_defines.vh
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/ila_vio_counter/sim/ila_vio_counter.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/ila_0/sim/ila_0.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/sim/bd_a493.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/sim/bd_a493_xsdbm_0.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/xsdbm_v3_0_vl_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/ltlib_v1_0_vl_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_1/sim/bd_a493_lut_buffer_0.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_1/hdl/lut_buffer_v2_0_vl_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/hdl/bd_a493_wrapper.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/sim/cl_debug_bridge.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/vio_0/sim/vio_0.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/sim/axi_register_slice_light.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_register_slice_v2_1_vl_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_vl_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/sim/axi_register_slice.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/fifo_generator_v13_2_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/axi_clock_converter_v2_1_vl_rfs.v
|
||||
${SH_LIB_DIR}/../ip/axi_clock_converter_0/sim/axi_clock_converter_0.v
|
||||
|
||||
${CL_ROOT}/design/cl_hello_world.sv
|
||||
|
||||
-f ${HDK_COMMON_DIR}/verif/tb/filelists/tb.${SIMULATOR}.f
|
||||
|
||||
${TEST_NAME}
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
# Amazon FPGA Hardware Development Kit
|
||||
#
|
||||
# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
#
|
||||
# Licensed under the Amazon Software License (the "License"). You may not use
|
||||
# this file except in compliance with the License. A copy of the License is
|
||||
# located at
|
||||
#
|
||||
# http://aws.amazon.com/asl/
|
||||
#
|
||||
# or in the "license" file accompanying this file. This file is distributed on
|
||||
# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
# implied. See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
-define VIVADO_SIM
|
||||
|
||||
-sourcelibext .v
|
||||
-sourcelibext .sv
|
||||
-sourcelibext .svh
|
||||
|
||||
-sourcelibdir ${CL_ROOT}/../common/design
|
||||
-sourcelibdir ${CL_ROOT}/design
|
||||
-sourcelibdir ${CL_ROOT}/verif/sv
|
||||
-sourcelibdir ${SH_LIB_DIR}
|
||||
-sourcelibdir ${SH_INF_DIR}
|
||||
-sourcelibdir ${SH_SH_DIR}
|
||||
|
||||
-include ${CL_ROOT}/../common/design
|
||||
-include ${CL_ROOT}/verif/sv
|
||||
-include ${SH_LIB_DIR}
|
||||
-include ${SH_INF_DIR}
|
||||
-include ${SH_SH_DIR}
|
||||
-include ${HDK_COMMON_DIR}/verif/include
|
||||
-include ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/sim
|
||||
-include ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog
|
||||
-include ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/hdl
|
||||
-include ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl
|
||||
|
||||
|
||||
${CL_ROOT}/../common/design/cl_common_defines.vh
|
||||
${CL_ROOT}/design/cl_zcash_defines.vh
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/ila_vio_counter/sim/ila_vio_counter.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/ila_0/sim/ila_0.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/sim/bd_a493.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/sim/bd_a493_xsdbm_0.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/xsdbm_v3_0_vl_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/ltlib_v1_0_vl_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_1/sim/bd_a493_lut_buffer_0.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_1/hdl/lut_buffer_v2_0_vl_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/hdl/bd_a493_wrapper.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/sim/cl_debug_bridge.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/vio_0/sim/vio_0.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/sim/axi_register_slice_light.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/sim/axi_register_slice.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_register_slice_v2_1_vl_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_vl_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/axi_clock_converter_v2_1_vl_rfs.v
|
||||
${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/fifo_generator_v13_2_rfs.v
|
||||
${SH_LIB_DIR}/../ip/axi_clock_converter_0/sim/axi_clock_converter_0.v
|
||||
${CL_ROOT}/design/cl_zcash_aws_wrapper.sv
|
||||
${CL_ROOT}/design/cl_zcash.sv
|
||||
|
||||
${CL_ROOT}/ip/axis_dwidth_converter_64_to_8/sim/axis_dwidth_converter_64_to_8.v
|
||||
${CL_ROOT}/ip/axis_dwidth_converter_64_to_8/hdl/axis_dwidth_converter_v1_1_vl_rfs.v
|
||||
${CL_ROOT}/ip/axis_dwidth_converter_64_to_8/hdl/axis_infrastructure_v1_1_0.vh
|
||||
${CL_ROOT}/ip/axis_dwidth_converter_64_to_8/hdl/axis_infrastructure_v1_1_vl_rfs.v
|
||||
${CL_ROOT}/ip/axis_dwidth_converter_64_to_8/hdl/axis_register_slice_v1_1_vl_rfs.v
|
||||
|
||||
${CL_ROOT}/ip/axis_dwidth_converter_8_to_64/sim/axis_dwidth_converter_8_to_64.v
|
||||
|
||||
${CL_ROOT}/ip/axis_dwidth_converter_48_to_8/sim/axis_dwidth_converter_48_to_8.v
|
||||
|
||||
-f ${ZCASH_DIR}/zcash_fpga/src/rtl/top/include.f
|
||||
|
||||
|
||||
-f ${HDK_COMMON_DIR}/verif/tb/filelists/tb.${SIMULATOR}.f
|
||||
|
||||
|
||||
|
||||
${TEST_NAME}
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
|
||||
${CL_ROOT}/ip/axi_fifo_mm_s_0/sim/axi_fifo_mm_s_0.vhd
|
||||
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
# Amazon FPGA Hardware Development Kit
|
||||
#
|
||||
# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
#
|
||||
# Licensed under the Amazon Software License (the "License"). You may not use
|
||||
# this file except in compliance with the License. A copy of the License is
|
||||
# located at
|
||||
#
|
||||
# http://aws.amazon.com/asl/
|
||||
#
|
||||
# or in the "license" file accompanying this file. This file is distributed on
|
||||
# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
# implied. See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
add_wave /tb/card/fpga/CL/*pcis*
|
||||
add_wave /tb/card/fpga/CL/rx_axi_lite_if/*
|
||||
add_wave /tb/card/fpga/CL/rx_axi4_if/*
|
||||
add_wave /tb/card/fpga/CL/zcash_axi_lite_if/*
|
||||
add_wave /tb/card/fpga/CL/zcash_if_tx/*
|
||||
add_wave /tb/card/fpga/CL/zcash_if_rx/*
|
||||
add_wave /tb/card/fpga/CL/cl_zcash_aws_wrapper/*
|
||||
|
||||
run 10 us
|
||||
Binary file not shown.
|
|
@ -0,0 +1,146 @@
|
|||
// Amazon FPGA Hardware Development Kit
|
||||
//
|
||||
// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
//
|
||||
// Licensed under the Amazon Software License (the "License"). You may not use
|
||||
// this file except in compliance with the License. A copy of the License is
|
||||
// located at
|
||||
//
|
||||
// http://aws.amazon.com/asl/
|
||||
//
|
||||
// or in the "license" file accompanying this file. This file is distributed on
|
||||
// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
// implied. See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
|
||||
module test_zcash();
|
||||
|
||||
import tb_type_defines_pkg::*;
|
||||
`include "cl_common_defines.vh" // CL Defines with register addresses
|
||||
|
||||
// AXI ID
|
||||
parameter [5:0] AXI_ID = 6'h0;
|
||||
|
||||
import zcash_fpga_pkg::*;
|
||||
|
||||
zcash_fpga_pkg::header_t header;
|
||||
zcash_fpga_pkg::fpga_status_rpl_t fpga_status_rpl;
|
||||
|
||||
logic [31:0] rdata;
|
||||
logic [1024*8-1:0] stream_data;
|
||||
integer stream_len;
|
||||
logic [15:0] vdip_value;
|
||||
logic [15:0] vled_value;
|
||||
|
||||
|
||||
initial begin
|
||||
|
||||
tb.power_up();
|
||||
|
||||
|
||||
read_ocl_reg(.addr(`AXI_FIFO_OFFSET), .exp_data(32'h01D00000), .rdata(rdata)); //ISR
|
||||
write_ocl_reg(.addr(`AXI_FIFO_OFFSET), .data(32'hFFFFFFFF)); // Reset ISR
|
||||
read_ocl_reg(.addr(`AXI_FIFO_OFFSET+32'hC), .exp_data(32'h000001FC), .rdata(rdata)); //TDFV
|
||||
read_ocl_reg(.addr(`AXI_FIFO_OFFSET+32'h1C), .exp_data(32'h00000000), .rdata(rdata)); //RDFO
|
||||
|
||||
write_ocl_reg(.addr(`AXI_FIFO_OFFSET+32'h4), .data(32'h0C000000)); //IER
|
||||
|
||||
// Build a status message and send it
|
||||
header.cmd = zcash_fpga_pkg::FPGA_STATUS;
|
||||
header.len = $bits(header_t)/8;
|
||||
|
||||
write_stream(.data(header), .len(header.len));
|
||||
stream_len = 0;
|
||||
fork
|
||||
begin
|
||||
while(stream_len == 0) read_stream(.data(stream_data), .len(stream_len));
|
||||
end
|
||||
begin
|
||||
while(10000) @(posedge tb.card.fpga.clk_main_a0);
|
||||
$fatal(1, "ERROR: No reply received from status_request");
|
||||
end
|
||||
join_any
|
||||
disable fork;
|
||||
|
||||
fpga_status_rpl = stream_data;
|
||||
|
||||
$display("INFO: Received status reply");
|
||||
$display("%p", fpga_status_rpl);
|
||||
$display("Version: 0x%x", fpga_status_rpl.version);
|
||||
|
||||
if (fpga_status_rpl.version != zcash_fpga_pkg::FPGA_VERSION)
|
||||
$fatal(1, "FPGA Version was wrong");
|
||||
|
||||
|
||||
$display("INFO: Test passed");
|
||||
tb.kernel_reset();
|
||||
|
||||
tb.power_down();
|
||||
|
||||
$finish;
|
||||
end
|
||||
|
||||
task read_ocl_reg(input logic [31:0] addr, output logic [31:0] rdata, input logic [31:0] exp_data = 32'hXXXXXXXX);
|
||||
|
||||
tb.peek(.addr(addr), .data(rdata), .id(AXI_ID), .intf(AxiPort::PORT_OCL));
|
||||
$display ("INFO: read_ocl_reg::Read 0x%x from address 0x%x", rdata, addr);
|
||||
if (rdata != exp_data) $fatal(1, "ERROR: AXI-FIFO ISR Register returned wrong value");
|
||||
|
||||
endtask
|
||||
|
||||
task write_ocl_reg(input logic [31:0] addr, input logic [31:0] data);
|
||||
|
||||
tb.poke(.addr(addr), .data(data), .id(AXI_ID), .intf(AxiPort::PORT_OCL));
|
||||
$display ("INFO: write_ocl_reg::Wrote 0x%x to address 0x%x", data, addr);
|
||||
|
||||
endtask
|
||||
|
||||
task write_stream(input logic [1024*8-1:0] data, input integer len);
|
||||
|
||||
logic [31:0] rdata;
|
||||
integer len_;
|
||||
len_ = len;
|
||||
read_ocl_reg(.addr(`AXI_FIFO_OFFSET+32'hC), .rdata(rdata));
|
||||
if (len > rdata) $fatal(1, "ERROR: write_pcis::AXI-FIFO does not have enough space to write %d bytes (%d free)", len, rdata);
|
||||
|
||||
while(len_ > 0) begin
|
||||
tb.poke_pcis(.addr(0), .data(data[511:0]), .strb(0));
|
||||
len_ = len_ - 512/8;
|
||||
data = data >> 512;
|
||||
end
|
||||
write_ocl_reg(.addr(`AXI_FIFO_OFFSET+32'h14), .data(len));
|
||||
|
||||
$display ("INFO: write_pcis::Wrote %d bytes of data", len);
|
||||
|
||||
// Check transmit complete bit and reset it
|
||||
read_ocl_reg(.addr(`AXI_FIFO_OFFSET), .rdata(rdata));
|
||||
if(rdata[27] == 0) $display("WARNING: write_stream transmit complete bit not set");
|
||||
write_ocl_reg(.addr(`AXI_FIFO_OFFSET), .data(32'h08000000));
|
||||
|
||||
endtask
|
||||
|
||||
task read_stream(output logic [1024*8-1:0] data, integer len);
|
||||
|
||||
logic [31:0] rdata;
|
||||
logic [511:0] pcis_data;
|
||||
len = 0;
|
||||
data = 0;
|
||||
read_ocl_reg(.addr(`AXI_FIFO_OFFSET), .rdata(rdata));
|
||||
if (rdata[26] == 0) return;
|
||||
write_ocl_reg(.addr(`AXI_FIFO_OFFSET), .data(32'h04000000)); //clear ISR
|
||||
|
||||
read_ocl_reg(.addr(`AXI_FIFO_OFFSET+ 32'h1C), .rdata(rdata)); //RDFO should be non-zero (slots used in FIFO)
|
||||
if (rdata == 0) return;
|
||||
|
||||
read_ocl_reg(.addr(`AXI_FIFO_OFFSET+ 32'h24), .rdata(rdata)); //RLR - length of packet in bytes
|
||||
while(rdata > 0) begin
|
||||
tb.peek_pcis(.addr(32'h1000), .data(pcis_data));
|
||||
data[len*8 +: 512] = pcis_data;
|
||||
len = len + rdata > (512/8) ? 512/8 : rdata/8;
|
||||
rdata = rdata < 512/8 ? 0 : rdata - 512/8;
|
||||
end
|
||||
|
||||
endtask
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue