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zcash-fpga
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Updates to help with timing

This commit is contained in:
bsdevlin 2019-04-10 14:52:11 -04:00
parent f4a2eb2fe3
commit a0769dd985
2 changed files with 11 additions and 7 deletions
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7
ip_cores/util/src/rtl/barret_mod.sv
View File

@ -44,6 +44,7 @@ module barret_mod #(
localparam MAX_IN_BITS = 2*K;
localparam [MAX_IN_BITS:0] U = (1 << (2*K)) / P;
localparam [MAX_IN_BITS-1:0] P_ = P;
logic [2:0][CTL_BITS-1:0] ctl_r;
if_axi_stream #(.DAT_BITS(2*(OUT_BITS+2))) mult_in_if(i_clk);
if_axi_stream #(.DAT_BITS(2*(OUT_BITS+2))) mult_out_if(i_clk);
@ -68,6 +69,7 @@ always_ff @ (posedge i_clk) begin
mult_in_if.reset_source();
mult_out_if.rdy <= 1;
o_ctl <= 0;
ctl_r <= 0;
end else begin
mult_out_if.rdy <= 1;
case (state)
@ -79,7 +81,7 @@ always_ff @ (posedge i_clk) begin
o_rdy <= 0;
state <= WAIT_MULT;
mult_in_if.val <= 1;
o_ctl <= i_ctl;
ctl_r[0] <= i_ctl;
mult_in_if.dat[0 +: OUT_BITS+1] <= i_dat >> (K-1);
mult_in_if.dat[OUT_BITS+1 +: OUT_BITS+1] <= U;
prev_state <= S0;
@ -89,6 +91,7 @@ always_ff @ (posedge i_clk) begin
{S0}: begin
c3 <= c2 >> (K + 1);
state <= S1;
ctl_r[1] <= ctl_r[0];
end
{S1}: begin
mult_in_if.val <= 1;
@ -96,6 +99,7 @@ always_ff @ (posedge i_clk) begin
mult_in_if.dat[OUT_BITS+1 +: OUT_BITS+1] <= P;
state <= WAIT_MULT;
prev_state <= S2;
ctl_r[2] <= ctl_r[1];
end
{S2}: begin
if (c4 >= P_) begin
@ -104,6 +108,7 @@ always_ff @ (posedge i_clk) begin
state <= FINISHED;
o_dat <= c4;
o_val <= 1;
o_ctl <= ctl_r[2];
end
end
{FINISHED}: begin

11
zcash_fpga/src/rtl/secp256k1/secp256k1_mod.sv
View File

@ -55,7 +55,7 @@ generate
c = (1 << 32) + (1 << 9) + (1 << 8) + (1 << 7) + (1 << 6) + (1 << 4) + 1;
end
always_ff @ (posedge i_clk) begin
if (~o_val || (o_val && i_rdy)) begin
if (~o_val || (i_rdy && o_val)) begin
res0 <= i_dat[511:256]*c + i_dat[255:0];
res1 <= res0[511:256]*c + res0[255:0];
end
@ -67,7 +67,7 @@ generate
res1_ = (res0[511:256] << 32) + (res0[511:256] << 9) + (res0[511:256] << 8) + (res0[511:256] << 7) + (res0[511:256] << 6) + (res0[511:256] << 4) + res0[511:256]+ res0[255:0];
end
always_ff @ (posedge i_clk) begin
if (~o_val || (o_val && i_rdy)) begin
if (~o_val || (i_rdy && o_val)) begin
res0 <= res0_;
res1 <= res1_;
end
@ -85,16 +85,15 @@ always_ff @ (posedge i_clk) begin
ctl <= 0;
o_err <= 0;
end else begin
//o_val <= 0;
if (~o_val || (o_val && i_rdy)) begin
if (~o_val || (i_rdy && o_val)) begin
val <= val << 1;
ctl <= {ctl, i_ctl};
err <= err << 1;
val[0] <= i_val && o_rdy;
err[0] <= i_err;
o_dat <= res1[255:0];
o_dat <= res1 >= p_eq ? res1 - p_eq : res1;
o_err <= err[1] || (res1 >= 2*p_eq);
o_err <= err[1] || res1 >= p_eq;
o_val <= val[1];
o_ctl <= ctl[1];
end