From aa2d2c1bba1693f7ce3f79dddaf7a44075f3aaf5 Mon Sep 17 00:00:00 2001
From: bsdevlin <bsdevlin@LAPTOP-AL12KDU7>
Date: Thu, 11 Apr 2019 10:09:24 -0400
Subject: [PATCH] Bugfix for cycle count

---
 zcash_fpga/src/rtl/secp256k1/secp256k1_top.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/zcash_fpga/src/rtl/secp256k1/secp256k1_top.sv b/zcash_fpga/src/rtl/secp256k1/secp256k1_top.sv
index 7adbeeb..cf41c7b 100644
--- a/zcash_fpga/src/rtl/secp256k1/secp256k1_top.sv
+++ b/zcash_fpga/src/rtl/secp256k1/secp256k1_top.sv
@@ -319,7 +319,7 @@ always_ff @ (posedge i_clk) begin
           end
           {3}: begin
             cnt <= $bits(verify_secp256k1_sig_rpl_t)/8;
-            msg <= verify_secp256k1_sig_rpl(secp256k1_ver, index);
+            msg <= verify_secp256k1_sig_rpl(secp256k1_ver, index, timeout);
             secp256k1_state <= FINISHED;
           end
         endcase
@@ -386,7 +386,7 @@ always_ff @ (posedge i_clk) begin
     end
     if (secp256k1_ver.TIMEOUT_FAIL && secp256k1_state != FINISHED) begin
       cnt <= $bits(verify_secp256k1_sig_rpl_t)/8;
-      msg <= verify_secp256k1_sig_rpl(secp256k1_ver, index);
+      msg <= verify_secp256k1_sig_rpl(secp256k1_ver, index, timeout);
       secp256k1_state <= FINISHED;
     end
   end