updates to testbench and using Xilinx width converter
This commit is contained in:
bsdevlin
parent
641e371e01
commit
ace41c69c1
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:vendorExtensions>
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</spirit:design>
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@ -0,0 +1,100 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>xci</spirit:library>
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<spirit:name>unknown</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:componentInstances>
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<spirit:componentInstance>
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<spirit:instanceName>axis_dwidth_converter_8_to_1</spirit:instanceName>
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||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_TKEEP" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_TLAST" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M_TDATA_NUM_BYTES" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S_TDATA_NUM_BYTES" xilinx:valueSource="user"/>
|
||||||
|
</xilinx:configElementInfos>
|
||||||
|
</xilinx:componentInstanceExtensions>
|
||||||
|
</spirit:vendorExtensions>
|
||||||
|
</spirit:componentInstance>
|
||||||
|
</spirit:componentInstances>
|
||||||
|
</spirit:design>
|
||||||
|
|
@ -32,6 +32,10 @@ module uart_wrapper #(
|
||||||
|
|
||||||
enum {UART_STARTUP, UART_LOOPBACK, UART_TX_STREAM, UART_RX_STREAM, UART_WAIT_STREAM} uart_state;
|
enum {UART_STARTUP, UART_LOOPBACK, UART_TX_STREAM, UART_RX_STREAM, UART_WAIT_STREAM} uart_state;
|
||||||
|
|
||||||
|
// Interfaces before data width conversion
|
||||||
|
if_axi_stream #(.DAT_BYTS(1), .CTL_BYTS(1)) tx_int_if (i_clk);
|
||||||
|
if_axi_stream #(.DAT_BYTS(8), .CTL_BYTS(1)) rx_int_if (i_clk);
|
||||||
|
|
||||||
logic interrupt;
|
logic interrupt;
|
||||||
logic [31:0] uart_axi_wdata, uart_axi_rdata;
|
logic [31:0] uart_axi_wdata, uart_axi_rdata;
|
||||||
logic [3:0] uart_axi_awaddr, uart_axi_araddr;
|
logic [3:0] uart_axi_awaddr, uart_axi_araddr;
|
||||||
|
|
@ -47,8 +51,8 @@ always_ff @ (posedge i_clk) begin
|
||||||
uart_axi_arvalid <= 0;
|
uart_axi_arvalid <= 0;
|
||||||
uart_axi_araddr <= 0;
|
uart_axi_araddr <= 0;
|
||||||
uart_state <= UART_STARTUP;
|
uart_state <= UART_STARTUP;
|
||||||
tx_if.reset_source();
|
tx_int_if.reset_source();
|
||||||
rx_if.rdy <= 0;
|
rx_int_if.rdy <= 0;
|
||||||
tx_byt_cnt <= 0;
|
tx_byt_cnt <= 0;
|
||||||
tx_byt_len <= 0;
|
tx_byt_len <= 0;
|
||||||
rx_byt_cnt <= 0;
|
rx_byt_cnt <= 0;
|
||||||
|
|
@ -57,7 +61,7 @@ always_ff @ (posedge i_clk) begin
|
||||||
|
|
||||||
if (uart_axi_awvalid && uart_axi_awready) uart_axi_awvalid <= 0;
|
if (uart_axi_awvalid && uart_axi_awready) uart_axi_awvalid <= 0;
|
||||||
if (uart_axi_arvalid && uart_axi_arready) uart_axi_arvalid <= 0;
|
if (uart_axi_arvalid && uart_axi_arready) uart_axi_arvalid <= 0;
|
||||||
if (tx_if.val && tx_if.rdy) tx_if.val <= 0;
|
if (tx_int_if.val && tx_int_if.rdy) tx_int_if.val <= 0;
|
||||||
|
|
||||||
case (uart_state)
|
case (uart_state)
|
||||||
UART_STARTUP: begin
|
UART_STARTUP: begin
|
||||||
|
|
@ -93,13 +97,13 @@ always_ff @ (posedge i_clk) begin
|
||||||
UART_WAIT_STREAM: begin
|
UART_WAIT_STREAM: begin
|
||||||
uart_axi_arvalid <= 1;
|
uart_axi_arvalid <= 1;
|
||||||
uart_axi_araddr <= 'h8;
|
uart_axi_araddr <= 'h8;
|
||||||
if (tx_if.val || uart_axi_awvalid) begin
|
if (tx_int_if.val || uart_axi_awvalid) begin
|
||||||
// Wait
|
// Wait
|
||||||
end else
|
end else
|
||||||
if (uart_axi_rvalid && uart_axi_rdata[0]) begin
|
if (uart_axi_rvalid && uart_axi_rdata[0]) begin
|
||||||
uart_state <= UART_RX_STREAM;
|
uart_state <= UART_RX_STREAM;
|
||||||
end else
|
end else
|
||||||
if (rx_if.val) begin
|
if (rx_int_if.val) begin
|
||||||
uart_state <= UART_TX_STREAM;
|
uart_state <= UART_TX_STREAM;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
@ -120,21 +124,21 @@ always_ff @ (posedge i_clk) begin
|
||||||
// Check for valid data byte
|
// Check for valid data byte
|
||||||
if (uart_axi_rvalid) begin
|
if (uart_axi_rvalid) begin
|
||||||
uart_axi_araddr <= 'h8;
|
uart_axi_araddr <= 'h8;
|
||||||
tx_if.dat <= uart_axi_rdata;
|
tx_int_if.dat <= uart_axi_rdata;
|
||||||
tx_if.val <= 1;
|
tx_int_if.val <= 1;
|
||||||
tx_if.sop <= 0;
|
tx_int_if.sop <= 0;
|
||||||
tx_if.eop <= 0;
|
tx_int_if.eop <= 0;
|
||||||
|
|
||||||
tx_byt_cnt <= tx_byt_cnt + 1;
|
tx_byt_cnt <= tx_byt_cnt + 1;
|
||||||
|
|
||||||
if (tx_byt_cnt == 0) begin
|
if (tx_byt_cnt == 0) begin
|
||||||
tx_byt_len[0 +: 8] <= uart_axi_rdata;
|
tx_byt_len[0 +: 8] <= uart_axi_rdata;
|
||||||
tx_if.sop <= 1;
|
tx_int_if.sop <= 1;
|
||||||
end else
|
end else
|
||||||
if (tx_byt_cnt == 1) begin
|
if (tx_byt_cnt == 1) begin
|
||||||
tx_byt_len[8 +: 8] <= uart_axi_rdata;
|
tx_byt_len[8 +: 8] <= uart_axi_rdata;
|
||||||
if (tx_byt_len[0 +: 8] <= 2 && uart_axi_rdata == 0) begin
|
if (tx_byt_len[0 +: 8] <= 2 && uart_axi_rdata == 0) begin
|
||||||
tx_if.eop <= 1;
|
tx_int_if.eop <= 1;
|
||||||
tx_byt_cnt <= 0;
|
tx_byt_cnt <= 0;
|
||||||
tx_byt_len <= 0;
|
tx_byt_len <= 0;
|
||||||
uart_state <= UART_WAIT_STREAM;
|
uart_state <= UART_WAIT_STREAM;
|
||||||
|
|
@ -142,7 +146,7 @@ always_ff @ (posedge i_clk) begin
|
||||||
end else begin
|
end else begin
|
||||||
// If we hit our length
|
// If we hit our length
|
||||||
if (tx_byt_cnt + 1 >= tx_byt_len) begin
|
if (tx_byt_cnt + 1 >= tx_byt_len) begin
|
||||||
tx_if.eop <= 1;
|
tx_int_if.eop <= 1;
|
||||||
tx_byt_cnt <= 0;
|
tx_byt_cnt <= 0;
|
||||||
tx_byt_len <= 0;
|
tx_byt_len <= 0;
|
||||||
uart_state <= UART_WAIT_STREAM;
|
uart_state <= UART_WAIT_STREAM;
|
||||||
|
|
@ -155,21 +159,21 @@ always_ff @ (posedge i_clk) begin
|
||||||
uart_axi_araddr <= 'h8;
|
uart_axi_araddr <= 'h8;
|
||||||
// Swap between sending data and status register (checking for full)
|
// Swap between sending data and status register (checking for full)
|
||||||
// Check status
|
// Check status
|
||||||
if (~rx_if.rdy && ~uart_axi_awvalid) begin
|
if (~rx_int_if.rdy && ~uart_axi_awvalid) begin
|
||||||
uart_axi_arvalid <= 1;
|
uart_axi_arvalid <= 1;
|
||||||
if (uart_axi_rvalid && ~uart_axi_rdata[3]) begin
|
if (uart_axi_rvalid && ~uart_axi_rdata[3]) begin
|
||||||
rx_if.rdy <= 1;
|
rx_int_if.rdy <= 1;
|
||||||
uart_axi_arvalid <= 0;
|
uart_axi_arvalid <= 0;
|
||||||
end
|
end
|
||||||
end else begin
|
end else begin
|
||||||
if (~uart_axi_awvalid) begin
|
if (~uart_axi_awvalid) begin
|
||||||
// Then check data
|
// Then check data
|
||||||
if (rx_if.val && rx_if.rdy) begin
|
if (rx_int_if.val && rx_int_if.rdy) begin
|
||||||
rx_if.rdy <= 0;
|
rx_int_if.rdy <= 0;
|
||||||
uart_axi_wdata <= rx_if.dat;
|
uart_axi_wdata <= rx_int_if.dat;
|
||||||
uart_axi_awvalid <= 1;
|
uart_axi_awvalid <= 1;
|
||||||
uart_axi_awaddr <= 'h4;
|
uart_axi_awaddr <= 'h4;
|
||||||
if (rx_if.eop) begin
|
if (rx_int_if.eop) begin
|
||||||
uart_state <= UART_WAIT_STREAM;
|
uart_state <= UART_WAIT_STREAM;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
@ -181,28 +185,83 @@ always_ff @ (posedge i_clk) begin
|
||||||
end
|
end
|
||||||
|
|
||||||
axi_uartlite_0 uart (
|
axi_uartlite_0 uart (
|
||||||
.s_axi_aclk(i_clk), // input wire s_axi_aclk
|
.s_axi_aclk(i_clk), // input wire s_axi_aclk
|
||||||
.s_axi_aresetn(~i_rst), // input wire s_axi_aresetn
|
.s_axi_aresetn(~i_rst), // input wire s_axi_aresetn
|
||||||
.interrupt(interrupt), // output wire interrupt
|
.interrupt(interrupt), // output wire interrupt
|
||||||
.s_axi_awaddr(uart_axi_awaddr), // input wire [3 : 0] s_axi_awaddr
|
.s_axi_awaddr(uart_axi_awaddr), // input wire [3 : 0] s_axi_awaddr
|
||||||
.s_axi_awvalid(uart_axi_awvalid), // input wire s_axi_awvalid
|
.s_axi_awvalid(uart_axi_awvalid), // input wire s_axi_awvalid
|
||||||
.s_axi_awready(uart_axi_awready), // output wire s_axi_awready
|
.s_axi_awready(uart_axi_awready), // output wire s_axi_awready
|
||||||
.s_axi_wdata(uart_axi_wdata), // input wire [31 : 0] s_axi_wdata
|
.s_axi_wdata(uart_axi_wdata), // input wire [31 : 0] s_axi_wdata
|
||||||
.s_axi_wstrb('d0), // input wire [3 : 0] s_axi_wstrb
|
.s_axi_wstrb('d0), // input wire [3 : 0] s_axi_wstrb
|
||||||
.s_axi_wvalid(uart_axi_awvalid), // input wire s_axi_wvalid
|
.s_axi_wvalid(uart_axi_awvalid), // input wire s_axi_wvalid
|
||||||
.s_axi_wready(uart_axi_wready), // output wire s_axi_wready
|
.s_axi_wready(uart_axi_wready), // output wire s_axi_wready
|
||||||
.s_axi_bresp(uart_axi_bresp), // output wire [1 : 0] s_axi_bresp
|
.s_axi_bresp(uart_axi_bresp), // output wire [1 : 0] s_axi_bresp
|
||||||
.s_axi_bvalid(), // output wire s_axi_bvalid
|
.s_axi_bvalid(), // output wire s_axi_bvalid
|
||||||
.s_axi_bready(1'b1), // input wire s_axi_bready
|
.s_axi_bready(1'b1), // input wire s_axi_bready
|
||||||
.s_axi_araddr(uart_axi_araddr), // input wire [3 : 0] s_axi_araddr
|
.s_axi_araddr(uart_axi_araddr), // input wire [3 : 0] s_axi_araddr
|
||||||
.s_axi_arvalid(uart_axi_arvalid), // input wire s_axi_arvalid
|
.s_axi_arvalid(uart_axi_arvalid), // input wire s_axi_arvalid
|
||||||
.s_axi_arready(uart_axi_arready), // output wire s_axi_arready
|
.s_axi_arready(uart_axi_arready), // output wire s_axi_arready
|
||||||
.s_axi_rdata(uart_axi_rdata), // output wire [31 : 0] s_axi_rdata
|
.s_axi_rdata(uart_axi_rdata), // output wire [31 : 0] s_axi_rdata
|
||||||
.s_axi_rresp(uart_axi_rresp), // output wire [1 : 0] s_axi_rresp
|
.s_axi_rresp(uart_axi_rresp), // output wire [1 : 0] s_axi_rresp
|
||||||
.s_axi_rvalid(uart_axi_rvalid), // output wire s_axi_rvalid
|
.s_axi_rvalid(uart_axi_rvalid), // output wire s_axi_rvalid
|
||||||
.s_axi_rready(1'd1), // input wire s_axi_rready
|
.s_axi_rready(1'd1), // input wire s_axi_rready
|
||||||
.rx(i_rx_uart), // input wire rx
|
.rx(i_rx_uart), // input wire rx
|
||||||
.tx(o_tx_uart) // output wire tx
|
.tx(o_tx_uart) // output wire tx
|
||||||
);
|
);
|
||||||
|
|
||||||
|
// Modules for data width converstion (UART is 1 byte, we want 8)
|
||||||
|
logic [7:0] tx_tkeep;
|
||||||
|
axis_dwidth_converter_1_to_8 tx_dwidth_converter (
|
||||||
|
.aclk(i_clk), // input wire aclk
|
||||||
|
.aresetn(~i_rst), // input wire aresetn
|
||||||
|
.s_axis_tvalid(tx_int_if.val), // input wire s_axis_tvalid
|
||||||
|
.s_axis_tready(tx_int_if.rdy), // output wire s_axis_tready
|
||||||
|
.s_axis_tdata (tx_int_if.dat), // input wire [7 : 0] s_axis_tdata
|
||||||
|
.s_axis_tlast (tx_int_if.eop), // input wire s_axis_tlast
|
||||||
|
.m_axis_tvalid(tx_if.val), // output wire m_axis_tvalid
|
||||||
|
.m_axis_tready(tx_if.rdy), // input wire m_axis_tready
|
||||||
|
.m_axis_tdata (tx_if.dat), // output wire [63 : 0] m_axis_tdata
|
||||||
|
.m_axis_tkeep (tx_tkeep), // output wire [7 : 0] m_axis_tkeep
|
||||||
|
.m_axis_tlast (tx_if.eop) // output wire m_axis_tlast
|
||||||
|
);
|
||||||
|
|
||||||
|
always_comb begin
|
||||||
|
tx_if.mod = $countones(tx_tkeep);
|
||||||
|
end
|
||||||
|
|
||||||
|
always_ff @ (posedge i_clk) begin
|
||||||
|
if (i_rst) begin
|
||||||
|
tx_if.ctl <= 0;
|
||||||
|
tx_if.err <= 0;
|
||||||
|
tx_if.sop <= 1;
|
||||||
|
end else begin
|
||||||
|
if (tx_if.val && tx_if.rdy) begin
|
||||||
|
tx_if.sop <= tx_if.eop;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
logic [7:0] rx_tkeep;
|
||||||
|
axis_dwidth_converter_8_to_1 rx_dwidth_converter (
|
||||||
|
.aclk(i_clk), // input wire aclk
|
||||||
|
.aresetn(~i_rst), // input wire aresetn
|
||||||
|
.s_axis_tvalid(rx_if.val), // input wire s_axis_tvalid
|
||||||
|
.s_axis_tready(rx_if.rdy), // output wire s_axis_tready
|
||||||
|
.s_axis_tdata(rx_if.dat), // input wire [63 : 0] s_axis_tdata
|
||||||
|
.s_axis_tlast(rx_if.eop), // input wire s_axis_tlast
|
||||||
|
.s_axis_tkeep(rx_tkeep), // input wire [7 : 0] s_axis_tkeep
|
||||||
|
.m_axis_tvalid(rx_int_if.val), // output wire m_axis_tvalid
|
||||||
|
.m_axis_tready(rx_int_if.rdy), // input wire m_axis_tready
|
||||||
|
.m_axis_tdata(rx_int_if.dat), // output wire [7 : 0] m_axis_tdata
|
||||||
|
.m_axis_tlast(rx_int_if.eop) // output wire m_axis_tlast
|
||||||
|
);
|
||||||
|
|
||||||
|
always_comb begin
|
||||||
|
rx_tkeep = {8{1'b1}};
|
||||||
|
for (int i = 0; i < 7; i++)
|
||||||
|
if (rx_if.mod > 0 && rx_if.mod <= i)
|
||||||
|
rx_tkeep[i] = 0;
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
@ -81,7 +81,7 @@ interface if_axi_stream # (
|
||||||
input logic [CTL_BITS-1:0] ctl_in = 0);
|
input logic [CTL_BITS-1:0] ctl_in = 0);
|
||||||
logic sop_l=0;
|
logic sop_l=0;
|
||||||
|
|
||||||
reset_source();
|
val = 0;
|
||||||
@(posedge i_clk);
|
@(posedge i_clk);
|
||||||
|
|
||||||
while (len > 0) begin
|
while (len > 0) begin
|
||||||
|
|
@ -97,7 +97,7 @@ interface if_axi_stream # (
|
||||||
@(posedge i_clk); // Go to next clock edge
|
@(posedge i_clk); // Go to next clock edge
|
||||||
while (!rdy) @(posedge i_clk); // If not rdy then wait here
|
while (!rdy) @(posedge i_clk); // If not rdy then wait here
|
||||||
end
|
end
|
||||||
reset_source();
|
val = 0;
|
||||||
endtask
|
endtask
|
||||||
|
|
||||||
task print();
|
task print();
|
||||||
|
|
|
||||||
Binary file not shown.
|
|
@ -23,7 +23,7 @@
|
||||||
module zcash_fpga_top
|
module zcash_fpga_top
|
||||||
import zcash_fpga_pkg::*, equihash_pkg::*;
|
import zcash_fpga_pkg::*, equihash_pkg::*;
|
||||||
#(
|
#(
|
||||||
parameter CORE_DAT_BYTS = 8 // Only tested at 8 byte data width
|
parameter DAT_BYTS = 8 // Only tested at 8 byte data width
|
||||||
)(
|
)(
|
||||||
// Clocks and resets
|
// Clocks and resets
|
||||||
input i_clk_100, i_rst_100, // 100 MHz clock
|
input i_clk_100, i_rst_100, // 100 MHz clock
|
||||||
|
|
@ -36,9 +36,7 @@ module zcash_fpga_top
|
||||||
if_axi_stream.source tx_if
|
if_axi_stream.source tx_if
|
||||||
);
|
);
|
||||||
|
|
||||||
localparam CORE_DAT_BITS = CORE_DAT_BYTS*8;
|
localparam CTL_BITS = 8;
|
||||||
localparam CORE_MOD_BITS = $clog2(CORE_DAT_BYTS);
|
|
||||||
localparam CORE_CTL_BITS = 8;
|
|
||||||
|
|
||||||
// These are the resets combined with the user reset
|
// These are the resets combined with the user reset
|
||||||
logic usr_rst_100, rst_100;
|
logic usr_rst_100, rst_100;
|
||||||
|
|
@ -46,13 +44,13 @@ logic usr_rst_200, rst_200;
|
||||||
logic usr_rst_300, rst_300;
|
logic usr_rst_300, rst_300;
|
||||||
logic usr_rst;
|
logic usr_rst;
|
||||||
|
|
||||||
if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BITS(CORE_CTL_BITS)) equihash_axi(i_clk_if);
|
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) equihash_axi(i_clk_if);
|
||||||
if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BITS(CORE_CTL_BITS)) equihash_axi_s(i_clk_100);
|
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) equihash_axi_s(i_clk_100);
|
||||||
|
|
||||||
if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BITS(CORE_CTL_BITS)) secp256k1_out_if(i_clk_if);
|
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) secp256k1_out_if(i_clk_if);
|
||||||
if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BITS(CORE_CTL_BITS)) secp256k1_in_if(i_clk_if);
|
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) secp256k1_in_if(i_clk_if);
|
||||||
if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BITS(CORE_CTL_BITS)) secp256k1_out_if_s(i_clk_200);
|
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) secp256k1_out_if_s(i_clk_200);
|
||||||
if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BITS(CORE_CTL_BITS)) secp256k1_in_if_s(i_clk_200);
|
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) secp256k1_in_if_s(i_clk_200);
|
||||||
|
|
||||||
equihash_bm_t equihash_mask, equihash_mask_s;
|
equihash_bm_t equihash_mask, equihash_mask_s;
|
||||||
logic equihash_mask_val, equihash_mask_val_s;
|
logic equihash_mask_val, equihash_mask_val_s;
|
||||||
|
|
@ -82,54 +80,18 @@ synchronizer #(.DAT_BITS ( 1 ), .NUM_CLKS ( 3 )) rst_300_sync (
|
||||||
);
|
);
|
||||||
always_ff @ (posedge i_clk_300) rst_300 <= i_rst_300 || usr_rst_300;
|
always_ff @ (posedge i_clk_300) rst_300 <= i_rst_300 || usr_rst_300;
|
||||||
|
|
||||||
|
|
||||||
// This block takes in the interface signals and interfaces with other blocks
|
// This block takes in the interface signals and interfaces with other blocks
|
||||||
// This runs on the same clock as the interface but we might need to change data width
|
// This runs on the same clock as the interface but we might need to change data width
|
||||||
if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BYTS(1)) rx_int_if (i_clk_if);
|
|
||||||
width_change_cdc_fifo #(
|
|
||||||
.IN_DAT_BYTS ( rx_if.DAT_BYTS ),
|
|
||||||
.OUT_DAT_BYTS ( CORE_DAT_BYTS ),
|
|
||||||
.CTL_BITS ( 8 ),
|
|
||||||
.FIFO_ABITS ( 6 ),
|
|
||||||
.USE_BRAM ( 1 ),
|
|
||||||
.CDC_ASYNC ( "NO" )
|
|
||||||
)
|
|
||||||
cdc_fifo_rx (
|
|
||||||
.i_clk_a ( i_clk_if ),
|
|
||||||
.i_rst_a ( i_rst_if ),
|
|
||||||
.i_clk_b ( i_clk_if ),
|
|
||||||
.i_rst_b ( i_rst_if ),
|
|
||||||
.i_axi_a ( rx_if ),
|
|
||||||
.o_axi_b ( rx_int_if )
|
|
||||||
);
|
|
||||||
|
|
||||||
if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BYTS(1)) tx_int_if (i_clk_if);
|
|
||||||
width_change_cdc_fifo #(
|
|
||||||
.IN_DAT_BYTS ( CORE_DAT_BYTS ),
|
|
||||||
.OUT_DAT_BYTS ( rx_if.DAT_BYTS ),
|
|
||||||
.CTL_BITS ( 8 ),
|
|
||||||
.FIFO_ABITS ( 6 ),
|
|
||||||
.USE_BRAM ( 1 ),
|
|
||||||
.CDC_ASYNC ( "NO" )
|
|
||||||
)
|
|
||||||
cdc_fifo_tx (
|
|
||||||
.i_clk_a ( i_clk_if ),
|
|
||||||
.i_rst_a ( i_rst_if ),
|
|
||||||
.i_clk_b ( i_clk_if ),
|
|
||||||
.i_rst_b ( i_rst_if ),
|
|
||||||
.i_axi_a ( tx_int_if ),
|
|
||||||
.o_axi_b ( tx_if )
|
|
||||||
);
|
|
||||||
|
|
||||||
control_top #(
|
control_top #(
|
||||||
.DAT_BYTS ( CORE_DAT_BYTS )
|
.DAT_BYTS ( DAT_BYTS )
|
||||||
)
|
)
|
||||||
control_top (
|
control_top (
|
||||||
.i_clk ( i_clk_if ),
|
.i_clk ( i_clk_if ),
|
||||||
.i_rst ( i_rst_if ),
|
.i_rst ( i_rst_if ),
|
||||||
.o_usr_rst ( usr_rst ),
|
.o_usr_rst ( usr_rst ),
|
||||||
.rx_if ( rx_int_if ),
|
.rx_if ( rx_if ),
|
||||||
.tx_if ( tx_int_if ),
|
.tx_if ( tx_if ),
|
||||||
.o_equihash_if ( equihash_axi ),
|
.o_equihash_if ( equihash_axi ),
|
||||||
.i_equihash_mask ( equihash_mask ),
|
.i_equihash_mask ( equihash_mask ),
|
||||||
.i_equihash_mask_val ( equihash_mask_val ),
|
.i_equihash_mask_val ( equihash_mask_val ),
|
||||||
|
|
@ -177,7 +139,7 @@ cdc_fifo_equihash_tx (
|
||||||
);
|
);
|
||||||
|
|
||||||
equihash_verif_top #(
|
equihash_verif_top #(
|
||||||
.DAT_BYTS( CORE_DAT_BYTS )
|
.DAT_BYTS( DAT_BYTS )
|
||||||
)
|
)
|
||||||
equihash_verif_top (
|
equihash_verif_top (
|
||||||
.i_clk ( i_clk_100 ),
|
.i_clk ( i_clk_100 ),
|
||||||
|
|
@ -225,12 +187,12 @@ cdc_fifo_secp256k1_tx (
|
||||||
);
|
);
|
||||||
|
|
||||||
// We add pipelining so this block can be on a different SLR
|
// We add pipelining so this block can be on a different SLR
|
||||||
if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BITS(CORE_CTL_BITS)) secp256k1_out_if_s_r(i_clk_200);
|
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) secp256k1_out_if_s_r(i_clk_200);
|
||||||
if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS), .CTL_BITS(CORE_CTL_BITS)) secp256k1_in_if_s_r(i_clk_200);
|
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) secp256k1_in_if_s_r(i_clk_200);
|
||||||
|
|
||||||
pipeline_if #(
|
pipeline_if #(
|
||||||
.DAT_BYTS( CORE_DAT_BYTS ),
|
.DAT_BYTS( DAT_BYTS ),
|
||||||
.CTL_BITS( CORE_CTL_BITS ),
|
.CTL_BITS( CTL_BITS ),
|
||||||
.NUM_STAGES (2)
|
.NUM_STAGES (2)
|
||||||
)
|
)
|
||||||
secp256k1_pipeline_if0 (
|
secp256k1_pipeline_if0 (
|
||||||
|
|
@ -240,8 +202,8 @@ secp256k1_pipeline_if0 (
|
||||||
);
|
);
|
||||||
|
|
||||||
pipeline_if #(
|
pipeline_if #(
|
||||||
.DAT_BYTS( CORE_DAT_BYTS ),
|
.DAT_BYTS( DAT_BYTS ),
|
||||||
.CTL_BITS( CORE_CTL_BITS ),
|
.CTL_BITS( CTL_BITS ),
|
||||||
.NUM_STAGES (2)
|
.NUM_STAGES (2)
|
||||||
)
|
)
|
||||||
secp256k1_pipeline_if1 (
|
secp256k1_pipeline_if1 (
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue