updates for v1.1.0 which includes bls12-381 co processor first cut

aws/cl_zcash/build/checkpoints/to_aws/.gitignore

@@ -0,0 +1,4 @@
+# Ignore everything in this directory
+*
+# Except this file
+!.gitignore

aws/cl_zcash/build/reports/.gitignore

@@ -0,0 +1,4 @@
+# Ignore everything in this directory
+*
+# Except this file
+!.gitignore

aws/cl_zcash/build/scripts/create_dcp_from_cl.tcl

@@ -19,7 +19,7 @@ package require tar
 set TOP top_sp
 
 ## Replace with the name of your module
-set CL_MODULE cl_hello_world
+set CL_MODULE cl_zcash
 
 #################################################
 ## Command-line Arguments

aws/cl_zcash/build/scripts/encrypt.tcl

@@ -18,6 +18,7 @@
 # Add check if /build and /build/src_port_encryption directories exist
 # Add check if the vivado_keyfile exist
 
+set ZCASH_DIR $::env(ZCASH_DIR)
 set HDK_SHELL_DIR $::env(HDK_SHELL_DIR)
 set HDK_SHELL_DESIGN_DIR $::env(HDK_SHELL_DESIGN_DIR)
 set CL_DIR $::env(CL_DIR)
@@ -30,16 +31,29 @@ if {[llength [glob -nocomplain -dir $TARGET_DIR *]] != 0} {
 
 #---- Developr would replace this section with design files ----
 
+set fileName "${ZCASH_DIR}/zcash_fpga/src/rtl/top/include.f"
+catch {set fptr [open $fileName r]} ;
+set contents [read -nonewline $fptr] ;#Read the file contents
+close $fptr ;#Close the file since it has been read now
+set splitCont [split $contents "\n"] ;#Split the files contents on new line
+foreach ele $splitCont {
+  set filep [subst $ele]
+  if { [file exists $filep] } {
+    file copy -force $filep $TARGET_DIR
+    puts "Copied $filep into $TARGET_DIR"
+  }
+}
+
 ## Change file names and paths below to reflect your CL area.  DO NOT include AWS RTL files.
-file copy -force $CL_DIR/design/cl_hello_world_defines.vh             $TARGET_DIR
+file copy -force $CL_DIR/design/cl_zcash_defines.vh                   $TARGET_DIR
 file copy -force $CL_DIR/design/cl_id_defines.vh                      $TARGET_DIR
-file copy -force $CL_DIR/design/cl_hello_world.sv                     $TARGET_DIR 
+file copy -force $CL_DIR/design/cl_zcash.sv                           $TARGET_DIR
+file copy -force $CL_DIR/design/cl_zcash_aws_wrapper.sv               $TARGET_DIR
 file copy -force $CL_DIR/../common/design/cl_common_defines.vh        $TARGET_DIR
 file copy -force $UNUSED_TEMPLATES_DIR/unused_apppf_irq_template.inc  $TARGET_DIR
 file copy -force $UNUSED_TEMPLATES_DIR/unused_cl_sda_template.inc     $TARGET_DIR
 file copy -force $UNUSED_TEMPLATES_DIR/unused_ddr_a_b_d_template.inc  $TARGET_DIR
 file copy -force $UNUSED_TEMPLATES_DIR/unused_ddr_c_template.inc      $TARGET_DIR
-file copy -force $UNUSED_TEMPLATES_DIR/unused_dma_pcis_template.inc   $TARGET_DIR
 file copy -force $UNUSED_TEMPLATES_DIR/unused_pcim_template.inc       $TARGET_DIR
 file copy -force $UNUSED_TEMPLATES_DIR/unused_sh_bar1_template.inc    $TARGET_DIR
 file copy -force $UNUSED_TEMPLATES_DIR/unused_flr_template.inc        $TARGET_DIR

aws/cl_zcash/build/scripts/synth_cl_zcash.tcl

@@ -60,6 +60,26 @@ read_verilog -sv [ list \
 
 puts "AWS FPGA: Reading IP blocks";
 
+# User IP
+read_ip [ list \
+  $CL_DIR/ip/axis_dwidth_converter_64_to_8/axis_dwidth_converter_64_to_8.xci \
+  $CL_DIR/ip/axis_dwidth_converter_8_to_64/axis_dwidth_converter_8_to_64.xci \
+  $CL_DIR/ip/axis_dwidth_converter_48_to_8/axis_dwidth_converter_48_to_8.xci \
+  $CL_DIR/ip/axi_fifo_mm_s_0/axi_fifo_mm_s_0.xci
+]
+
+puts "AWS FPGA: Generating IP blocks";
+
+set_property generate_synth_checkpoint false [get_files axis_dwidth_converter_64_to_8.xci]
+set_property generate_synth_checkpoint false [get_files axis_dwidth_converter_8_to_64.xci]
+set_property generate_synth_checkpoint false [get_files axis_dwidth_converter_48_to_8.xci]
+set_property generate_synth_checkpoint false [get_files axi_fifo_mm_s_0.xci]
+
+generate_target all [get_ips axis_dwidth_converter_64_to_8]
+generate_target all [get_ips axis_dwidth_converter_8_to_64]
+generate_target all [get_ips axis_dwidth_converter_48_to_8]
+generate_target all [get_ips axi_fifo_mm_s_0]
+
 #Read IP for axi register slices
 read_ip [ list \
   $HDK_SHELL_DESIGN_DIR/ip/src_register_slice/src_register_slice.xci \

aws/cl_zcash/design/cl_zcash_aws_wrapper.sv

@@ -37,6 +37,8 @@ if_axi_stream #(.DAT_BYTS(64), .CTL_BITS(1)) rx_aws_if (i_clk);
 if_axi_stream #(.DAT_BYTS(64), .CTL_BITS(1)) tx_aws_if (i_clk);
 
 logic [7:0] rx_zcash_if_keep, tx_zcash_if_keep;
+logic [63:0] rx_aws_if_keep, tx_aws_if_keep;
+
 
 always_comb begin
   rx_zcash_if_keep = rx_zcash_if.get_keep_from_mod();
@@ -147,7 +149,7 @@ axis_dwidth_converter_8_to_64 converter_8_to_64 (
   .m_axis_tready( tx_aws_if.rdy    ),
   .m_axis_tdata ( tx_aws_if.dat    ),
   .m_axis_tlast ( tx_aws_if.eop    ),
-  .m_axis_tkeep ( tx_aws_if.mod    )
+  .m_axis_tkeep ( tx_aws_if_keep   )
 );
 
 // Convert 64 bytes to 8 bytes
@@ -158,7 +160,7 @@ axis_dwidth_converter_64_to_8 converter_64_to_8 (
   .s_axis_tready( rx_aws_if.rdy    ),
   .s_axis_tdata ( rx_aws_if.dat    ),
   .s_axis_tlast ( rx_aws_if.eop    ),
-  .s_axis_tkeep ( rx_aws_if.mod    ),
+  .s_axis_tkeep ( rx_aws_if_keep   ),
   .m_axis_tvalid( tx_zcash_if.val  ),
   .m_axis_tready( tx_zcash_if.rdy  ),
   .m_axis_tdata ( tx_zcash_if.dat  ),
@@ -231,14 +233,14 @@ axi_fifo_mm_s_0 axi_fifo_mm_s_0 (
   .axi_str_txd_tvalid ( rx_aws_if.val  ),
   .axi_str_txd_tready ( rx_aws_if.rdy  ),
   .axi_str_txd_tlast  ( rx_aws_if.eop  ),
-  .axi_str_txd_tkeep  ( rx_aws_if.mod ),
+  .axi_str_txd_tkeep  ( rx_aws_if_keep ),
   .axi_str_txd_tdata  ( rx_aws_if.dat  ),
 
   .s2mm_prmry_reset_out_n(),
   .axi_str_rxd_tvalid( tx_aws_if.val  ),
   .axi_str_rxd_tready( tx_aws_if.rdy  ),
   .axi_str_rxd_tlast ( tx_aws_if.eop  ),
-  .axi_str_rxd_tkeep ( tx_aws_if.mod ),
+  .axi_str_rxd_tkeep ( tx_aws_if_keep ),
   .axi_str_rxd_tdata ( tx_aws_if.dat  )
 );
 

aws/cl_zcash/verif/scripts/waves.tcl

@@ -21,4 +21,4 @@ add_wave /tb/card/fpga/CL/zcash_if_tx/*
 add_wave /tb/card/fpga/CL/zcash_if_rx/*
 add_wave /tb/card/fpga/CL/cl_zcash_aws_wrapper/*
 
-run 10 us
+run 110 us

aws/cl_zcash/verif/tests/test_zcash.sv

@@ -80,13 +80,16 @@ endtask
 task write_stream(input logic [1024*8-1:0] data, input integer len);
 
   logic [31:0] rdata;
+  logic [63:0] strb;
   integer len_;
   len_ = len;
   read_ocl_reg(.addr(`AXI_FIFO_OFFSET+32'hC), .rdata(rdata));
   if (len > rdata) $fatal(1, "ERROR: write_pcis::AXI-FIFO does not have enough space to write %d bytes (%d free)", len, rdata);
 
   while(len_ > 0) begin
-    tb.poke_pcis(.addr(0), .data(data[511:0]), .strb(0));
+    strb = 0;
+    for(int i = 0; i < 64; i++) if(len_ > i) strb[i] = 1;
+    tb.poke_pcis(.addr(0), .data(data[511:0]), .strb(strb));
     len_ = len_ - 512/8;
     data = data >> 512;
   end
@@ -94,9 +97,10 @@ task write_stream(input logic [1024*8-1:0] data, input integer len);
 
   $display ("INFO: write_pcis::Wrote %d bytes of data", len);
 
-  // Check transmit complete bit and reset it
+  // Wait a few clocks then check transmit complete bit and reset it
+  repeat (10) @(posedge tb.card.fpga.clk_main_a0);
   read_ocl_reg(.addr(`AXI_FIFO_OFFSET), .rdata(rdata));
-  if(rdata[27] == 0) $display("WARNING: write_stream transmit complete bit not set");
+  if(rdata[27] == 0) $display("WARNING: write_stream transmit complete bit not set (read 0x%x)", rdata);
   write_ocl_reg(.addr(`AXI_FIFO_OFFSET), .data(32'h08000000));
 
 endtask
@@ -141,7 +145,7 @@ task test_status_message();
       while(stream_len == 0) read_stream(.data(stream_data), .len(stream_len));
     end
     begin
-      while(10000) @(posedge tb.card.fpga.clk_main_a0);
+      repeat(10000) @(posedge tb.card.fpga.clk_main_a0);
       $fatal(1, "ERROR: No reply received from status_request");
     end
   join_any

zcash_fpga/src/rtl/secp256k1/secp256k1_point_mult.sv

@@ -45,6 +45,8 @@ module secp256k1_point_mult
   input            i_p2_val
 );
 
+localparam CHK_INPUT = 0;
+
 // [0] is connection from/to dbl block, [1] is add block, [2] is arbitrated value
 if_axi_stream #(.DAT_BYTS(256*2/8), .CTL_BITS(16)) mult_in_if [2:0] (i_clk);
 if_axi_stream #(.DAT_BYTS(256/8), .CTL_BITS(16)) mult_out_if [2:0] (i_clk);
@@ -104,7 +106,7 @@ always_ff @ (posedge i_clk) begin
           p_q <= i_p2;
           state <= ADD_ONLY;
           // Check for special cases to determine double or add
-          if (i_p.x == i_p2.x && i_p.y == i_p2.y) begin
+          if (CHK_INPUT == 1 && i_p.x == i_p2.x && i_p.y == i_p2.y) begin
             p_dbl_in_val <= 1;
           end else begin
             p_add_in_val <= 1;
@@ -144,21 +146,21 @@ always_ff @ (posedge i_clk) begin
           if (k_l[0]) begin
             p_add_in_val <= 1;
             // Need to check for special case where the x, y point is the same
+            if (CHK_INPUT == 1) begin
               if (p_q.x == p_n.x && p_q.y == p_n.y) begin
                 special_dbl <= 1;
                 p_add_in_val <= 0;
                 p_add_done <= 1;
               end
+            end
           end else begin
             p_add_done <= 1;
           end
-
           // Don't need to double on the final bit
           if ((k_l >> 1) != 0)
             p_dbl_in_val <= ~lookahead_dbl; // Don't do if we already started
           else
             p_dbl_done <= 1;
-
           if (k_l == 0) begin
             state <= FINISHED;
             o_p <= p_add;
@@ -167,7 +169,6 @@ always_ff @ (posedge i_clk) begin
             p_add_in_val <= 0;
           end
         end
-
       end
       {ADD_ONLY}: begin
         p_dbl_in_val <= (p_dbl_in_val && p_dbl_in_rdy) ? 0 : p_dbl_in_val;

zcash_fpga/src/rtl/top/zcash_fpga_pkg.sv

@@ -27,14 +27,15 @@ package zcash_fpga_pkg;
 
   import bls12_381_pkg::point_type_t;
 
-  parameter FPGA_VERSION = 32'h01_00_01;  //v1.0.0
+  parameter FPGA_VERSION = 32'h01_01_00;  //v1.1.0
 
   // What features are enabled in this build
   parameter bit ENB_VERIFY_SECP256K1_SIG = 1;
   parameter bit ENB_VERIFY_EQUIHASH = 1;
   parameter bit ENB_BLS12_381 = 1;
 
-  localparam [63:0] FPGA_CMD_CAP = {{61'd0},
+  localparam [63:0] FPGA_CMD_CAP = {{60'd0},
+                                     ENB_BLS12_381,
                                      ENB_VERIFY_SECP256K1_SIG,
                                     (ENB_VERIFY_EQUIHASH && equihash_pkg::N == 144 && equihash_pkg::K == 5),       // N = 144, K = 5 for VERIFY_EQUIHASH command
                                     (ENB_VERIFY_EQUIHASH && equihash_pkg::N == 200 && equihash_pkg::K == 9)};      // N = 200, K = 9 for VERIFY_EQUIHASH command