updates for v1.1.0 which includes bls12-381 co processor first cut
This commit is contained in:
bsdevlin
parent
d1ab35d9cd
commit
ae2f524c6b
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@ -0,0 +1,4 @@
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# Ignore everything in this directory
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*
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# Except this file
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!.gitignore
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@ -0,0 +1,4 @@
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# Ignore everything in this directory
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*
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# Except this file
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!.gitignore
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@ -19,7 +19,7 @@ package require tar
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set TOP top_sp
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## Replace with the name of your module
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set CL_MODULE cl_hello_world
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set CL_MODULE cl_zcash
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#################################################
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## Command-line Arguments
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@ -39,7 +39,7 @@ set uram_option [lindex $argv 11]
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set notify_via_sns [lindex $argv 12]
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set VDEFINES [lindex $argv 13]
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##################################################
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## Flow control variables
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## Flow control variables
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##################################################
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set cl.synth 1
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set implement 1
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@ -148,7 +148,7 @@ if {[string compare $notify_via_sns "1"] == 0} {
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}
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##################################################
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### Strategy options
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### Strategy options
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##################################################
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switch $strategy {
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"BASIC" {
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@ -187,14 +187,14 @@ source $HDK_SHELL_DIR/build/scripts/device_type.tcl
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source $HDK_SHELL_DIR/build/scripts/step_user.tcl -notrace
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########################################
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## Generate clocks based on Recipe
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## Generate clocks based on Recipe
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########################################
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
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source $HDK_SHELL_DIR/build/scripts/aws_gen_clk_constraints.tcl
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#################################################################
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#### Do not remove this setting. Need to workaround bug
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#### Do not remove this setting. Need to workaround bug
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##################################################################
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set_param hd.clockRoutingWireReduction false
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##################################################
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@ -236,7 +236,7 @@ if {$implement} {
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# Apply Clock Properties for Clock Table Recipes
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##################################################
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Sourcing aws_clock_properties.tcl to apply properties to clocks. ";
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# Apply properties to clocks
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source $HDK_SHELL_DIR/build/scripts/aws_clock_properties.tcl
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@ -18,6 +18,7 @@
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# Add check if /build and /build/src_port_encryption directories exist
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# Add check if the vivado_keyfile exist
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set ZCASH_DIR $::env(ZCASH_DIR)
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set HDK_SHELL_DIR $::env(HDK_SHELL_DIR)
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set HDK_SHELL_DESIGN_DIR $::env(HDK_SHELL_DESIGN_DIR)
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set CL_DIR $::env(CL_DIR)
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@ -30,16 +31,29 @@ if {[llength [glob -nocomplain -dir $TARGET_DIR *]] != 0} {
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#---- Developr would replace this section with design files ----
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set fileName "${ZCASH_DIR}/zcash_fpga/src/rtl/top/include.f"
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catch {set fptr [open $fileName r]} ;
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set contents [read -nonewline $fptr] ;#Read the file contents
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close $fptr ;#Close the file since it has been read now
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set splitCont [split $contents "\n"] ;#Split the files contents on new line
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foreach ele $splitCont {
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set filep [subst $ele]
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if { [file exists $filep] } {
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file copy -force $filep $TARGET_DIR
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puts "Copied $filep into $TARGET_DIR"
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}
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}
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## Change file names and paths below to reflect your CL area. DO NOT include AWS RTL files.
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file copy -force $CL_DIR/design/cl_hello_world_defines.vh $TARGET_DIR
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file copy -force $CL_DIR/design/cl_zcash_defines.vh $TARGET_DIR
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file copy -force $CL_DIR/design/cl_id_defines.vh $TARGET_DIR
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file copy -force $CL_DIR/design/cl_hello_world.sv $TARGET_DIR
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file copy -force $CL_DIR/../common/design/cl_common_defines.vh $TARGET_DIR
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file copy -force $CL_DIR/design/cl_zcash.sv $TARGET_DIR
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file copy -force $CL_DIR/design/cl_zcash_aws_wrapper.sv $TARGET_DIR
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file copy -force $CL_DIR/../common/design/cl_common_defines.vh $TARGET_DIR
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file copy -force $UNUSED_TEMPLATES_DIR/unused_apppf_irq_template.inc $TARGET_DIR
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file copy -force $UNUSED_TEMPLATES_DIR/unused_cl_sda_template.inc $TARGET_DIR
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file copy -force $UNUSED_TEMPLATES_DIR/unused_ddr_a_b_d_template.inc $TARGET_DIR
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file copy -force $UNUSED_TEMPLATES_DIR/unused_ddr_c_template.inc $TARGET_DIR
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file copy -force $UNUSED_TEMPLATES_DIR/unused_dma_pcis_template.inc $TARGET_DIR
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file copy -force $UNUSED_TEMPLATES_DIR/unused_pcim_template.inc $TARGET_DIR
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file copy -force $UNUSED_TEMPLATES_DIR/unused_sh_bar1_template.inc $TARGET_DIR
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file copy -force $UNUSED_TEMPLATES_DIR/unused_flr_template.inc $TARGET_DIR
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@ -21,7 +21,7 @@ set VDEFINES $VDEFINES
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create_project -in_memory -part [DEVICE_TYPE] -force
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########################################
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## Generate clocks based on Recipe
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## Generate clocks based on Recipe
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########################################
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
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@ -60,6 +60,26 @@ read_verilog -sv [ list \
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puts "AWS FPGA: Reading IP blocks";
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# User IP
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read_ip [ list \
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$CL_DIR/ip/axis_dwidth_converter_64_to_8/axis_dwidth_converter_64_to_8.xci \
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$CL_DIR/ip/axis_dwidth_converter_8_to_64/axis_dwidth_converter_8_to_64.xci \
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$CL_DIR/ip/axis_dwidth_converter_48_to_8/axis_dwidth_converter_48_to_8.xci \
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$CL_DIR/ip/axi_fifo_mm_s_0/axi_fifo_mm_s_0.xci
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]
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puts "AWS FPGA: Generating IP blocks";
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set_property generate_synth_checkpoint false [get_files axis_dwidth_converter_64_to_8.xci]
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set_property generate_synth_checkpoint false [get_files axis_dwidth_converter_8_to_64.xci]
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set_property generate_synth_checkpoint false [get_files axis_dwidth_converter_48_to_8.xci]
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set_property generate_synth_checkpoint false [get_files axi_fifo_mm_s_0.xci]
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generate_target all [get_ips axis_dwidth_converter_64_to_8]
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generate_target all [get_ips axis_dwidth_converter_8_to_64]
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generate_target all [get_ips axis_dwidth_converter_48_to_8]
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generate_target all [get_ips axi_fifo_mm_s_0]
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#Read IP for axi register slices
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read_ip [ list \
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$HDK_SHELL_DESIGN_DIR/ip/src_register_slice/src_register_slice.xci \
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@ -111,8 +131,8 @@ eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS $VDEFINES
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set failval [catch {exec grep "FAIL" failfast.csv}]
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if { $failval==0 } {
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puts "AWS FPGA: FATAL ERROR--Resource utilization error; check failfast.csv for details"
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exit 1
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puts "AWS FPGA: FATAL ERROR--Resource utilization error; check failfast.csv for details"
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exit 1
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}
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) writing post synth checkpoint.";
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@ -37,6 +37,8 @@ if_axi_stream #(.DAT_BYTS(64), .CTL_BITS(1)) rx_aws_if (i_clk);
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if_axi_stream #(.DAT_BYTS(64), .CTL_BITS(1)) tx_aws_if (i_clk);
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logic [7:0] rx_zcash_if_keep, tx_zcash_if_keep;
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logic [63:0] rx_aws_if_keep, tx_aws_if_keep;
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always_comb begin
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rx_zcash_if_keep = rx_zcash_if.get_keep_from_mod();
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@ -147,7 +149,7 @@ axis_dwidth_converter_8_to_64 converter_8_to_64 (
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.m_axis_tready( tx_aws_if.rdy ),
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.m_axis_tdata ( tx_aws_if.dat ),
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.m_axis_tlast ( tx_aws_if.eop ),
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.m_axis_tkeep ( tx_aws_if.mod )
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.m_axis_tkeep ( tx_aws_if_keep )
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);
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// Convert 64 bytes to 8 bytes
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@ -158,7 +160,7 @@ axis_dwidth_converter_64_to_8 converter_64_to_8 (
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.s_axis_tready( rx_aws_if.rdy ),
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.s_axis_tdata ( rx_aws_if.dat ),
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.s_axis_tlast ( rx_aws_if.eop ),
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.s_axis_tkeep ( rx_aws_if.mod ),
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.s_axis_tkeep ( rx_aws_if_keep ),
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.m_axis_tvalid( tx_zcash_if.val ),
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.m_axis_tready( tx_zcash_if.rdy ),
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.m_axis_tdata ( tx_zcash_if.dat ),
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@ -228,22 +230,22 @@ axi_fifo_mm_s_0 axi_fifo_mm_s_0 (
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.s_axi4_rready ( rx_axi4_if.rready ),
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.mm2s_prmry_reset_out_n(),
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.axi_str_txd_tvalid ( rx_aws_if.val ),
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.axi_str_txd_tready ( rx_aws_if.rdy ),
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.axi_str_txd_tlast ( rx_aws_if.eop ),
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.axi_str_txd_tkeep ( rx_aws_if.mod ),
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.axi_str_txd_tdata ( rx_aws_if.dat ),
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.axi_str_txd_tvalid ( rx_aws_if.val ),
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.axi_str_txd_tready ( rx_aws_if.rdy ),
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.axi_str_txd_tlast ( rx_aws_if.eop ),
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.axi_str_txd_tkeep ( rx_aws_if_keep ),
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.axi_str_txd_tdata ( rx_aws_if.dat ),
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.s2mm_prmry_reset_out_n(),
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.axi_str_rxd_tvalid( tx_aws_if.val ),
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.axi_str_rxd_tready( tx_aws_if.rdy ),
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.axi_str_rxd_tlast ( tx_aws_if.eop ),
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.axi_str_rxd_tkeep ( tx_aws_if.mod ),
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.axi_str_rxd_tdata ( tx_aws_if.dat )
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.axi_str_rxd_tvalid( tx_aws_if.val ),
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.axi_str_rxd_tready( tx_aws_if.rdy ),
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.axi_str_rxd_tlast ( tx_aws_if.eop ),
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.axi_str_rxd_tkeep ( tx_aws_if_keep ),
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.axi_str_rxd_tdata ( tx_aws_if.dat )
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);
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always_comb begin
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rx_axi4_if.rid = 0;
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end
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endmodule
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endmodule
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@ -14,11 +14,11 @@
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# limitations under the License.
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add_wave /tb/card/fpga/CL/*pcis*
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add_wave /tb/card/fpga/CL/rx_axi_lite_if/*
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add_wave /tb/card/fpga/CL/rx_axi4_if/*
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add_wave /tb/card/fpga/CL/zcash_axi_lite_if/*
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add_wave /tb/card/fpga/CL/zcash_if_tx/*
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add_wave /tb/card/fpga/CL/zcash_if_rx/*
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add_wave /tb/card/fpga/CL/rx_axi_lite_if/*
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add_wave /tb/card/fpga/CL/rx_axi4_if/*
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add_wave /tb/card/fpga/CL/zcash_axi_lite_if/*
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add_wave /tb/card/fpga/CL/zcash_if_tx/*
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add_wave /tb/card/fpga/CL/zcash_if_rx/*
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add_wave /tb/card/fpga/CL/cl_zcash_aws_wrapper/*
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run 10 us
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run 110 us
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@ -80,13 +80,16 @@ endtask
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task write_stream(input logic [1024*8-1:0] data, input integer len);
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logic [31:0] rdata;
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logic [63:0] strb;
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integer len_;
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len_ = len;
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read_ocl_reg(.addr(`AXI_FIFO_OFFSET+32'hC), .rdata(rdata));
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if (len > rdata) $fatal(1, "ERROR: write_pcis::AXI-FIFO does not have enough space to write %d bytes (%d free)", len, rdata);
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while(len_ > 0) begin
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tb.poke_pcis(.addr(0), .data(data[511:0]), .strb(0));
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strb = 0;
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for(int i = 0; i < 64; i++) if(len_ > i) strb[i] = 1;
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tb.poke_pcis(.addr(0), .data(data[511:0]), .strb(strb));
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len_ = len_ - 512/8;
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data = data >> 512;
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end
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@ -94,9 +97,10 @@ task write_stream(input logic [1024*8-1:0] data, input integer len);
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$display ("INFO: write_pcis::Wrote %d bytes of data", len);
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// Check transmit complete bit and reset it
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// Wait a few clocks then check transmit complete bit and reset it
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repeat (10) @(posedge tb.card.fpga.clk_main_a0);
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read_ocl_reg(.addr(`AXI_FIFO_OFFSET), .rdata(rdata));
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if(rdata[27] == 0) $display("WARNING: write_stream transmit complete bit not set");
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if(rdata[27] == 0) $display("WARNING: write_stream transmit complete bit not set (read 0x%x)", rdata);
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write_ocl_reg(.addr(`AXI_FIFO_OFFSET), .data(32'h08000000));
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endtask
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@ -141,7 +145,7 @@ task test_status_message();
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while(stream_len == 0) read_stream(.data(stream_data), .len(stream_len));
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end
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begin
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while(10000) @(posedge tb.card.fpga.clk_main_a0);
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repeat(10000) @(posedge tb.card.fpga.clk_main_a0);
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$fatal(1, "ERROR: No reply received from status_request");
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end
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join_any
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@ -1,7 +1,7 @@
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/*
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This performs point multiplication. We use the standard double
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and add algorithm.
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Same as ec_point_mult but also has additional input for adding points
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which is needed in secp256k1 key verification.
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@ -45,6 +45,8 @@ module secp256k1_point_mult
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input i_p2_val
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);
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localparam CHK_INPUT = 0;
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// [0] is connection from/to dbl block, [1] is add block, [2] is arbitrated value
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if_axi_stream #(.DAT_BYTS(256*2/8), .CTL_BITS(16)) mult_in_if [2:0] (i_clk);
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if_axi_stream #(.DAT_BYTS(256/8), .CTL_BITS(16)) mult_out_if [2:0] (i_clk);
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@ -104,7 +106,7 @@ always_ff @ (posedge i_clk) begin
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p_q <= i_p2;
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state <= ADD_ONLY;
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// Check for special cases to determine double or add
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if (i_p.x == i_p2.x && i_p.y == i_p2.y) begin
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if (CHK_INPUT == 1 && i_p.x == i_p2.x && i_p.y == i_p2.y) begin
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p_dbl_in_val <= 1;
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end else begin
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p_add_in_val <= 1;
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@ -127,7 +129,7 @@ always_ff @ (posedge i_clk) begin
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p_dbl_in_val <= 1;
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lookahead_dbl <= 1;
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p_dbl_out_rdy <= 0; // Want to make sure we don't output while still waiting for add
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end
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end
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end
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if (p_add_out_val && p_add_out_rdy) begin
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p_add_done <= 1;
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@ -144,21 +146,21 @@ always_ff @ (posedge i_clk) begin
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if (k_l[0]) begin
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p_add_in_val <= 1;
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// Need to check for special case where the x, y point is the same
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if (p_q.x == p_n.x && p_q.y == p_n.y) begin
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special_dbl <= 1;
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p_add_in_val <= 0;
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p_add_done <= 1;
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if (CHK_INPUT == 1) begin
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if (p_q.x == p_n.x && p_q.y == p_n.y) begin
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special_dbl <= 1;
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p_add_in_val <= 0;
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p_add_done <= 1;
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end
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end
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end else begin
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p_add_done <= 1;
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end
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// Don't need to double on the final bit
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if ((k_l >> 1) != 0)
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p_dbl_in_val <= ~lookahead_dbl; // Don't do if we already started
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else
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p_dbl_done <= 1;
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if (k_l == 0) begin
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state <= FINISHED;
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o_p <= p_add;
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@ -167,7 +169,6 @@ always_ff @ (posedge i_clk) begin
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p_add_in_val <= 0;
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end
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end
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end
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{ADD_ONLY}: begin
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p_dbl_in_val <= (p_dbl_in_val && p_dbl_in_rdy) ? 0 : p_dbl_in_val;
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@ -256,7 +257,7 @@ localparam ARB_BIT = 8;
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resource_share # (
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.NUM_IN ( 2 ),
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.CTL_BITS ( 16 ),
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.DAT_BITS ( 512 ),
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.DAT_BITS ( 512 ),
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.DAT_BYTS ( 512/8 ),
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.OVR_WRT_BIT ( ARB_BIT ),
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.PIPELINE_IN ( 0 ),
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@ -267,14 +268,14 @@ resource_share_add (
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.i_rst ( i_rst ),
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.i_axi ( add_in_if[1:0] ),
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.o_res ( add_in_if[2] ),
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.i_res ( add_out_if[2] ),
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.i_res ( add_out_if[2] ),
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.o_axi ( add_out_if[1:0] )
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);
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resource_share # (
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.NUM_IN ( 2 ),
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.CTL_BITS ( 16 ),
|
||||
.DAT_BITS ( 512 ),
|
||||
.DAT_BITS ( 512 ),
|
||||
.DAT_BYTS ( 512/8 ),
|
||||
.OVR_WRT_BIT ( ARB_BIT ),
|
||||
.PIPELINE_IN ( 0 ),
|
||||
|
|
@ -285,14 +286,14 @@ resource_share_sub (
|
|||
.i_rst ( i_rst ),
|
||||
.i_axi ( sub_in_if[1:0] ),
|
||||
.o_res ( sub_in_if[2] ),
|
||||
.i_res ( sub_out_if[2] ),
|
||||
.i_res ( sub_out_if[2] ),
|
||||
.o_axi ( sub_out_if[1:0] )
|
||||
);
|
||||
|
||||
resource_share # (
|
||||
.NUM_IN ( 2 ),
|
||||
.CTL_BITS ( 16 ),
|
||||
.DAT_BITS ( 512 ),
|
||||
.DAT_BITS ( 512 ),
|
||||
.DAT_BYTS ( 512/8 ),
|
||||
.OVR_WRT_BIT ( ARB_BIT ),
|
||||
.PIPELINE_IN ( 0 ),
|
||||
|
|
@ -303,7 +304,7 @@ resource_share_mult (
|
|||
.i_rst ( i_rst ),
|
||||
.i_axi ( mult_in_if[1:0] ),
|
||||
.o_res ( mult_in_if[2] ),
|
||||
.i_res ( mult_out_if[2] ),
|
||||
.i_res ( mult_out_if[2] ),
|
||||
.o_axi ( mult_out_if[1:0] )
|
||||
);
|
||||
|
||||
|
|
@ -354,7 +355,7 @@ generate
|
|||
mult_out_if[2].ctl = i_mult_if.ctl;
|
||||
end
|
||||
end else begin
|
||||
|
||||
|
||||
always_comb begin
|
||||
o_mult_if.reset_source();
|
||||
i_mult_if.rdy = 0;
|
||||
|
|
|
|||
|
|
@ -24,17 +24,18 @@ package zcash_fpga_pkg;
|
|||
import equihash_pkg::N;
|
||||
import equihash_pkg::K;
|
||||
import secp256k1_pkg::secp256k1_ver_t;
|
||||
|
||||
|
||||
import bls12_381_pkg::point_type_t;
|
||||
|
||||
parameter FPGA_VERSION = 32'h01_00_01; //v1.0.0
|
||||
parameter FPGA_VERSION = 32'h01_01_00; //v1.1.0
|
||||
|
||||
// What features are enabled in this build
|
||||
parameter bit ENB_VERIFY_SECP256K1_SIG = 1;
|
||||
parameter bit ENB_VERIFY_EQUIHASH = 1;
|
||||
parameter bit ENB_BLS12_381 = 1;
|
||||
|
||||
localparam [63:0] FPGA_CMD_CAP = {{61'd0},
|
||||
localparam [63:0] FPGA_CMD_CAP = {{60'd0},
|
||||
ENB_BLS12_381,
|
||||
ENB_VERIFY_SECP256K1_SIG,
|
||||
(ENB_VERIFY_EQUIHASH && equihash_pkg::N == 144 && equihash_pkg::K == 5), // N = 144, K = 5 for VERIFY_EQUIHASH command
|
||||
(ENB_VERIFY_EQUIHASH && equihash_pkg::N == 200 && equihash_pkg::K == 9)}; // N = 200, K = 9 for VERIFY_EQUIHASH command
|
||||
|
|
|
|||
Loading…
Reference in New Issue