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zcash-fpga
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synthesis bug fix for bls12_381 module

This commit is contained in:
bsdevlin 2019-06-24 21:39:33 +08:00
parent adf8630be3
commit af5f552a51
1 changed files with 0 additions and 2 deletions
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2
zcash_fpga/src/rtl/bls12_381/bls12_381_top.sv
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@ -656,7 +656,6 @@ always_ff @ (posedge i_clk) begin
case (interrupt_state)
WAIT_FIFO: begin
idx_out_if.rdy <= 1;
interrupt_out_if.rdy <= 0;
if (idx_out_if.val) begin
idx_out_if.rdy <= 0;
interrupt_state <= SEND_HDR;
@ -676,7 +675,6 @@ always_ff @ (posedge i_clk) begin
end
end
SEND_DATA: begin
interrupt_out_if.rdy <= 1;
if (~tx_if.val || (tx_if.val && tx_if.rdy)) begin
tx_if.sop <= 0;
tx_if.val <= interrupt_out_if.val;