synthesis bug fix for bls12_381 module
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@ -656,7 +656,6 @@ always_ff @ (posedge i_clk) begin
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case (interrupt_state)
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WAIT_FIFO: begin
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idx_out_if.rdy <= 1;
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interrupt_out_if.rdy <= 0;
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if (idx_out_if.val) begin
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idx_out_if.rdy <= 0;
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interrupt_state <= SEND_HDR;
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@ -676,7 +675,6 @@ always_ff @ (posedge i_clk) begin
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end
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end
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SEND_DATA: begin
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interrupt_out_if.rdy <= 1;
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if (~tx_if.val || (tx_if.val && tx_if.rdy)) begin
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tx_if.sop <= 0;
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tx_if.val <= interrupt_out_if.val;
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