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add Xilinx FIFO and fix flow control

This commit is contained in:
bsdevlin 2020-09-09 22:02:23 -04:00
parent 4927d4177d
commit b1bdc38423
7 changed files with 1322 additions and 664 deletions
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2
aws/cl_zcash/build/scripts/synth_cl_zcash.tcl
View File

@ -75,6 +75,8 @@ read_ip [ list \
puts "AWS FPGA: Generating IP blocks";
upgrade_ip [get_ips *]
set_property generate_synth_checkpoint false [get_files axis_dwidth_converter_64_to_8.xci]
set_property generate_synth_checkpoint false [get_files axis_dwidth_converter_8_to_64.xci]
set_property generate_synth_checkpoint false [get_files axis_dwidth_converter_4_to_8.xci]

4
aws/cl_zcash/ip/cl_sde_ip_setup.tcl
View File

@ -10,6 +10,7 @@ axis_dwidth_converter_48_to_8/axis_dwidth_converter_48_to_8.xci
axis_dwidth_converter_4_to_8/axis_dwidth_converter_4_to_8.xci
axis_dwidth_converter_8_to_4/axis_dwidth_converter_8_to_4.xci
ila_2/ila_2.xci
fifo_generator_0/fifo_generator_0.xci
}
upgrade_ip [get_ips *]
@ -21,4 +22,5 @@ generate_target all [get_files axis_dwidth_converter_8_to_64/axis_dwidth_conver
generate_target all [get_files axis_dwidth_converter_48_to_8/axis_dwidth_converter_48_to_8.xci]
generate_target all [get_files axis_dwidth_converter_4_to_8/axis_dwidth_converter_4_to_8.xci]
generate_target all [get_files axis_dwidth_converter_8_to_4/axis_dwidth_converter_8_to_4.xci]
generate_target all [get_files ila_2/ila_2.xci]
generate_target all [get_files ila_2/ila_2.xci]
generate_target all [get_files fifo_generator_0/fifo_generator_0.xci]

583
aws/cl_zcash/ip/fifo_generator_0.xci Normal file
View File

@ -0,0 +1,583 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>fifo_generator_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/>
<spirit:configurableElementValues>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">66</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">66</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Synchronous_Reset</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">virtexuplus</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcvu9p</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">flga2104</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_axis" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_rach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_rdch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wdch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wrch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.INTERFACE_TYPE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Performance_Options" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
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</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>

3
aws/cl_zcash/ip/mk_clean
View File

@ -6,4 +6,5 @@ rm -rf axis_dwidth_converter_48_to_8/
rm -rf axi_fifo_mm_s_lite/
rm -rf axis_dwidth_converter_4_to_8/
rm -rf axis_dwidth_converter_8_to_4/
rm -rf ila_2/
rm -rf ila_2/
rm -rf fifo_generator_0.xci/

2
aws/cl_zcash/ip/run_cl_sde_ip_flow
View File

@ -6,6 +6,7 @@ mkdir axis_dwidth_converter_48_to_8
mkdir axis_dwidth_converter_4_to_8
mkdir axis_dwidth_converter_8_to_4
mkdir ila_2
mkdir fifo_generator_0
cp axi_fifo_mm_s_0.xci axi_fifo_mm_s_0/axi_fifo_mm_s_0.xci
cp axi_fifo_mm_s_lite.xci axi_fifo_mm_s_lite/axi_fifo_mm_s_lite.xci
@ -15,6 +16,7 @@ cp axis_dwidth_converter_48_to_8.xci axis_dwidth_converter_48_to_8/axis_dwidth_c
cp axis_dwidth_converter_4_to_8.xci axis_dwidth_converter_4_to_8/axis_dwidth_converter_4_to_8.xci
cp axis_dwidth_converter_8_to_4.xci axis_dwidth_converter_8_to_4/axis_dwidth_converter_8_to_4.xci
cp ila_2.xci ila_2/ila_2.xci
cp fifo_generator_0.xci fifo_generator_0/fifo_generator_0.xci
vivado -mode batch -source cl_sde_ip_setup.tcl

839
zcash_fpga/src/rtl/control/control_top.sv
View File

@ -1,415 +1,426 @@
/*
This module is the top level for the FPGA interface to SW. It takes in commands
from SW, running the commands, and then building the replies back to SW.
Copyright (C) 2019 Benjamin Devlin and Zcash Foundation
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
module control_top
import zcash_fpga_pkg::*, equihash_pkg::*;
#(
parameter DAT_BYTS = 8, // Only tested at 8 byte data width
parameter [63:0] BUILD_HOST = "test",
parameter [63:0] BUILD_DATE = "20180311"
)(
input i_clk, i_rst,
// User is able to reset custom logic on FPGA
output logic o_usr_rst,
// Interface inputs and outputs
if_axi_stream.sink rx_if,
if_axi_stream.source tx_if,
// Used when verifying equihash soltion
if_axi_stream.source o_equihash_if,
input equihash_bm_t i_equihash_mask,
input i_equihash_mask_val,
// Driving secp256k1 core
if_axi_stream.source o_secp256k1_if,
if_axi_stream.sink i_secp256k1_if
);
localparam DAT_BITS = DAT_BYTS*8;
localparam MAX_BYT_MSG = 256; // Max bytes in a reply message
logic rst_int;
always_comb rst_int = i_rst || o_usr_rst;
// When a command comes in it is put through a clock crossing, and then stored in a command
// FIFO to be processed. There are two FIFOS - one for processing status / reset commands (msg_type == 0),
// and one for everything else. This is so we can process these messages even if we are
// running something else.
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BYTS(1)) rx_int0_if (i_clk);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BYTS(1)) rx_int1_if (i_clk);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BYTS(1)) rx_typ0_if (i_clk);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BYTS(1)) rx_typ1_if (i_clk);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BYTS(1)) tx_arb_in_if [2] (i_clk);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BYTS(1)) tx_int_if (i_clk);
typedef enum {TYP0_IDLE = 0,
TYP0_SEND_STATUS = 1,
TYP0_RESET_FPGA = 2,
TYP0_SEND_IGNORE = 3,
TYP0_IGNORE = 4} typ0_msg_state_t;
typ0_msg_state_t typ0_msg_state;
typedef enum {TYP1_IDLE = 0,
TYP1_VERIFY_EQUIHASH = 1,
TYP1_VERIFY_SECP256K1 = 2,
TYP1_SEND_IGNORE = 3,
TYP1_IGNORE = 4} typ1_msg_state_t;
typ1_msg_state_t typ1_msg_state;
header_t header, header0, header1, header0_l, header1_l;
logic verify_equihash_rpl_val;
logic [7:0] reset_cnt;
logic [$clog2(MAX_BYT_MSG) -1:0] typ0_wrd_cnt, typ1_wrd_cnt;
logic [MAX_BYT_MSG*8 -1:0] typ0_msg, typ1_msg;
logic [63:0] equihash_index;
logic equihash_index_val, rx_typ1_if_rdy;
logic sop_l, eop_l;
logic eop_typ0_l, eop_typ1_l;
fpga_state_t fpga_state;
always_comb begin
fpga_state = 0;
fpga_state.error = 0;
fpga_state.typ1_state = typ1_msg_state;
header = rx_if.dat;
header0 = rx_typ0_if.dat;
header1 = rx_typ1_if.dat;
end
// Logic for processing msg_type == 0 messages
always_ff @ (posedge i_clk) begin
if (i_rst) begin
rx_typ0_if.rdy <= 0;
typ0_msg_state <= TYP0_IDLE;
header0_l <= 0;
tx_arb_in_if[0].reset_source();
typ0_wrd_cnt <= 0;
o_usr_rst <= 0;
reset_cnt <= 0;
eop_typ0_l <= 0;
typ0_msg <= 0;
end else begin
rx_typ0_if.rdy <= 1;
case (typ0_msg_state)
TYP0_IDLE: begin
if (rx_typ0_if.val && rx_typ0_if.rdy) begin
header0_l <= header0;
rx_typ0_if.rdy <= 0;
case(header0.cmd)
RESET_FPGA: begin
typ0_msg <= get_fpga_reset_rpl();
typ0_wrd_cnt <= $bits(fpga_reset_rpl_t)/8;
typ0_msg_state <= TYP0_RESET_FPGA;
o_usr_rst <= 1;
reset_cnt <= -1;
end
FPGA_STATUS: begin
typ0_msg <= get_fpga_status_rpl(BUILD_HOST, BUILD_DATE, fpga_state);
typ0_wrd_cnt <= $bits(fpga_status_rpl_t)/8;
typ0_msg_state <= TYP0_SEND_STATUS;
end
default: begin
typ0_msg <= get_fpga_ignore_rpl(header0);
typ0_wrd_cnt <= $bits(fpga_ignore_rpl_t)/8;
eop_typ0_l <= rx_typ0_if.eop;
typ0_msg_state <= TYP0_SEND_IGNORE;
end
endcase
end
end
TYP0_SEND_STATUS: begin
send_typ0_message($bits(fpga_status_rpl_t)/8);
end
TYP0_RESET_FPGA: begin
rx_typ0_if.rdy <= 0;
if (reset_cnt != 0)
reset_cnt <= reset_cnt - 1;
if (reset_cnt >> 4 == 0)
o_usr_rst <= 0;
if (reset_cnt == 0) begin
send_typ0_message($bits(fpga_reset_rpl_t)/8);
end
end
TYP0_SEND_IGNORE: begin
send_typ0_message($bits(fpga_ignore_rpl_t)/8, eop_typ0_l ? TYP0_IDLE : TYP0_IGNORE);
end
TYP0_IGNORE: begin
rx_typ0_if.rdy <= 1;
if (rx_typ0_if.rdy && rx_typ0_if.eop && rx_typ0_if.val)
typ0_msg_state <= TYP0_IDLE;
end
endcase
end
end
// Task to help build reply messages. Assume no message will be more than MAX_BYT_MSG bytes
task send_typ0_message(input logic [$clog2(MAX_BYT_MSG)-1:0] msg_size,
input typ0_msg_state_t nxt_state = TYP0_IDLE);
rx_typ0_if.rdy <= 0;
if (~tx_arb_in_if[0].val || (tx_arb_in_if[0].rdy && tx_arb_in_if[0].val)) begin
tx_arb_in_if[0].dat <= typ0_msg;
tx_arb_in_if[0].val <= 1;
tx_arb_in_if[0].sop <= typ0_wrd_cnt == msg_size;
tx_arb_in_if[0].eop <= typ0_wrd_cnt <= DAT_BYTS;
tx_arb_in_if[0].mod <= typ0_wrd_cnt < DAT_BYTS ? typ0_wrd_cnt : 0;
typ0_wrd_cnt <= (typ0_wrd_cnt > DAT_BYTS) ? (typ0_wrd_cnt - DAT_BYTS) : 0;
typ0_msg <= typ0_msg >> DAT_BITS;
if (typ0_wrd_cnt == 0) begin
tx_arb_in_if[0].val <= 0;
typ0_msg_state <= nxt_state;
end
end
endtask
always_comb begin
case(typ1_msg_state)
TYP1_IDLE: rx_typ1_if.rdy = rx_typ1_if_rdy;
VERIFY_EQUIHASH: rx_typ1_if.rdy = rx_typ1_if_rdy && o_equihash_if.rdy;
default: rx_typ1_if.rdy = rx_typ1_if_rdy;
endcase
end
always_comb begin
i_secp256k1_if.rdy = (typ1_msg_state == TYP1_VERIFY_SECP256K1) && tx_arb_in_if[1].rdy;
end
// Logic for processing msg_type == 1 messages
always_ff @ (posedge i_clk) begin
if (rst_int) begin
rx_typ1_if_rdy <= 0;
typ1_msg_state <= TYP1_IDLE;
header1_l <= 0;
tx_arb_in_if[1].reset_source();
o_equihash_if.reset_source();
typ1_wrd_cnt <= 0;
equihash_index <= 0;
verify_equihash_rpl_val <= 0;
equihash_index_val <= 0;
sop_l <= 0;
eop_typ1_l <= 0;
typ1_msg <= 0;
o_secp256k1_if.reset_source();
eop_l <= 0;
end else begin
case (typ1_msg_state)
TYP1_IDLE: begin
rx_typ1_if_rdy <= 1;
verify_equihash_rpl_val <= 0;
equihash_index_val <= 0;
sop_l <= 0;
if (rx_typ1_if.val && rx_typ1_if.rdy) begin
header1_l <= header1;
rx_typ1_if_rdy <= 0;
case(header1.cmd)
VERIFY_EQUIHASH: begin
rx_typ1_if_rdy <= 1;
typ1_wrd_cnt <= $bits(verify_equihash_rpl_t)/8;
typ1_msg_state <= TYP1_VERIFY_EQUIHASH;
if (~ENB_VERIFY_EQUIHASH) begin
typ1_msg <= get_fpga_ignore_rpl(header1);
typ1_wrd_cnt <= $bits(fpga_ignore_rpl_t)/8;
eop_typ1_l <= rx_typ1_if.eop;
typ1_msg_state <= TYP1_SEND_IGNORE;
end
end
VERIFY_SECP256K1_SIG: begin
rx_typ1_if_rdy <= o_secp256k1_if.rdy;
o_secp256k1_if.copy_if(rx_typ1_if.dat, rx_typ1_if.val, rx_typ1_if.sop, rx_typ1_if.eop);
typ1_msg_state <= TYP1_VERIFY_SECP256K1;
if (~ENB_VERIFY_SECP256K1_SIG) begin
typ1_msg <= get_fpga_ignore_rpl(header1);
typ1_wrd_cnt <= $bits(fpga_ignore_rpl_t)/8;
eop_typ1_l <= rx_typ1_if.eop;
typ1_msg_state <= TYP1_SEND_IGNORE;
end
end
default: begin
typ1_msg <= get_fpga_ignore_rpl(header1);
typ1_wrd_cnt <= $bits(fpga_ignore_rpl_t)/8;
eop_typ1_l <= rx_typ1_if.eop;
typ1_msg_state <= TYP1_SEND_IGNORE;
end
endcase
end
end
TYP1_VERIFY_EQUIHASH: begin
if (rx_typ1_if.eop && rx_typ1_if.val && rx_typ1_if.rdy)
rx_typ1_if_rdy <= 0;
if (~equihash_index_val) begin
if (rx_typ1_if.rdy && rx_typ1_if.val) begin
equihash_index <= rx_typ1_if.dat;
equihash_index_val <= 1;
end
end else begin
// First load block data (this might be bypassed if loading from memory)
if (~o_equihash_if.val || (o_equihash_if.rdy && o_equihash_if.val)) begin
o_equihash_if.copy_if(rx_typ1_if.dat, rx_typ1_if.val, ~sop_l, rx_typ1_if.eop, rx_typ1_if.err, rx_typ1_if.mod);
// First cycle has .sop set
if (rx_typ1_if.val) sop_l <= 1;
end
end
// Wait for reply with result
if (i_equihash_mask_val && ~verify_equihash_rpl_val) begin
typ1_msg <= get_verify_equihash_rpl(i_equihash_mask, equihash_index);
verify_equihash_rpl_val <= 1;
end
// Send result
if (verify_equihash_rpl_val) begin
send_typ1_message($bits(verify_equihash_rpl_t)/8);
end
end
// The command header is sent through to output
TYP1_VERIFY_SECP256K1: begin
rx_typ1_if_rdy <= o_secp256k1_if.rdy;
if (~eop_l && ~o_secp256k1_if.val || (o_secp256k1_if.rdy && o_secp256k1_if.val)) begin
o_secp256k1_if.copy_if(rx_typ1_if.dat, rx_typ1_if.val, rx_typ1_if.sop, rx_typ1_if.eop, rx_typ1_if.err, rx_typ1_if.mod);
eop_l <= rx_typ1_if.eop && rx_typ1_if.val;
if (rx_typ1_if.eop && rx_typ1_if.val)
rx_typ1_if_rdy <= 0;
end
if (~tx_arb_in_if[1].val || (tx_arb_in_if[1].rdy && tx_arb_in_if[1].val)) begin
tx_arb_in_if[1].copy_if(i_secp256k1_if.dat, i_secp256k1_if.val, i_secp256k1_if.sop, i_secp256k1_if.eop, 0, i_secp256k1_if.mod);
end
if (tx_arb_in_if[1].val && tx_arb_in_if[1].rdy && tx_arb_in_if[1].eop) begin
typ1_msg_state <= TYP1_IDLE;
end
end
TYP1_SEND_IGNORE: begin
send_typ1_message($bits(fpga_ignore_rpl_t)/8, eop_typ1_l ? TYP1_IDLE : TYP1_IGNORE);
end
TYP1_IGNORE: begin
rx_typ1_if_rdy <= 1;
if (rx_typ1_if.rdy && rx_typ1_if.eop && rx_typ1_if.val)
typ1_msg_state <= TYP1_IDLE;
end
endcase
end
end
// Task to help build reply messages. Assume no message will be more than MAX_BYT_MSG bytes
task send_typ1_message(input logic [$clog2(MAX_BYT_MSG)-1:0] msg_size,
input typ1_msg_state_t nxt_state = TYP1_IDLE);
rx_typ1_if_rdy <= 0;
if (~tx_arb_in_if[1].val || (tx_arb_in_if[1].rdy && tx_arb_in_if[1].val)) begin
tx_arb_in_if[1].dat <= typ1_msg;
tx_arb_in_if[1].val <= 1;
tx_arb_in_if[1].sop <= typ1_wrd_cnt == msg_size;
tx_arb_in_if[1].eop <= typ1_wrd_cnt <= DAT_BYTS;
tx_arb_in_if[1].mod <= typ1_wrd_cnt < DAT_BYTS ? typ1_wrd_cnt : 0;
typ1_wrd_cnt <= (typ1_wrd_cnt > DAT_BYTS) ? (typ1_wrd_cnt - DAT_BYTS) : 0;
typ1_msg <= typ1_msg >> DAT_BITS;
if (typ1_wrd_cnt == 0) begin
tx_arb_in_if[1].val <= 0;
typ1_msg_state <= nxt_state;
end
end
endtask
// Logic to mux the packet depending on its command type
logic msg_type, msg_type_l;
always_comb begin
rx_int0_if.copy_if_comb(rx_if.dat, 0, rx_if.sop, rx_if.eop, 0, rx_if.mod, 0);
rx_int1_if.copy_if_comb(rx_if.dat, 0, rx_if.sop, rx_if.eop, 0, rx_if.mod, 0);
rx_if.rdy = 0;
if (rx_if.sop && rx_if.val) begin
if(header.cmd[8 +: 8] == 8'd0) begin
msg_type = 0;
rx_int0_if.val = rx_if.val;
rx_if.rdy = rx_int0_if.rdy;
end else begin
msg_type = 1;
rx_int1_if.val = rx_if.val;
rx_if.rdy = rx_int1_if.rdy;
end
end else begin
rx_int0_if.val = rx_if.val && (msg_type_l == 0);
rx_int1_if.val = rx_if.val && (msg_type_l == 1);
rx_if.rdy = (msg_type_l == 0) ? rx_int0_if.rdy : rx_int1_if.rdy;
msg_type = msg_type_l;
end
end
always_ff @ (posedge i_clk) begin
if (i_rst) begin
msg_type_l <= 0;
end else begin
if (rx_if.val && rx_if.rdy) begin
if (rx_if.sop)
msg_type_l <= msg_type;
end
end
end
// FIFO control queues for different message types
axi_stream_fifo #(
.SIZE ( 64 ),
.DAT_BITS ( DAT_BITS )
)
cmd_fifo0 (
.i_clk ( i_clk ),
.i_rst ( rst_int ),
.i_axi ( rx_int0_if ),
.o_axi ( rx_typ0_if )
);
axi_stream_fifo #(
.SIZE ( 64 ),
.DAT_BITS ( DAT_BITS )
)
cmd_fifo1 (
.i_clk ( i_clk ),
.i_rst ( rst_int ),
.i_axi ( rx_int1_if ),
.o_axi ( rx_typ1_if )
);
// Arbitrator for sending messages back
packet_arb # (
.NUM_IN ( 2 ),
.DAT_BYTS ( DAT_BYTS ),
.CTL_BITS ( 8 )
)
packet_arb_tx (
.i_clk ( i_clk ),
.i_rst ( rst_int ),
.i_axi ( tx_arb_in_if ),
.o_axi ( tx_if )
);
/*
This module is the top level for the FPGA interface to SW. It takes in commands
from SW, running the commands, and then building the replies back to SW.
Copyright (C) 2019 Benjamin Devlin and Zcash Foundation
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
module control_top
import zcash_fpga_pkg::*, equihash_pkg::*;
#(
parameter DAT_BYTS = 8, // Only tested at 8 byte data width
parameter [63:0] BUILD_HOST = "test",
parameter [63:0] BUILD_DATE = "20180311"
)(
input i_clk, i_rst,
// User is able to reset custom logic on FPGA
output logic o_usr_rst,
// Interface inputs and outputs
if_axi_stream.sink rx_if,
if_axi_stream.source tx_if,
// Used when verifying equihash soltion
if_axi_stream.source o_equihash_if,
input equihash_bm_t i_equihash_mask,
input i_equihash_mask_val,
// Driving secp256k1 core
if_axi_stream.source o_secp256k1_if,
if_axi_stream.sink i_secp256k1_if
);
localparam DAT_BITS = DAT_BYTS*8;
localparam MAX_BYT_MSG = 256; // Max bytes in a reply message
logic rst_int;
always_comb rst_int = i_rst || o_usr_rst;
// When a command comes in it is put through a clock crossing, and then stored in a command
// FIFO to be processed. There are two FIFOS - one for processing status / reset commands (msg_type == 0),
// and one for everything else. This is so we can process these messages even if we are
// running something else.
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BYTS(1)) rx_int0_if (i_clk);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BYTS(1)) rx_int1_if (i_clk);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BYTS(1)) rx_typ0_if (i_clk);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BYTS(1)) rx_typ1_if (i_clk);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BYTS(1)) tx_arb_in_if [2] (i_clk);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BYTS(1)) tx_int_if (i_clk);
typedef enum {TYP0_IDLE = 0,
TYP0_SEND_STATUS = 1,
TYP0_RESET_FPGA = 2,
TYP0_SEND_IGNORE = 3,
TYP0_IGNORE = 4} typ0_msg_state_t;
typ0_msg_state_t typ0_msg_state;
typedef enum {TYP1_IDLE = 0,
TYP1_VERIFY_EQUIHASH = 1,
TYP1_VERIFY_SECP256K1 = 2,
TYP1_SEND_IGNORE = 3,
TYP1_IGNORE = 4} typ1_msg_state_t;
typ1_msg_state_t typ1_msg_state;
header_t header, header0, header1, header0_l, header1_l;
logic verify_equihash_rpl_val;
logic [7:0] reset_cnt;
logic [$clog2(MAX_BYT_MSG) -1:0] typ0_wrd_cnt, typ1_wrd_cnt;
logic [MAX_BYT_MSG*8 -1:0] typ0_msg, typ1_msg;
logic [63:0] equihash_index;
logic equihash_index_val, rx_typ1_if_rdy;
logic sop_l, eop_l;
logic eop_typ0_l, eop_typ1_l;
fpga_state_t fpga_state;
always_comb begin
fpga_state = 0;
fpga_state.error = 0;
fpga_state.typ1_state = typ1_msg_state;
header = rx_if.dat;
header0 = rx_typ0_if.dat;
header1 = rx_typ1_if.dat;
end
// Logic for processing msg_type == 0 messages
always_ff @ (posedge i_clk) begin
if (i_rst) begin
rx_typ0_if.rdy <= 0;
typ0_msg_state <= TYP0_IDLE;
header0_l <= 0;
tx_arb_in_if[0].reset_source();
typ0_wrd_cnt <= 0;
o_usr_rst <= 0;
reset_cnt <= 0;
eop_typ0_l <= 0;
typ0_msg <= 0;
end else begin
rx_typ0_if.rdy <= 1;
if (tx_arb_in_if[0].rdy) tx_arb_in_if[0].val <= 0;
case (typ0_msg_state)
TYP0_IDLE: begin
if (rx_typ0_if.val && rx_typ0_if.rdy) begin
header0_l <= header0;
rx_typ0_if.rdy <= 0;
case(header0.cmd)
RESET_FPGA: begin
typ0_msg <= get_fpga_reset_rpl();
typ0_wrd_cnt <= $bits(fpga_reset_rpl_t)/8;
typ0_msg_state <= TYP0_RESET_FPGA;
o_usr_rst <= 1;
reset_cnt <= -1;
end
FPGA_STATUS: begin
typ0_msg <= get_fpga_status_rpl(BUILD_HOST, BUILD_DATE, fpga_state);
typ0_wrd_cnt <= $bits(fpga_status_rpl_t)/8;
typ0_msg_state <= TYP0_SEND_STATUS;
end
default: begin
typ0_msg <= get_fpga_ignore_rpl(header0);
typ0_wrd_cnt <= $bits(fpga_ignore_rpl_t)/8;
eop_typ0_l <= rx_typ0_if.eop;
typ0_msg_state <= TYP0_SEND_IGNORE;
end
endcase
end
end
TYP0_SEND_STATUS: begin
send_typ0_message($bits(fpga_status_rpl_t)/8);
end
TYP0_RESET_FPGA: begin
rx_typ0_if.rdy <= 0;
if (reset_cnt != 0)
reset_cnt <= reset_cnt - 1;
if (reset_cnt >> 4 == 0)
o_usr_rst <= 0;
if (reset_cnt == 0) begin
send_typ0_message($bits(fpga_reset_rpl_t)/8);
end
end
TYP0_SEND_IGNORE: begin
send_typ0_message($bits(fpga_ignore_rpl_t)/8, eop_typ0_l ? TYP0_IDLE : TYP0_IGNORE);
end
TYP0_IGNORE: begin
rx_typ0_if.rdy <= 1;
if (rx_typ0_if.rdy && rx_typ0_if.eop && rx_typ0_if.val)
typ0_msg_state <= TYP0_IDLE;
end
endcase
end
end
// Task to help build reply messages. Assume no message will be more than MAX_BYT_MSG bytes
task send_typ0_message(input logic [$clog2(MAX_BYT_MSG)-1:0] msg_size,
input typ0_msg_state_t nxt_state = TYP0_IDLE);
rx_typ0_if.rdy <= 0;
if (~tx_arb_in_if[0].val || (tx_arb_in_if[0].rdy && tx_arb_in_if[0].val)) begin
tx_arb_in_if[0].dat <= typ0_msg;
tx_arb_in_if[0].val <= 1;
tx_arb_in_if[0].sop <= typ0_wrd_cnt == msg_size;
tx_arb_in_if[0].eop <= typ0_wrd_cnt <= DAT_BYTS;
tx_arb_in_if[0].mod <= typ0_wrd_cnt < DAT_BYTS ? typ0_wrd_cnt : 0;
typ0_wrd_cnt <= (typ0_wrd_cnt > DAT_BYTS) ? (typ0_wrd_cnt - DAT_BYTS) : 0;
typ0_msg <= typ0_msg >> DAT_BITS;
if (typ0_wrd_cnt == 0) begin
tx_arb_in_if[0].val <= 0;
typ0_msg_state <= nxt_state;
end
end
endtask
always_comb begin
case(typ1_msg_state)
TYP1_IDLE: rx_typ1_if.rdy = rx_typ1_if_rdy;
VERIFY_EQUIHASH: rx_typ1_if.rdy = rx_typ1_if_rdy && o_equihash_if.rdy;
default: rx_typ1_if.rdy = rx_typ1_if_rdy;
endcase
end
always_comb begin
i_secp256k1_if.rdy = (typ1_msg_state == TYP1_VERIFY_SECP256K1) && (~tx_arb_in_if[1].val || (tx_arb_in_if[1].rdy && tx_arb_in_if[1].val));
end
// Logic for processing msg_type == 1 messages
always_ff @ (posedge i_clk) begin
if (rst_int) begin
rx_typ1_if_rdy <= 0;
typ1_msg_state <= TYP1_IDLE;
header1_l <= 0;
tx_arb_in_if[1].reset_source();
o_equihash_if.reset_source();
typ1_wrd_cnt <= 0;
equihash_index <= 0;
verify_equihash_rpl_val <= 0;
equihash_index_val <= 0;
sop_l <= 0;
eop_typ1_l <= 0;
typ1_msg <= 0;
o_secp256k1_if.reset_source();
eop_l <= 0;
end else begin
if (tx_arb_in_if[1].rdy) tx_arb_in_if[1].val <= 0;
case (typ1_msg_state)
TYP1_IDLE: begin
rx_typ1_if_rdy <= 1;
verify_equihash_rpl_val <= 0;
equihash_index_val <= 0;
sop_l <= 0;
if (rx_typ1_if.val && rx_typ1_if.rdy) begin
header1_l <= header1;
rx_typ1_if_rdy <= 0;
case(header1.cmd)
VERIFY_EQUIHASH: begin
rx_typ1_if_rdy <= 1;
typ1_wrd_cnt <= $bits(verify_equihash_rpl_t)/8;
typ1_msg_state <= TYP1_VERIFY_EQUIHASH;
if (~ENB_VERIFY_EQUIHASH) begin
typ1_msg <= get_fpga_ignore_rpl(header1);
typ1_wrd_cnt <= $bits(fpga_ignore_rpl_t)/8;
eop_typ1_l <= rx_typ1_if.eop;
typ1_msg_state <= TYP1_SEND_IGNORE;
end
end
VERIFY_SECP256K1_SIG: begin
rx_typ1_if_rdy <= o_secp256k1_if.rdy;
o_secp256k1_if.copy_if(rx_typ1_if.dat, rx_typ1_if.val, rx_typ1_if.sop, rx_typ1_if.eop);
typ1_msg_state <= TYP1_VERIFY_SECP256K1;
if (~ENB_VERIFY_SECP256K1_SIG) begin
typ1_msg <= get_fpga_ignore_rpl(header1);
typ1_wrd_cnt <= $bits(fpga_ignore_rpl_t)/8;
eop_typ1_l <= rx_typ1_if.eop;
typ1_msg_state <= TYP1_SEND_IGNORE;
end
end
default: begin
typ1_msg <= get_fpga_ignore_rpl(header1);
typ1_wrd_cnt <= $bits(fpga_ignore_rpl_t)/8;
eop_typ1_l <= rx_typ1_if.eop;
typ1_msg_state <= TYP1_SEND_IGNORE;
end
endcase
end
end
TYP1_VERIFY_EQUIHASH: begin
if (rx_typ1_if.eop && rx_typ1_if.val && rx_typ1_if.rdy)
rx_typ1_if_rdy <= 0;
if (~equihash_index_val) begin
if (rx_typ1_if.rdy && rx_typ1_if.val) begin
equihash_index <= rx_typ1_if.dat;
equihash_index_val <= 1;
end
end else begin
// First load block data (this might be bypassed if loading from memory)
if (~o_equihash_if.val || (o_equihash_if.rdy && o_equihash_if.val)) begin
o_equihash_if.copy_if(rx_typ1_if.dat, rx_typ1_if.val, ~sop_l, rx_typ1_if.eop, rx_typ1_if.err, rx_typ1_if.mod);
// First cycle has .sop set
if (rx_typ1_if.val) sop_l <= 1;
end
end
// Wait for reply with result
if (i_equihash_mask_val && ~verify_equihash_rpl_val) begin
typ1_msg <= get_verify_equihash_rpl(i_equihash_mask, equihash_index);
verify_equihash_rpl_val <= 1;
end
// Send result
if (verify_equihash_rpl_val) begin
send_typ1_message($bits(verify_equihash_rpl_t)/8);
end
end
// The command header is sent through to output
TYP1_VERIFY_SECP256K1: begin
rx_typ1_if_rdy <= o_secp256k1_if.rdy;
if (~eop_l && ~o_secp256k1_if.val || (o_secp256k1_if.rdy && o_secp256k1_if.val)) begin
o_secp256k1_if.copy_if(rx_typ1_if.dat, rx_typ1_if.val, rx_typ1_if.sop, rx_typ1_if.eop, rx_typ1_if.err, rx_typ1_if.mod);
eop_l <= rx_typ1_if.eop && rx_typ1_if.val;
if (rx_typ1_if.eop && rx_typ1_if.val)
rx_typ1_if_rdy <= 0;
end
if (~tx_arb_in_if[1].val || (tx_arb_in_if[1].rdy && tx_arb_in_if[1].val)) begin
tx_arb_in_if[1].val <= i_secp256k1_if.val;
tx_arb_in_if[1].dat <= i_secp256k1_if.dat;
tx_arb_in_if[1].mod <= i_secp256k1_if.mod;
tx_arb_in_if[1].sop <= i_secp256k1_if.sop;
tx_arb_in_if[1].eop <= i_secp256k1_if.eop;
tx_arb_in_if[1].err <= i_secp256k1_if.err;
end
if (tx_arb_in_if[1].val && tx_arb_in_if[1].rdy && tx_arb_in_if[1].eop) begin
typ1_msg_state <= TYP1_IDLE;
end
end
TYP1_SEND_IGNORE: begin
send_typ1_message($bits(fpga_ignore_rpl_t)/8, eop_typ1_l ? TYP1_IDLE : TYP1_IGNORE);
end
TYP1_IGNORE: begin
rx_typ1_if_rdy <= 1;
if (rx_typ1_if.rdy && rx_typ1_if.eop && rx_typ1_if.val)
typ1_msg_state <= TYP1_IDLE;
end
endcase
end
end
// Task to help build reply messages. Assume no message will be more than MAX_BYT_MSG bytes
task send_typ1_message(input logic [$clog2(MAX_BYT_MSG)-1:0] msg_size,
input typ1_msg_state_t nxt_state = TYP1_IDLE);
rx_typ1_if_rdy <= 0;
if (~tx_arb_in_if[1].val || (tx_arb_in_if[1].rdy && tx_arb_in_if[1].val)) begin
tx_arb_in_if[1].dat <= typ1_msg;
tx_arb_in_if[1].val <= 1;
tx_arb_in_if[1].sop <= typ1_wrd_cnt == msg_size;
tx_arb_in_if[1].eop <= typ1_wrd_cnt <= DAT_BYTS;
tx_arb_in_if[1].mod <= typ1_wrd_cnt < DAT_BYTS ? typ1_wrd_cnt : 0;
typ1_wrd_cnt <= (typ1_wrd_cnt > DAT_BYTS) ? (typ1_wrd_cnt - DAT_BYTS) : 0;
typ1_msg <= typ1_msg >> DAT_BITS;
if (typ1_wrd_cnt == 0) begin
tx_arb_in_if[1].val <= 0;
typ1_msg_state <= nxt_state;
end
end
endtask
// Logic to mux the packet depending on its command type
logic msg_type, msg_type_l;
always_comb begin
rx_int0_if.copy_if_comb(rx_if.dat, 0, rx_if.sop, rx_if.eop, 0, rx_if.mod, 0);
rx_int1_if.copy_if_comb(rx_if.dat, 0, rx_if.sop, rx_if.eop, 0, rx_if.mod, 0);
rx_if.rdy = 0;
if (rx_if.sop && rx_if.val) begin
if(header.cmd[8 +: 8] == 8'd0) begin
msg_type = 0;
rx_int0_if.val = rx_if.val;
rx_if.rdy = rx_int0_if.rdy;
end else begin
msg_type = 1;
rx_int1_if.val = rx_if.val;
rx_if.rdy = rx_int1_if.rdy;
end
end else begin
rx_int0_if.val = rx_if.val && (msg_type_l == 0);
rx_int1_if.val = rx_if.val && (msg_type_l == 1);
rx_if.rdy = (msg_type_l == 0) ? rx_int0_if.rdy : rx_int1_if.rdy;
msg_type = msg_type_l;
end
end
always_ff @ (posedge i_clk) begin
if (i_rst) begin
msg_type_l <= 0;
end else begin
if (rx_if.val && rx_if.rdy) begin
if (rx_if.sop)
msg_type_l <= msg_type;
end
end
end
// FIFO control queues for different message types
axi_stream_fifo #(
.SIZE ( 64 ),
.DAT_BITS ( DAT_BITS )
)
cmd_fifo0 (
.i_clk ( i_clk ),
.i_rst ( rst_int ),
.i_axi ( rx_int0_if ),
.o_axi ( rx_typ0_if )
);
axi_stream_fifo #(
.SIZE ( 64 ),
.DAT_BITS ( DAT_BITS )
)
cmd_fifo1 (
.i_clk ( i_clk ),
.i_rst ( rst_int ),
.i_axi ( rx_int1_if ),
.o_axi ( rx_typ1_if )
);
// Arbitrator for sending messages back
packet_arb # (
.NUM_IN ( 2 ),
.DAT_BYTS ( DAT_BYTS ),
.CTL_BITS ( 8 )
)
packet_arb_tx (
.i_clk ( i_clk ),
.i_rst ( rst_int ),
.i_axi ( tx_arb_in_if ),
.o_axi ( tx_if )
);
endmodule

553
zcash_fpga/src/rtl/top/zcash_fpga_top.sv
View File

@ -1,249 +1,306 @@
/*
This is the top level of the Zcash FPGA acceleration engine.
We have different interfaces that are all muxed together to provide FPGA
with commands and data.
Copyright (C) 2019 Benjamin Devlin and Zcash Foundation
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
module zcash_fpga_top
import zcash_fpga_pkg::*, equihash_pkg::*;
#(
parameter DAT_BYTS = 8 // Only tested at 8 byte data width
)(
// Clocks and resets
input i_clk_100, i_rst_100, // 100 MHz clock
input i_clk_200, i_rst_200, // 200 MHz clock
input i_clk_300, i_rst_300, // 300 MHz clock
input i_clk_if, i_rst_if, // Command interface clock (e.g. UART / PCIe)
// AXI lite interface
if_axi_lite.sink axi_lite_if,
// Command interface input and output
if_axi_stream.sink rx_if,
if_axi_stream.source tx_if
);
localparam CTL_BITS = 8;
// These are the resets combined with the user reset
logic usr_rst_100, rst_100;
logic usr_rst_200, rst_200;
logic usr_rst_300, rst_300;
logic usr_rst;
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) equihash_axi(i_clk_if);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) equihash_axi_s(i_clk_100);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) secp256k1_out_if(i_clk_if);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) secp256k1_in_if(i_clk_if);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) secp256k1_out_if_s(i_clk_200);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) secp256k1_in_if_s(i_clk_200);
equihash_bm_t equihash_mask, equihash_mask_s;
logic equihash_mask_val, equihash_mask_val_s;
// Synchronize resets from interface into each clock domain
synchronizer #(.DAT_BITS ( 1 ), .NUM_CLKS ( 3 )) rst_100_sync (
.i_clk_a ( i_clk_if ),
.i_clk_b ( i_clk_100 ),
.i_dat_a ( usr_rst ),
.o_dat_b ( usr_rst_100 )
);
always_ff @ (posedge i_clk_200) rst_200 <= i_rst_200 || usr_rst_200;
synchronizer #(.DAT_BITS ( 1 ), .NUM_CLKS ( 3 )) rst_200_sync (
.i_clk_a ( i_clk_if ),
.i_clk_b ( i_clk_200 ),
.i_dat_a ( usr_rst ),
.o_dat_b ( usr_rst_200 )
);
always_ff @ (posedge i_clk_100) rst_100 <= i_rst_100 || usr_rst_100;
synchronizer #(.DAT_BITS ( 1 ), .NUM_CLKS ( 3 )) rst_300_sync (
.i_clk_a ( i_clk_if ),
.i_clk_b ( i_clk_300 ),
.i_dat_a ( usr_rst ),
.o_dat_b ( usr_rst_300 )
);
always_ff @ (posedge i_clk_300) rst_300 <= i_rst_300 || usr_rst_300;
// This block takes in the interface signals and interfaces with other blocks
// This runs on the same clock as the interface but we might need to change data width
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(1)) tx_int_if [1:0] (i_clk_if);
control_top #(
.DAT_BYTS ( DAT_BYTS )
)
control_top (
.i_clk ( i_clk_if ),
.i_rst ( i_rst_if ),
.o_usr_rst ( usr_rst ),
.rx_if ( rx_if ),
.tx_if ( tx_int_if[0] ),
.o_equihash_if ( equihash_axi ),
.i_equihash_mask ( equihash_mask ),
.i_equihash_mask_val ( equihash_mask_val ),
.o_secp256k1_if ( secp256k1_out_if ),
.i_secp256k1_if ( secp256k1_in_if )
);
// This block is used to verify a equihash solution
cdc_fifo_if #(
.SIZE ( 16 ),
.USE_BRAM ( 0 ),
.RAM_PERFORMANCE ("HIGH_PERFORMANCE")
)
cdc_fifo_equihash_rx (
.i_clk_a ( i_clk_if ),
.i_rst_a ( usr_rst || i_rst_if ),
.i_clk_b ( i_clk_100 ),
.i_rst_b ( rst_100 || ENB_VERIFY_EQUIHASH == 0 ),
.i_a ( equihash_axi ),
.o_full_a(),
.o_b ( equihash_axi_s ),
.o_emp_b ()
);
cdc_fifo #(
.SIZE ( 16 ),
.DAT_BITS ( $bits(equihash_bm_t) ),
.USE_BRAM ( 0 )
)
cdc_fifo_equihash_tx (
.i_clk_a ( i_clk_100 ),
.i_rst_a ( rst_100 || ENB_VERIFY_EQUIHASH == 0 ),
.i_clk_b ( i_clk_if ),
.i_rst_b ( usr_rst || i_rst_if ),
.i_val_a ( equihash_mask_val_s ),
.i_dat_a ( equihash_mask_s ),
.o_rdy_a (),
.o_full_a(),
.o_val_b ( equihash_mask_val ),
.o_dat_b ( equihash_mask ),
.i_rdy_b ( 1'd1 ),
.o_emp_b (),
.o_rd_wrds_b()
);
equihash_verif_top #(
.DAT_BYTS( DAT_BYTS )
)
equihash_verif_top (
.i_clk ( i_clk_100 ),
.i_rst ( rst_100 || ENB_VERIFY_EQUIHASH == 0 ),
.i_clk_300 ( i_clk_300 ),
.i_rst_300 ( rst_300 || ENB_VERIFY_EQUIHASH == 0 ),
.i_axi ( equihash_axi_s ),
.o_mask ( equihash_mask_s ),
.o_mask_val ( equihash_mask_val_s )
);
// This block is the ECCDSA block for curve secp256k1
cdc_fifo_if #(
.SIZE ( 16 ),
.USE_BRAM ( 0 ),
.RAM_PERFORMANCE ("HIGH_PERFORMANCE")
)
cdc_fifo_secp256k1_rx (
.i_clk_a ( i_clk_if ),
.i_rst_a ( usr_rst || i_rst_if ),
.i_clk_b ( i_clk_200 ),
.i_rst_b ( rst_200 || ENB_VERIFY_SECP256K1_SIG == 0 ),
.i_a ( secp256k1_out_if ),
.o_full_a(),
.o_b ( secp256k1_out_if_s ),
.o_emp_b ()
);
cdc_fifo_if #(
.SIZE ( 16 ),
.USE_BRAM ( 0 ),
.RAM_PERFORMANCE ("HIGH_PERFORMANCE")
)
cdc_fifo_secp256k1_tx (
.i_clk_a ( i_clk_200 ),
.i_rst_a ( rst_200 || ENB_VERIFY_SECP256K1_SIG == 0 ),
.i_clk_b ( i_clk_if ),
.i_rst_b ( usr_rst || i_rst_if ),
.i_a ( secp256k1_in_if_s ),
.o_full_a(),
.o_b ( secp256k1_in_if ),
.o_emp_b ()
);
// We add pipelining so this block can be on a different SLR
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) secp256k1_out_if_s_r(i_clk_200);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) secp256k1_in_if_s_r(i_clk_200);
pipeline_if #(
.DAT_BYTS( DAT_BYTS ),
.CTL_BITS( CTL_BITS ),
.NUM_STAGES (2)
)
secp256k1_pipeline_if0 (
.i_rst ( rst_200 ),
.i_if ( secp256k1_out_if_s ),
.o_if ( secp256k1_out_if_s_r )
);
pipeline_if #(
.DAT_BYTS( DAT_BYTS ),
.CTL_BITS( CTL_BITS ),
.NUM_STAGES (2)
)
secp256k1_pipeline_if1 (
.i_rst ( rst_200 ),
.i_if ( secp256k1_in_if_s_r ),
.o_if ( secp256k1_in_if_s )
);
secp256k1_top secp256k1_top (
.i_clk ( i_clk_200 ),
.i_rst ( rst_200 || ENB_VERIFY_SECP256K1_SIG == 0 ),
.if_cmd_rx ( secp256k1_out_if_s_r ),
.if_cmd_tx ( secp256k1_in_if_s_r )
);
bls12_381_top #(
.USE_KARATSUBA ( BLS12_381_USE_KARATSUBA )
)
bls12_381_top (
.i_clk ( i_clk_if ),
.i_rst ( i_rst_if || ENB_BLS12_381 == 0 ),
.tx_if ( tx_int_if[1] ),
.axi_lite_if ( axi_lite_if )
);
// Mux output of control block and BLS12_381 block
packet_arb # (
.DAT_BYTS ( DAT_BYTS ),
.CTL_BITS ( 1 ),
.NUM_IN ( 2 )
) packet_arb_tx (
.i_clk ( i_clk_if ),
.i_rst ( i_rst_if ),
.i_axi ( tx_int_if ),
.o_axi ( tx_if )
);
/*
This is the top level of the Zcash FPGA acceleration engine.
We have different interfaces that are all muxed together to provide FPGA
with commands and data.
Copyright (C) 2019 Benjamin Devlin and Zcash Foundation
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
module zcash_fpga_top
import zcash_fpga_pkg::*, equihash_pkg::*;
#(
parameter DAT_BYTS = 8 // Only tested at 8 byte data width
)(
// Clocks and resets
input i_clk_100, i_rst_100, // 100 MHz clock
input i_clk_200, i_rst_200, // 200 MHz clock
input i_clk_300, i_rst_300, // 300 MHz clock
input i_clk_if, i_rst_if, // Command interface clock (e.g. UART / PCIe)
// AXI lite interface
if_axi_lite.sink axi_lite_if,
// Command interface input and output
if_axi_stream.sink rx_if,
if_axi_stream.source tx_if
);
localparam CTL_BITS = 8;
localparam USE_XILINX_FIFO = "YES"; // If you use this make sure you generate the ip folder in aws/cl_zcash/ip
// These are the resets combined with the user reset
logic usr_rst_100, rst_100;
logic usr_rst_200, rst_200;
logic usr_rst_300, rst_300;
logic usr_rst;
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) equihash_axi(i_clk_if);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) equihash_axi_s(i_clk_100);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) secp256k1_out_if(i_clk_if);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) secp256k1_in_if(i_clk_if);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) secp256k1_out_if_s(i_clk_200);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) secp256k1_in_if_s(i_clk_200);
equihash_bm_t equihash_mask, equihash_mask_s;
logic equihash_mask_val, equihash_mask_val_s;
// Synchronize resets from interface into each clock domain
synchronizer #(.DAT_BITS ( 1 ), .NUM_CLKS ( 3 )) rst_100_sync (
.i_clk_a ( i_clk_if ),
.i_clk_b ( i_clk_100 ),
.i_dat_a ( usr_rst ),
.o_dat_b ( usr_rst_100 )
);
always_ff @ (posedge i_clk_200) rst_200 <= i_rst_200 || usr_rst_200;
synchronizer #(.DAT_BITS ( 1 ), .NUM_CLKS ( 3 )) rst_200_sync (
.i_clk_a ( i_clk_if ),
.i_clk_b ( i_clk_200 ),
.i_dat_a ( usr_rst ),
.o_dat_b ( usr_rst_200 )
);
always_ff @ (posedge i_clk_100) rst_100 <= i_rst_100 || usr_rst_100;
synchronizer #(.DAT_BITS ( 1 ), .NUM_CLKS ( 3 )) rst_300_sync (
.i_clk_a ( i_clk_if ),
.i_clk_b ( i_clk_300 ),
.i_dat_a ( usr_rst ),
.o_dat_b ( usr_rst_300 )
);
always_ff @ (posedge i_clk_300) rst_300 <= i_rst_300 || usr_rst_300;
// This block takes in the interface signals and interfaces with other blocks
// This runs on the same clock as the interface but we might need to change data width
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(1)) tx_int_if [1:0] (i_clk_if);
control_top #(
.DAT_BYTS ( DAT_BYTS )
)
control_top (
.i_clk ( i_clk_if ),
.i_rst ( i_rst_if ),
.o_usr_rst ( usr_rst ),
.rx_if ( rx_if ),
.tx_if ( tx_int_if[0] ),
.o_equihash_if ( equihash_axi ),
.i_equihash_mask ( equihash_mask ),
.i_equihash_mask_val ( equihash_mask_val ),
.o_secp256k1_if ( secp256k1_out_if ),
.i_secp256k1_if ( secp256k1_in_if )
);
// This block is used to verify a equihash solution
cdc_fifo_if #(
.SIZE ( 16 ),
.USE_BRAM ( 0 ),
.RAM_PERFORMANCE ("HIGH_PERFORMANCE")
)
cdc_fifo_equihash_rx (
.i_clk_a ( i_clk_if ),
.i_rst_a ( usr_rst || i_rst_if ),
.i_clk_b ( i_clk_100 ),
.i_rst_b ( rst_100 || ENB_VERIFY_EQUIHASH == 0 ),
.i_a ( equihash_axi ),
.o_full_a(),
.o_b ( equihash_axi_s ),
.o_emp_b ()
);
cdc_fifo #(
.SIZE ( 16 ),
.DAT_BITS ( $bits(equihash_bm_t) ),
.USE_BRAM ( 0 )
)
cdc_fifo_equihash_tx (
.i_clk_a ( i_clk_100 ),
.i_rst_a ( rst_100 || ENB_VERIFY_EQUIHASH == 0 ),
.i_clk_b ( i_clk_if ),
.i_rst_b ( usr_rst || i_rst_if ),
.i_val_a ( equihash_mask_val_s ),
.i_dat_a ( equihash_mask_s ),
.o_rdy_a (),
.o_full_a(),
.o_val_b ( equihash_mask_val ),
.o_dat_b ( equihash_mask ),
.i_rdy_b ( 1'd1 ),
.o_emp_b (),
.o_rd_wrds_b()
);
equihash_verif_top #(
.DAT_BYTS( DAT_BYTS )
)
equihash_verif_top (
.i_clk ( i_clk_100 ),
.i_rst ( rst_100 || ENB_VERIFY_EQUIHASH == 0 ),
.i_clk_300 ( i_clk_300 ),
.i_rst_300 ( rst_300 || ENB_VERIFY_EQUIHASH == 0 ),
.i_axi ( equihash_axi_s ),
.o_mask ( equihash_mask_s ),
.o_mask_val ( equihash_mask_val_s )
);
// This block is the ECCDSA block for curve secp256k1
if (USE_XILINX_FIFO == "YES") begin
logic cdc_fifo_secp256k1_rx_full, cdc_fifo_secp256k1_rx_empty, cdc_fifo_secp256k1_rx_wr_rst_busy, cdc_fifo_secp256k1_rx_rd_rst_busy;
always_comb begin
secp256k1_out_if.rdy = ~cdc_fifo_secp256k1_rx_full && ~cdc_fifo_secp256k1_rx_wr_rst_busy;
secp256k1_out_if_s.val = ~cdc_fifo_secp256k1_rx_rd_rst_busy && ~cdc_fifo_secp256k1_rx_empty;
secp256k1_out_if_s.ctl = 0;
secp256k1_out_if_s.err = 0;
secp256k1_out_if_s.mod = 0;
end
fifo_generator_0 cdc_fifo_secp256k1_rx (
.srst (i_rst_if),
.wr_clk (i_clk_if),
.rd_clk (i_clk_200),
.din ({secp256k1_out_if.dat, secp256k1_out_if.sop, secp256k1_out_if.eop}),
.wr_en (secp256k1_out_if.val),
.rd_en (secp256k1_out_if_s.rdy && secp256k1_out_if_s.val),
.dout ({secp256k1_out_if_s.dat, secp256k1_out_if_s.sop, secp256k1_out_if_s.eop}),
.full (cdc_fifo_secp256k1_rx_full),
.empty (cdc_fifo_secp256k1_rx_empty),
.wr_rst_busy(cdc_fifo_secp256k1_rx_wr_rst_busy),
.rd_rst_busy(cdc_fifo_secp256k1_rx_rd_rst_busy)
);
logic cdc_fifo_secp256k1_tx_full, cdc_fifo_secp256k1_tx_empty, cdc_fifo_secp256k1_tx_wr_rst_busy, cdc_fifo_secp256k1_tx_rd_rst_busy;
always_comb begin
secp256k1_in_if_s.rdy = ~cdc_fifo_secp256k1_tx_full && ~cdc_fifo_secp256k1_tx_wr_rst_busy;
secp256k1_in_if.val = ~cdc_fifo_secp256k1_tx_rd_rst_busy && ~cdc_fifo_secp256k1_tx_empty;
secp256k1_in_if.ctl = 0;
secp256k1_in_if.err = 0;
secp256k1_in_if.mod = 0;
end
fifo_generator_0 cdc_fifo_secp256k1_tx (
.srst (i_rst_if),
.wr_clk (i_clk_200),
.rd_clk (i_clk_if),
.din ({secp256k1_in_if_s.dat, secp256k1_in_if_s.sop, secp256k1_in_if_s.eop}),
.wr_en (secp256k1_in_if_s.val),
.rd_en (secp256k1_in_if.rdy && secp256k1_in_if.val),
.dout ({secp256k1_in_if.dat, secp256k1_in_if.sop, secp256k1_in_if.eop}),
.full (cdc_fifo_secp256k1_tx_full),
.empty (cdc_fifo_secp256k1_tx_empty),
.wr_rst_busy(cdc_fifo_secp256k1_tx_wr_rst_busy),
.rd_rst_busy(cdc_fifo_secp256k1_tx_rd_rst_busy)
);
end else begin
cdc_fifo_if #(
.SIZE ( 16 ),
.USE_BRAM ( 0 ),
.RAM_PERFORMANCE ("HIGH_PERFORMANCE")
)
cdc_fifo_secp256k1_rx (
.i_clk_a ( i_clk_if ),
.i_rst_a ( usr_rst || i_rst_if ),
.i_clk_b ( i_clk_200 ),
.i_rst_b ( rst_200 || ENB_VERIFY_SECP256K1_SIG == 0 ),
.i_a ( secp256k1_out_if ),
.o_full_a(),
.o_b ( secp256k1_out_if_s ),
.o_emp_b ()
);
cdc_fifo_if #(
.SIZE ( 16 ),
.USE_BRAM ( 0 ),
.RAM_PERFORMANCE ("HIGH_PERFORMANCE")
)
cdc_fifo_secp256k1_tx (
.i_clk_a ( i_clk_200 ),
.i_rst_a ( rst_200 || ENB_VERIFY_SECP256K1_SIG == 0 ),
.i_clk_b ( i_clk_if ),
.i_rst_b ( usr_rst || i_rst_if ),
.i_a ( secp256k1_in_if_s ),
.o_full_a(),
.o_b ( secp256k1_in_if ),
.o_emp_b ()
);
end
// We add pipelining so this block can be on a different SLR
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) secp256k1_out_if_s_r(i_clk_200);
if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) secp256k1_in_if_s_r(i_clk_200);
pipeline_if #(
.DAT_BYTS( DAT_BYTS ),
.CTL_BITS( CTL_BITS ),
.NUM_STAGES (2)
)
secp256k1_pipeline_if0 (
.i_rst ( rst_200 ),
.i_if ( secp256k1_out_if_s ),
.o_if ( secp256k1_out_if_s_r )
);
pipeline_if #(
.DAT_BYTS( DAT_BYTS ),
.CTL_BITS( CTL_BITS ),
.NUM_STAGES (2)
)
secp256k1_pipeline_if1 (
.i_rst ( rst_200 ),
.i_if ( secp256k1_in_if_s_r ),
.o_if ( secp256k1_in_if_s )
);
secp256k1_top secp256k1_top (
.i_clk ( i_clk_200 ),
.i_rst ( rst_200 || ENB_VERIFY_SECP256K1_SIG == 0 ),
.if_cmd_rx ( secp256k1_out_if_s_r ),
.if_cmd_tx ( secp256k1_in_if_s_r )
);
bls12_381_top #(
.USE_KARATSUBA ( BLS12_381_USE_KARATSUBA )
)
bls12_381_top (
.i_clk ( i_clk_if ),
.i_rst ( i_rst_if || ENB_BLS12_381 == 0 ),
.tx_if ( tx_int_if[1] ),
.axi_lite_if ( axi_lite_if )
);
// Mux output of control block and BLS12_381 block
packet_arb # (
.DAT_BYTS ( DAT_BYTS ),
.CTL_BITS ( 1 ),
.NUM_IN ( 2 )
) packet_arb_tx (
.i_clk ( i_clk_if ),
.i_rst ( i_rst_if ),
.i_axi ( tx_int_if ),
.o_axi ( tx_if )
);
endmodule