more readme updates
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@ -28,6 +28,8 @@ These contain shared IP cores used by the projects in this repo. These include m
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- AXI4-lite
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- Block RAM
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* Fifo implementations
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* Hash map implementation
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- Fully parameterized for bit widths and uses CRC as the hashing function
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* Blocks for parsing/processing streams
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* Karabutsa multiplier
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- Fully parameterized for number of levels
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@ -1 +0,0 @@
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This is the design for verifing the Zcash blockchain on an FPGA
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