Updated debug file and added pipeline for interface
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446e628849
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/*
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Pipelining for an interface.
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Copyright (C) 2019 Benjamin Devlin and Zcash Foundation
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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module pipeline_if #(
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parameter NUM_STAGES = 1
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) (
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input rst,
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if_axi_stream.sink i_if,
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if_axi_stream.source o_if
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);
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genvar g0;
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generate
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if (NUM_STAGES == 0) begin
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always_comb o_if.copy_if_comb(i_if.dat, i_if.val, i_if.sop, i_if.eop, i_if.err, i_if.mod, i_if.ctl);
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end else begin
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if_axi_stream #(.DAT_BYTS(i_if.DAT_BYTS), .CTL_BITS(i_if.CTL_BITS)) if_stage [NUM_STAGES-1] (i_if.clk);
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for (g0 = 0; g0 < NUM_STAGES; g0++) begin : GEN_STAGE
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pipeline_if_single pipeline_if_single (.i_if(g0 == 0 ? i_if : if_stage[g0-1]), .o_of(g0 == NUM_STAGES-1 ? o_if : if_stage[g0]));
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end
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end
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endgenerate
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endmodule
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@ -0,0 +1,58 @@
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/*
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Pipelining for an interface.
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Copyright (C) 2019 Benjamin Devlin and Zcash Foundation
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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module pipeline_if_single (
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input rst,
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if_axi_stream.sink i_if,
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if_axi_stream.source o_if
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);
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// Need pipeline stage to store temp data
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if_axi_stream #(.DAT_BYTS(i_if.DAT_BYTS), .CTL_BITS(i_if.CTL_BITS)) if_r (i_if.clk);
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always_ff @ (i_if.clk) begin
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if (rst) begin
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o_if.reset_source();
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if_r.reset_source();
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if_r.rdy <= 0;
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i_if.rdy <= 0;
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end else begin
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i_if.rdy <= ~o_if.val || (o_if.val && o_if.rdy && ~if_r.val);
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// Data transfer cases
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if (~o_if.val || (o_if.val && o_if.rdy)) begin
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// First case - second interface is valid
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if (if_r.val) begin
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o_if.copy_if(if_r.dat, if_r.val, if_r.sop, if_r.eop, if_r.err, if_r.mod, if_r.ctl);
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if_r.val <= 0;
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// Second case - second interface not valid
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end else begin
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o_if.copy_if(i_if.dat, i_if.val, i_if.sop, i_if.eop, i_if.err, i_if.mod, i_if.ctl);
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end
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end
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// Check for case where input is valid so we need to store in second interface
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if (i_if.rdy && (o_if.val && ~o_if.rdy)) begin
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if_r.copy_if(i_if.dat, i_if.val, i_if.sop, i_if.eop, i_if.err, i_if.mod, i_if.ctl);
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end
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end
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end
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endmodule
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@ -17,12 +17,7 @@
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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*/
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module debug_if #(
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module debug_if (
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parameter DAT_BYTS,
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parameter DAT_BITS = DAT_BYTS*8,
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parameter MOD_BITS = DAT_BYTS == 1 ? 1 :$clog2(DAT_BYTS),
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parameter CTL_BITS
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) (
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if_axi_stream i_if
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if_axi_stream i_if
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);
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);
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@ -31,9 +26,9 @@ module debug_if #(
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(* mark_debug = "true" *) logic err;
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(* mark_debug = "true" *) logic err;
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(* mark_debug = "true" *) logic sop;
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(* mark_debug = "true" *) logic sop;
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(* mark_debug = "true" *) logic eop;
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(* mark_debug = "true" *) logic eop;
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(* mark_debug = "true" *) logic [CTL_BITS-1:0] ctl;
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(* mark_debug = "true" *) logic [i_if.CTL_BITS-1:0] ctl;
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(* mark_debug = "true" *) logic [DAT_BITS-1:0] dat;
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(* mark_debug = "true" *) logic [i_if.DAT_BITS-1:0] dat;
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(* mark_debug = "true" *) logic [MOD_BITS-1:0] mod;
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(* mark_debug = "true" *) logic [i_if.MOD_BITS-1:0] mod;
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always_ff @ (posedge i_if.i_clk) begin
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always_ff @ (posedge i_if.i_clk) begin
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rdy <= i_if.rdy;
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rdy <= i_if.rdy;
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