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Updated debug file and added pipeline for interface

This commit is contained in:
bsdevlin 2019-04-15 11:48:40 -04:00
parent 446e628849
commit bc4861fc9f
3 changed files with 106 additions and 9 deletions
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44
ip_cores/common/src/rtl/pipeline_if.sv Normal file
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@ -0,0 +1,44 @@
/*
Pipelining for an interface.
Copyright (C) 2019 Benjamin Devlin and Zcash Foundation
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
module pipeline_if #(
parameter NUM_STAGES = 1
) (
input rst,
if_axi_stream.sink i_if,
if_axi_stream.source o_if
);
genvar g0;
generate
if (NUM_STAGES == 0) begin
always_comb o_if.copy_if_comb(i_if.dat, i_if.val, i_if.sop, i_if.eop, i_if.err, i_if.mod, i_if.ctl);
end else begin
if_axi_stream #(.DAT_BYTS(i_if.DAT_BYTS), .CTL_BITS(i_if.CTL_BITS)) if_stage [NUM_STAGES-1] (i_if.clk);
for (g0 = 0; g0 < NUM_STAGES; g0++) begin : GEN_STAGE
pipeline_if_single pipeline_if_single (.i_if(g0 == 0 ? i_if : if_stage[g0-1]), .o_of(g0 == NUM_STAGES-1 ? o_if : if_stage[g0]));
end
end
endgenerate
endmodule

58
ip_cores/common/src/rtl/pipeline_if_single.sv Normal file
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@ -0,0 +1,58 @@
/*
Pipelining for an interface.
Copyright (C) 2019 Benjamin Devlin and Zcash Foundation
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
module pipeline_if_single (
input rst,
if_axi_stream.sink i_if,
if_axi_stream.source o_if
);
// Need pipeline stage to store temp data
if_axi_stream #(.DAT_BYTS(i_if.DAT_BYTS), .CTL_BITS(i_if.CTL_BITS)) if_r (i_if.clk);
always_ff @ (i_if.clk) begin
if (rst) begin
o_if.reset_source();
if_r.reset_source();
if_r.rdy <= 0;
i_if.rdy <= 0;
end else begin
i_if.rdy <= ~o_if.val || (o_if.val && o_if.rdy && ~if_r.val);
// Data transfer cases
if (~o_if.val || (o_if.val && o_if.rdy)) begin
// First case - second interface is valid
if (if_r.val) begin
o_if.copy_if(if_r.dat, if_r.val, if_r.sop, if_r.eop, if_r.err, if_r.mod, if_r.ctl);
if_r.val <= 0;
// Second case - second interface not valid
end else begin
o_if.copy_if(i_if.dat, i_if.val, i_if.sop, i_if.eop, i_if.err, i_if.mod, i_if.ctl);
end
end
// Check for case where input is valid so we need to store in second interface
if (i_if.rdy && (o_if.val && ~o_if.rdy)) begin
if_r.copy_if(i_if.dat, i_if.val, i_if.sop, i_if.eop, i_if.err, i_if.mod, i_if.ctl);
end
end
end
endmodule

13
ip_cores/util/src/rtl/debug_if.sv
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@ -17,12 +17,7 @@
along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
module debug_if #(
parameter DAT_BYTS,
parameter DAT_BITS = DAT_BYTS*8,
parameter MOD_BITS = DAT_BYTS == 1 ? 1 :$clog2(DAT_BYTS),
parameter CTL_BITS
) (
module debug_if (
if_axi_stream i_if
);
@ -31,9 +26,9 @@ module debug_if #(
(* mark_debug = "true" *) logic err;
(* mark_debug = "true" *) logic sop;
(* mark_debug = "true" *) logic eop;
(* mark_debug = "true" *) logic [CTL_BITS-1:0] ctl;
(* mark_debug = "true" *) logic [DAT_BITS-1:0] dat;
(* mark_debug = "true" *) logic [MOD_BITS-1:0] mod;
(* mark_debug = "true" *) logic [i_if.CTL_BITS-1:0] ctl;
(* mark_debug = "true" *) logic [i_if.DAT_BITS-1:0] dat;
(* mark_debug = "true" *) logic [i_if.MOD_BITS-1:0] mod;
always_ff @ (posedge i_if.i_clk) begin
rdy <= i_if.rdy;