First cut of AWS test program
This commit is contained in:
bsdevlin
parent
fcdc3c4975
commit
c144db9064
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@ -19,27 +19,16 @@
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#include <assert.h>
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#include <string.h>
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#ifdef SV_TEST
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#include "fpga_pci_sv.h"
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#else
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#include <fpga_pci.h>
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#include <fpga_mgmt.h>
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#include <utils/lcd.h>
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#endif
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#include <fpga_pci.h>
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#include <fpga_mgmt.h>
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#include <utils/lcd.h>
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#include <utils/sh_dpi_tasks.h>
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/* Constants determined by the CL */
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/* a set of register offsets; this CL has only one */
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/* these register addresses should match the addresses in */
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/* /aws-fpga/hdk/cl/examples/common/cl_common_defines.vh */
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/* SV_TEST macro should be set if SW/HW co-simulation should be enabled */
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#define HELLO_WORLD_REG_ADDR UINT64_C(0x500)
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#define VLED_REG_ADDR UINT64_C(0x504)
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#define AXI_FIFO_OFFSET UINT64_C(0x0)
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#define ZCASH_OFFSET UINT64_C(0x1000)
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/* use the stdout logger for printing debug information */
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#ifndef SV_TEST
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const struct logger *logger = &logger_stdout;
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/*
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* pci_vendor_id and pci_device_id values below are Amazon's and avaliable to use for a given FPGA slot.
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@ -48,14 +37,26 @@ const struct logger *logger = &logger_stdout;
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static uint16_t pci_vendor_id = 0x1D0F; /* Amazon PCI Vendor ID */
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static uint16_t pci_device_id = 0xF000; /* PCI Device ID preassigned by Amazon for F1 applications */
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pci_bar_handle_t pci_bar_handle_bar0 = PCI_BAR_HANDLE_INIT;
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pci_bar_handle_t pci_bar_handle_bar4 = PCI_BAR_HANDLE_INIT;
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/*
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* check if the corresponding AFI for hello_world is loaded
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*/
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int check_afi_ready(int slot_id);
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/*
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* An example to attach to an arbitrary slot, pf, and bar with register access.
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* Initialize the FPGA
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*/
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int peek_poke_example(uint32_t value, int slot_id, int pf_id, int bar_id);
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int init(int slot_id);
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/*
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* Read / Write to the FPGA stream interface
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*/
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int read_stream(uint8_t* data, unsigned int size); // Size is the buffer size being passed
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int write_stream(uint8_t* data, unsigned int len);
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void usage(char* program_name) {
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printf("usage: %s [--slot <slot-id>][<poke-value>]\n", program_name);
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@ -63,7 +64,6 @@ void usage(char* program_name) {
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uint32_t byte_swap(uint32_t value);
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#endif
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uint32_t byte_swap(uint32_t value) {
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uint32_t swapped_value = 0;
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@ -74,28 +74,13 @@ uint32_t byte_swap(uint32_t value) {
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return swapped_value;
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}
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#ifdef SV_TEST
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//For cadence and questa simulators the main has to return some value
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#ifdef INT_MAIN
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int test_main(uint32_t *exit_code) {
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#else
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void test_main(uint32_t *exit_code) {
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#endif
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#else
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int main(int argc, char **argv) {
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#endif
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//The statements within SCOPE ifdef below are needed for HW/SW co-simulation with VCS
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#ifdef SCOPE
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svScope scope;
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scope = svGetScopeFromName("tb");
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svSetScope(scope);
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#endif
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uint32_t value = 0xefbeadde;
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int main(int argc, char **argv) {
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int slot_id = 0;
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int rc;
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#ifndef SV_TEST
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// Process command line args
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{
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int i;
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@ -119,60 +104,195 @@ uint32_t byte_swap(uint32_t value) {
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}
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}
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}
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#endif
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// Initialize all the FPGA connections
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rc = init(slot_id);
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fail_on(rc, out, "Unable to initialize the FPGA");
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// Test: read from register in BLS core
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uint32_t rdata;
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rc = fpga_pci_peek(pci_bar_handle_bar0, ZCASH_OFFSET, &rdata);
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fail_on(rc, out, "Unable to read from FPGA!");
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printf("INFO: Read 0x%x from address 0", rdata);
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// Test: send status message
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uint8_t message[8];
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memset(message, 0, 8);
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message[0] = 8;
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message[4] = 1;
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rc = write_stream(message, sizeof(message));
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fail_on(rc, out, "Unable to read from FPGA!");
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// Try read reply
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uint8_t reply[256];
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int timeout = 0;
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unsigned int read_len = 0;
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while ((read_len = read_stream(reply, 256)) == 0) {
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usleep(10);
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timeout++;
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if (timeout > 1000) {
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printf("ERROR: No reply received, timeout\n");
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rc = 1;
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goto out;
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}
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}
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printf("Reply received of %d bytes:0x", read_len);
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for (int i = 0; i < read_len; i++)
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printf("%x", reply[i]);
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printf("\n");
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return rc;
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out:
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return 1;
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}
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int write_stream(uint8_t* data, unsigned int len);
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int rc;
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uint32_t rdata;
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unsigned int len_send = 0;
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rc = fpga_pci_peek(pci_bar_handle_bar0, AXI_FIFO_OFFSET + 0xCULL, &rdata);
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fail_on(rc, out, "Unable to read from FPGA!");
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if (len > rdata) {
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printf("ERROR: write_stream does not have enough space to write %d bytes! (%d free)\n", len, rdata);
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goto out;
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}
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while(len_send < len) {
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fpga_pci_poke64(pci_bar_handle_bar4, 0, *(uint64_t*)(&data[len_send]));
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len_send += 8;
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}
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rc = fpga_pci_poke(pci_bar_handle_bar0, AXI_FIFO_OFFSET+0x14ULL, len); // Reset ISR
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fail_on(rc, out, "Unable to write to FPGA!");
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printf("INFO: write_stream::Wrote %d bytes of data", len);
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// Check transmit complete bit and reset it
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rc = fpga_pci_peek(pci_bar_handle_bar0, AXI_FIFO_OFFSET, &rdata);
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fail_on(rc, out, "Unable to read from FPGA!");
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if (rdata & (1 << 27) == 0) {
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printf("WARNING: write_stream transmit bit not set, register returned 0x%x\n", rdata);
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}
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rc = fpga_pci_poke(pci_bar_handle_bar0, AXI_FIFO_OFFSET, 0x08000000); // Reset ISR
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fail_on(rc, out, "Unable to write to FPGA!");
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return rc;
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out:
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return 1;
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}
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int read_stream(uint8_t* data, unsigned int size);
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uint32_t rdata;
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int read_len = 0;
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if (size == 0) {
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printf("WARNING: Size was 0, cannot read into empty buffer!\n");
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return 0;
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}
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rc = fpga_pci_peek(pci_bar_handle_bar0, AXI_FIFO_OFFSET, &rdata);
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fail_on(rc, out, "Unable to read from FPGA!");
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if (rdata & (1 << 26) == 0) return 0; // Nothing to read
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rc = fpga_pci_poke(pci_bar_handle_bar0, AXI_FIFO_OFFSET, 0x04000000); // clear ISR
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fail_on(rc, out, "Unable to write to FPGA!");
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rc = fpga_pci_peek(pci_bar_handle_bar0, AXI_FIFO_OFFSET + 0x1CULL, &rdata); //RDFO should be non-zero (slots used in FIFO)
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fail_on(rc, out, "Unable to read from FPGA!");
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if (rdata == 0) {
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printf("WARNING: Read FIFO shows data but length was 0!\n");
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return 0;
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}
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rc = fpga_pci_peek(pci_bar_handle_bar0, AXI_FIFO_OFFSET + 0x24ULL, &rdata); //RLR - length of packet in bytes
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fail_on(rc, out, "Unable to read from FPGA!");
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while(rdata > 0 && size >= read_len+8) {
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rc = fpga_pci_peek64(pci_bar_handle_bar4, 0, (uint64_t*)(&data[read_len]));
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fail_on(rc, out, "Unable to read from FPGA PCIS!");
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read_len += 8;
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}
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printf("INFO: Read %d bytes from read_stream()\n", read_len);
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return read_len;
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out:
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return -1;
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}
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int init(int slot_id) {
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int rc;
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uint32_t rdata;
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/* initialize the fpga_pci library so we could have access to FPGA PCIe from this applications */
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rc = fpga_pci_init();
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fail_on(rc, out, "Unable to initialize the fpga_pci library");
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#ifndef SV_TEST
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rc = check_afi_ready(slot_id);
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fail_on(rc, out, "AFI not ready");
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#endif
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// We need to attach to the FPGA BAR0 (OCL) and BAR4 (PCIS)
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rc = fpga_pci_attach(slot_id, FPGA_APP_PF, APP_PF_BAR0, 0, &pci_bar_handle_bar0);
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fail_on(rc, out, "Unable to attach to the AFI BAR0 on slot id %d", slot_id);
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/* Accessing the CL registers via AppPF BAR0, which maps to sh_cl_ocl_ AXI-Lite bus between AWS FPGA Shell and the CL*/
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rc = fpga_pci_attach(slot_id, FPGA_APP_PF, APP_PF_BAR4, BURST_CAPABLE, &pci_bar_handle_bar4);
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fail_on(rc, out, "Unable to attach to the AFI BAR4 on slot id %d", slot_id);
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printf("===== Starting with peek_poke_example =====\n");
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rc = peek_poke_example(value, slot_id, FPGA_APP_PF, APP_PF_BAR0);
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fail_on(rc, out, "peek-poke example failed");
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// Now setup the streaming interface
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printf("Developers are encouraged to modify the Virtual DIP Switch by calling the linux shell command to demonstrate how AWS FPGA Virtual DIP switches can be used to change a CustomLogic functionality:\n");
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printf("$ fpga-set-virtual-dip-switch -S (slot-id) -D (16 digit setting)\n\n");
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printf("In this example, setting a virtual DIP switch to zero clears the corresponding LED, even if the peek-poke example would set it to 1.\nFor instance:\n");
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rc = fpga_pci_peek(pci_bar_handle_bar0, AXI_FIFO_OFFSET, &rdata); //ISR
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fail_on(rc, out, "Unable to read from FPGA!");
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printf("INFO: Read 0x%x from ISR register.\n", rdata);
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if (rdata != 0x01D00000) {
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printf("WARNING: Expected 0x01D00000.\n");
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}
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printf(
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"# sudo fpga-set-virtual-dip-switch -S 0 -D 1111111111111111\n"
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"# sudo fpga-get-virtual-led -S 0\n"
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"FPGA slot id 0 have the following Virtual LED:\n"
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"1010-1101-1101-1110\n"
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"# sudo fpga-set-virtual-dip-switch -S 0 -D 0000000000000000\n"
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"# sudo fpga-get-virtual-led -S 0\n"
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"FPGA slot id 0 have the following Virtual LED:\n"
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"0000-0000-0000-0000\n"
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);
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rc = fpga_pci_poke(pci_bar_handle_bar0, AXI_FIFO_OFFSET, 0xFFFFFFFF); // Reset ISR
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fail_on(rc, out, "Unable to write to FPGA!");
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rc = fpga_pci_peek(pci_bar_handle_bar0, AXI_FIFO_OFFSET+0xCULL, &rdata); //TDFV
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fail_on(rc, out, "Unable to read from FPGA!");
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printf("INFO: Read 0x%x from TDFV register.\n", rdata);
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if (rdata != 0x000001FC) {
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printf("WARNING: Expected 0x000001FC.\n");
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}
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rc = fpga_pci_peek(pci_bar_handle_bar0, AXI_FIFO_OFFSET+0x1CULL, &rdata); //RDFO
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fail_on(rc, out, "Unable to read from FPGA!");
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printf("INFO: Read 0x%x from RDFO register.\n", rdata);
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if (rdata != 0x00000000) {
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printf("WARNING: Expected 0x00000000.\n");
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}
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rc = fpga_pci_poke(pci_bar_handle_bar0, AXI_FIFO_OFFSET+0x4ULL, 0x0C000000); // Clear IER
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fail_on(rc, out, "Unable to write to FPGA!");
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printf("INFO: Finished initializing FPGA.\n");
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#ifndef SV_TEST
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return rc;
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out:
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out:
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/* clean up */
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if (pci_bar_handle_bar0 >= 0) {
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rc = fpga_pci_detach(pci_bar_handle_bar0);
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if (rc) printf("Failure while detaching bar0 from the fpga.\n");
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}
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if (pci_bar_handle_bar4 >= 0) {
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rc = fpga_pci_detach(pci_bar_handle_bar4);
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if (rc) printf("Failure while detaching bar4 from the fpga.\n");
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}
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return 1;
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#else
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out:
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#ifdef INT_MAIN
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*exit_code = 0;
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return 0;
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#else
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*exit_code = 0;
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#endif
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#endif
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}
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/* As HW simulation test is not run on a AFI, the below function is not valid */
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#ifndef SV_TEST
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int check_afi_ready(int slot_id) {
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int check_afi_ready(int slot_id) {
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struct fpga_mgmt_image_info info = {0};
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int rc;
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@ -218,71 +338,6 @@ out:
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return rc;
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out:
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return 1;
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}
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#endif
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/*
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* An example to attach to an arbitrary slot, pf, and bar with register access.
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*/
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int peek_poke_example(uint32_t value, int slot_id, int pf_id, int bar_id) {
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int rc;
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/* pci_bar_handle_t is a handler for an address space exposed by one PCI BAR on one of the PCI PFs of the FPGA */
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pci_bar_handle_t pci_bar_handle = PCI_BAR_HANDLE_INIT;
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/* attach to the fpga, with a pci_bar_handle out param
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* To attach to multiple slots or BARs, call this function multiple times,
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* saving the pci_bar_handle to specify which address space to interact with in
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* other API calls.
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* This function accepts the slot_id, physical function, and bar number
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*/
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#ifndef SV_TEST
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rc = fpga_pci_attach(slot_id, pf_id, bar_id, 0, &pci_bar_handle);
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fail_on(rc, out, "Unable to attach to the AFI on slot id %d", slot_id);
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#endif
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/* write a value into the mapped address space */
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uint32_t expected = byte_swap(value);
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printf("Writing 0x%08x to HELLO_WORLD register (0x%016lx)\n", value, HELLO_WORLD_REG_ADDR);
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rc = fpga_pci_poke(pci_bar_handle, HELLO_WORLD_REG_ADDR, value);
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fail_on(rc, out, "Unable to write to the fpga !");
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/* read it back and print it out; you should expect the byte order to be
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* reversed (That's what this CL does) */
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rc = fpga_pci_peek(pci_bar_handle, HELLO_WORLD_REG_ADDR, &value);
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fail_on(rc, out, "Unable to read read from the fpga !");
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printf("===== Entering peek_poke_example =====\n");
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printf("register: 0x%x\n", value);
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if(value == expected) {
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printf("TEST PASSED");
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printf("Resulting value matched expected value 0x%x. It worked!\n", expected);
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}
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else{
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printf("TEST FAILED");
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printf("Resulting value did not match expected value 0x%x. Something didn't work.\n", expected);
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}
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out:
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/* clean up */
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if (pci_bar_handle >= 0) {
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rc = fpga_pci_detach(pci_bar_handle);
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if (rc) {
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printf("Failure while detaching from the fpga.\n");
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}
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}
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/* if there is an error code, exit with status 1 */
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return (rc != 0 ? 1 : 0);
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}
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#ifdef SV_TEST
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/*This function is used transfer string buffer from SV to C.
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This function currently returns 0 but can be used to update a buffer on the 'C' side.*/
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int send_rdbuf_to_c(char* rd_buf)
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{
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return 0;
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}
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#endif
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