bls12_381 exponent calculation module and testbench
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bsdevlin
parent
891dd214dc
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d01edec6a9
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/*
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This takes an fe12 element and raises it to a power using the multiply and
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square algorithm.
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Inputs must be interleaved starting at c0 (i.e. clock 0 = {b.c0, a.c0})
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_s in the name represents the input is a stream starting at c0.
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Copyright (C) 2019 Benjamin Devlin and Zcash Foundation
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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module ec_fe12_pow_s
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#(
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parameter type FE_TYPE, // Base field element type
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parameter POW_BITS, // Number of bits for the power value (in .ctl of input)
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parameter SQ_BIT // This bit is set when we are doing a square
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)(
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input i_clk, i_rst,
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// Interface to FE_TYPE12 mul (mod P) 2*FE_TYPE data width
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if_axi_stream.source o_mul_fe12_if,
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if_axi_stream.sink i_mul_fe12_if,
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// Interface to FE_TYPE sub (mod P) 2*FE_TYPE data width
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if_axi_stream.source o_sub_fe_if,
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if_axi_stream.sink i_sub_fe_if,
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// Interface to FE_TYPE mul (mod P) FE_TYPE data width
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if_axi_stream.source o_pow_fe12_if,
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if_axi_stream.sink i_pow_fe12_if // Power is stored in .ctl
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);
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FE_TYPE [11:0] a;
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FE_TYPE [11:0] res;
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logic [3:0] cnt;
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logic [POW_BITS-1:0] pow;
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enum {IDLE, POW_MUL, POW_SQ, SUB, OUTPUT} state;
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always_comb begin
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i_pow_fe12_if.rdy = state == IDLE;
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end
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always_ff @ (posedge i_clk) begin
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if (i_rst) begin
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o_mul_fe12_if.reset_source();
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o_sub_fe_if.reset_source();
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o_pow_fe12_if.reset_source();
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a <= 0;
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res <= 0;
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cnt <= 0;
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state <= IDLE;
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pow <= 0;
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end else begin
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i_sub_fe_if.rdy <= 0;
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i_mul_fe12_if.rdy <= 0;
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if (o_sub_fe_if.rdy) o_sub_fe_if.val <= 0;
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if (o_mul_fe12_if.rdy) o_mul_fe12_if.val <= 0;
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if (o_pow_fe12_if.rdy) o_pow_fe12_if.val <= 0;
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case (state)
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IDLE: begin
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cnt <= 0;
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res <= 0;
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res[0][0] <= 1;
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if (i_pow_fe12_if.val && i_pow_fe12_if.rdy) begin
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if (i_pow_fe12_if.eop) begin
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state <= pow[0] ? POW_MUL : POW_SQ;
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pow <= pow >> 1;
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end
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if (i_pow_fe12_if.sop) begin
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o_pow_fe12_if.ctl <= i_pow_fe12_if.ctl;
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pow <= i_pow_fe12_if.ctl;
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end
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a <= {i_pow_fe12_if.dat, a[11:1]};
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end
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end
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POW_MUL: begin
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if (cnt < 12) begin
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if (~o_mul_fe12_if.val || (o_mul_fe12_if.val && o_mul_fe12_if.rdy)) begin
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cnt <= cnt + 1;
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o_mul_fe12_if.ctl[SQ_BIT] <= 0;
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o_mul_fe12_if.sop <= cnt == 0;
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o_mul_fe12_if.eop <= cnt == 11;
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o_mul_fe12_if.dat <= {a[cnt], res[cnt]};
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o_mul_fe12_if.val <= 1;
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end
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end else begin
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// Waiting for result
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i_mul_fe12_if.rdy <= 1;
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if (i_mul_fe12_if.val && i_mul_fe12_if.rdy) begin
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res <= {i_mul_fe12_if.dat, res[11:1]};
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if (i_mul_fe12_if.eop) begin
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state <= (pow == 0) ? SUB : POW_SQ;
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cnt <= 0;
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end
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end
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end
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end
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POW_SQ: begin
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if (cnt < 12) begin
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if (~o_mul_fe12_if.val || (o_mul_fe12_if.val && o_mul_fe12_if.rdy)) begin
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cnt <= cnt + 1;
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o_mul_fe12_if.ctl[SQ_BIT] <= 1;
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o_mul_fe12_if.sop <= cnt == 0;
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o_mul_fe12_if.eop <= cnt == 11;
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o_mul_fe12_if.dat <= {a[cnt], a[cnt]};
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o_mul_fe12_if.val <= 1;
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end
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end else begin
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// Waiting for result
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i_mul_fe12_if.rdy <= 1;
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if (i_mul_fe12_if.val && i_mul_fe12_if.rdy) begin
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a <= {i_mul_fe12_if.dat, a[11:1]};
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if (i_mul_fe12_if.eop) begin
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pow <= pow >> 1;
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state <= pow[0] ? POW_MUL : POW_SQ;
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cnt <= 0;
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end
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end
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end
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end
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SUB: begin
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if (cnt < 6) begin
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if (~o_sub_fe_if.val || (o_sub_fe_if.val && o_sub_fe_if.rdy)) begin
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cnt <= cnt + 1;
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o_sub_fe_if.ctl[SQ_BIT] <= 1;
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o_sub_fe_if.sop <= cnt == 0;
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o_sub_fe_if.eop <= cnt == 5;
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o_sub_fe_if.dat[0 +: $bits(FE_TYPE)] <= 0;
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o_sub_fe_if.dat[$bits(FE_TYPE) +: $bits(FE_TYPE)] <= res[cnt+6]; // Only top Fe6
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o_sub_fe_if.val <= 1;
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end
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end else begin
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// Waiting for result
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i_sub_fe_if.rdy <= 1;
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if (i_sub_fe_if.val && i_sub_fe_if.rdy) begin
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res[11:6] <= {i_sub_fe_if.dat, res[11:7]};
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if (i_sub_fe_if.eop) begin
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i_sub_fe_if.rdy <= 0;
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cnt <= 0;
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state <= OUTPUT;
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end
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end
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end
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end
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OUTPUT: begin
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if (~o_pow_fe12_if.val || (o_pow_fe12_if.val && o_pow_fe12_if.rdy)) begin
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o_pow_fe12_if.sop <= cnt == 0;
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o_pow_fe12_if.eop <= cnt == 11;
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o_pow_fe12_if.val <= 1;
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o_pow_fe12_if.dat <= res[0];
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res <= {i_sub_fe_if.dat, res[11:1]};
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cnt <= cnt + 1;
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if (cnt == 11) state <= IDLE;
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end
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end
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endcase
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end
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end
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endmodule
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@ -0,0 +1,321 @@
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/*
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Copyright (C) 2019 Benjamin Devlin and Zcash Foundation
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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`timescale 1ps/1ps
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module ec_fe12_pow_s_tb ();
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import common_pkg::*;
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import bls12_381_pkg::*;
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parameter type FE_TYPE = bls12_381_pkg::fe_t;
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parameter type FE2_TYPE = bls12_381_pkg::fe2_t;
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parameter type FE6_TYPE = bls12_381_pkg::fe6_t;
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parameter type FE12_TYPE = bls12_381_pkg::fe12_t;
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parameter P = bls12_381_pkg::P;
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parameter POW_BITS = $bits(bls12_381_pkg::ATE_X);
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localparam CTL_BITS = 32;
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localparam SQ_BIT = 24;
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localparam CLK_PERIOD = 100;
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logic clk, rst;
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initial begin
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rst = 0;
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repeat(2) #(20*CLK_PERIOD) rst = ~rst;
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end
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initial begin
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clk = 0;
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forever #(CLK_PERIOD/2) clk = ~clk;
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end
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if_axi_stream #(.DAT_BITS(2*$bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) mul_fe_o_if (clk);
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if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) mul_fe_i_if (clk);
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if_axi_stream #(.DAT_BITS(2*$bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) add_fe_o_if [4:0] (clk);
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if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) add_fe_i_if [4:0] (clk);
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if_axi_stream #(.DAT_BITS(2*$bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) sub_fe_o_if [5:0] (clk);
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if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) sub_fe_i_if [5:0] (clk);
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if_axi_stream #(.DAT_BITS(2*$bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) mul_fe2_o_if (clk);
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if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) mul_fe2_i_if (clk);
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if_axi_stream #(.DAT_BITS(2*$bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) mul_fe6_o_if (clk);
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if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) mul_fe6_i_if (clk);
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if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) mnr_fe2_o_if [2:0] (clk);
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if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) mnr_fe2_i_if [2:0] (clk);
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if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) mnr_fe6_o_if (clk);
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if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) mnr_fe6_i_if (clk);
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if_axi_stream #(.DAT_BITS(2*$bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) mul_fe12_o_if (clk);
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if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) mul_fe12_i_if (clk);
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if_axi_stream #(.DAT_BYTS(($bits(FE_TYPE)+7)/8), .CTL_BITS(POW_BITS)) pow_fe12_o_if (clk);
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if_axi_stream #(.DAT_BYTS(($bits(FE_TYPE)+7)/8), .CTL_BITS(POW_BITS)) pow_fe12_i_if (clk);
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ec_fp_mult_mod #(
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.P ( P ),
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.KARATSUBA_LVL ( 3 ),
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.CTL_BITS ( CTL_BITS )
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)
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ec_fp_mult_mod (
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.i_clk( clk ),
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.i_rst( rst ),
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.i_mul ( mul_fe_o_if ),
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.o_mul ( mul_fe_i_if )
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);
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adder_pipe # (
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.BITS ( bls12_381_pkg::DAT_BITS ),
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.P ( P ),
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.CTL_BITS ( CTL_BITS ),
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.LEVEL ( 2 )
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)
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adder_pipe (
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.i_clk ( clk ),
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.i_rst ( rst ),
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.i_add ( add_fe_o_if[4] ),
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.o_add ( add_fe_i_if[4] )
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);
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subtractor_pipe # (
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.BITS ( bls12_381_pkg::DAT_BITS ),
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.P ( P ),
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.CTL_BITS ( CTL_BITS ),
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.LEVEL ( 2 )
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)
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subtractor_pipe (
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.i_clk ( clk ),
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.i_rst ( rst ),
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.i_sub ( sub_fe_o_if[5] ),
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.o_sub ( sub_fe_i_if[5] )
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);
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ec_fe2_mul_s #(
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.FE_TYPE ( FE_TYPE ),
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.CTL_BITS ( CTL_BITS )
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)
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ec_fe2_mul_s (
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.i_clk ( clk ),
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.i_rst ( rst ),
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.o_mul_fe2_if ( mul_fe2_i_if ),
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.i_mul_fe2_if ( mul_fe2_o_if ),
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.o_add_fe_if ( add_fe_o_if[0] ),
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.i_add_fe_if ( add_fe_i_if[0] ),
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.o_sub_fe_if ( sub_fe_o_if[0] ),
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.i_sub_fe_if ( sub_fe_i_if[0] ),
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.o_mul_fe_if ( mul_fe_o_if ),
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.i_mul_fe_if ( mul_fe_i_if )
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);
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fe2_mul_by_nonresidue_s #(
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.FE_TYPE ( FE_TYPE )
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)
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fe2_mul_by_nonresidue_s (
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.i_clk ( clk ),
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.i_rst ( rst ),
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.o_mnr_fe2_if ( mnr_fe2_i_if[2] ),
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.i_mnr_fe2_if ( mnr_fe2_o_if[2] ),
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.o_add_fe_if ( add_fe_o_if[1] ),
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.i_add_fe_if ( add_fe_i_if[1] ),
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.o_sub_fe_if ( sub_fe_o_if[1] ),
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.i_sub_fe_if ( sub_fe_i_if[1] )
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);
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ec_fe6_mul_s #(
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.FE_TYPE ( FE_TYPE ),
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.FE2_TYPE ( FE2_TYPE ),
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.FE6_TYPE ( FE6_TYPE ),
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.CTL_BITS ( CTL_BITS ),
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.OVR_WRT_BIT ( 0 )
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)
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ec_fe6_mul_s (
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.i_clk ( clk ),
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.i_rst ( rst ),
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.o_mul_fe2_if ( mul_fe2_o_if ),
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.i_mul_fe2_if ( mul_fe2_i_if ),
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.o_add_fe_if ( add_fe_o_if[2] ),
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.i_add_fe_if ( add_fe_i_if[2] ),
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.o_sub_fe_if ( sub_fe_o_if[2] ),
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.i_sub_fe_if ( sub_fe_i_if[2] ),
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.o_mnr_fe2_if ( mnr_fe2_o_if[0] ),
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.i_mnr_fe2_if ( mnr_fe2_i_if[0] ),
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.o_mul_fe6_if ( mul_fe6_i_if ),
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.i_mul_fe6_if ( mul_fe6_o_if )
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);
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fe6_mul_by_nonresidue_s #(
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.FE_TYPE ( FE_TYPE )
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)
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fe6_mul_by_nonresidue_s (
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.i_clk ( clk ),
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.i_rst ( rst ),
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.o_mnr_fe2_if ( mnr_fe2_o_if[1] ),
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.i_mnr_fe2_if ( mnr_fe2_i_if[1] ),
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.o_mnr_fe6_if ( mnr_fe6_i_if ),
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.i_mnr_fe6_if ( mnr_fe6_o_if )
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);
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ec_fe12_mul_s #(
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.FE_TYPE ( FE_TYPE ),
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.OVR_WRT_BIT ( 16 ),
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.SQ_BIT(SQ_BIT)
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)
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ec_fe12_mul_s (
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.i_clk ( clk ),
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.i_rst ( rst ),
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.o_mul_fe6_if ( mul_fe6_o_if ),
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.i_mul_fe6_if ( mul_fe6_i_if ),
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.o_add_fe_if ( add_fe_o_if[3] ),
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.i_add_fe_if ( add_fe_i_if[3] ),
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.o_sub_fe_if ( sub_fe_o_if[3] ),
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.i_sub_fe_if ( sub_fe_i_if[3] ),
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.o_mnr_fe6_if ( mnr_fe6_o_if ),
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.i_mnr_fe6_if ( mnr_fe6_i_if ),
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.o_mul_fe12_if ( mul_fe12_i_if ),
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.i_mul_fe12_if ( mul_fe12_o_if )
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);
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ec_fe12_pow_s #(
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.FE_TYPE ( FE_TYPE ),
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.POW_BITS ( POW_BITS ),
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.SQ_BIT ( SQ_BIT )
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)
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ec_fe12_pow_s (
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.i_clk ( clk ),
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.i_rst ( rst ),
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.o_mul_fe12_if ( mul_fe12_o_if ),
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.i_mul_fe12_if ( mul_fe12_i_if),
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.o_sub_fe_if ( sub_fe_o_if[4] ),
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.i_sub_fe_if ( sub_fe_i_if[4] ),
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.o_pow_fe12_if ( pow_fe12_i_if ),
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.i_pow_fe12_if ( pow_fe12_o_if )
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);
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resource_share # (
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.NUM_IN ( 4 ),
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.DAT_BITS ( 2*$bits(FE_TYPE) ),
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.CTL_BITS ( CTL_BITS ),
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.OVR_WRT_BIT ( 8 ),
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.PIPELINE_IN ( 1 ),
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.PIPELINE_OUT ( 1 )
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)
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resource_share_fe_add (
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.i_clk ( clk ),
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.i_rst ( rst ),
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.i_axi ( add_fe_o_if[3:0] ),
|
||||
.o_res ( add_fe_o_if[4] ),
|
||||
.i_res ( add_fe_i_if[4] ),
|
||||
.o_axi ( add_fe_i_if[3:0] )
|
||||
);
|
||||
|
||||
resource_share # (
|
||||
.NUM_IN ( 5 ),
|
||||
.DAT_BITS ( 2*$bits(FE_TYPE) ),
|
||||
.CTL_BITS ( CTL_BITS ),
|
||||
.OVR_WRT_BIT ( 8 ),
|
||||
.PIPELINE_IN ( 1 ),
|
||||
.PIPELINE_OUT ( 1 )
|
||||
)
|
||||
resource_share_fe_sub (
|
||||
.i_clk ( clk ),
|
||||
.i_rst ( rst ),
|
||||
.i_axi ( sub_fe_o_if[4:0] ),
|
||||
.o_res ( sub_fe_o_if[5] ),
|
||||
.i_res ( sub_fe_i_if[5] ),
|
||||
.o_axi ( sub_fe_i_if[4:0] )
|
||||
);
|
||||
|
||||
resource_share # (
|
||||
.NUM_IN ( 2 ),
|
||||
.DAT_BITS ( 2*$bits(FE_TYPE) ),
|
||||
.CTL_BITS ( CTL_BITS ),
|
||||
.OVR_WRT_BIT ( 12 ),
|
||||
.PIPELINE_IN ( 1 ),
|
||||
.PIPELINE_OUT ( 1 )
|
||||
)
|
||||
resource_share_fe2_mnr (
|
||||
.i_clk ( clk ),
|
||||
.i_rst ( rst ),
|
||||
.i_axi ( mnr_fe2_o_if[1:0] ),
|
||||
.o_res ( mnr_fe2_o_if[2] ),
|
||||
.i_res ( mnr_fe2_i_if[2] ),
|
||||
.o_axi ( mnr_fe2_i_if[1:0] )
|
||||
);
|
||||
|
||||
task test(input [POW_BITS-1:0] pow);
|
||||
fe12_t a, f_exp, f_exp2, f_out;
|
||||
integer signed get_len;
|
||||
integer start_time, finish_time;
|
||||
logic [common_pkg::MAX_SIM_BYTS*8-1:0] get_dat, dat_in;
|
||||
|
||||
$display("Running test ...");
|
||||
for (int lp = 0; lp < 10; lp++) begin
|
||||
$display("Loop %d", lp);
|
||||
dat_in = 0;
|
||||
for (int i = 0; i < 2; i++)
|
||||
for (int j = 0; j < 3; j++)
|
||||
for (int k = 0; k < 2; k++) begin
|
||||
a[i][j][k] = random_vector(384/8) % P;
|
||||
dat_in[(i*6+j*2+k)*384 +: $bits(FE_TYPE)] = a[i][j][k];
|
||||
end
|
||||
|
||||
f_exp = fe12_pow(a, pow);
|
||||
|
||||
start_time = $time;
|
||||
fork
|
||||
pow_fe12_o_if.put_stream(dat_in, 12*384/8, pow);
|
||||
pow_fe12_i_if.get_stream(get_dat, get_len);
|
||||
join
|
||||
finish_time = $time;
|
||||
|
||||
for (int i = 0; i < 2; i++)
|
||||
for (int j = 0; j < 3; j++)
|
||||
for (int k = 0; k < 2; k++)
|
||||
f_out[i][j][k] = get_dat[(i*6+j*2+k)*384 +: $bits(FE_TYPE)];
|
||||
|
||||
if (f_exp != f_out) begin
|
||||
$display("Input a was:");
|
||||
print_fe12(a);
|
||||
$display("Output was:");
|
||||
print_fe12(f_out);
|
||||
$display("Output Expected:");
|
||||
print_fe12(f_exp);
|
||||
$fatal(1, "%m %t ERROR: output was wrong", $time);
|
||||
end
|
||||
|
||||
$display("test PASSED in %d clocks", (finish_time-start_time)/CLK_PERIOD);
|
||||
end
|
||||
|
||||
endtask
|
||||
|
||||
|
||||
initial begin
|
||||
pow_fe12_o_if.reset_source();
|
||||
pow_fe12_i_if.rdy = 0;
|
||||
#(50*CLK_PERIOD)
|
||||
|
||||
test(bls12_381_pkg::ATE_X);
|
||||
|
||||
#50ns $finish();
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue