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Bugfix: Multiplier was not handeling backpressure correctly in some 

cases so fixed it to be similier for now. Updated testbench.
This commit is contained in:
bsdevlin 2019-08-22 16:22:30 +08:00
parent 6453e94724
commit dbed8ccb0d
3 changed files with 15 additions and 8 deletions
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2
ip_cores/util/src/rtl/barret_mod_pipe.sv
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@ -154,7 +154,7 @@ end
// Fifo to store inputs (as we need to do final subtraction) // Fifo to store inputs (as we need to do final subtraction)
axi_stream_fifo #( axi_stream_fifo #(
.SIZE ( 32 ), .SIZE ( 16 ),
.DAT_BITS ( 2*K + 2 ), .DAT_BITS ( 2*K + 2 ),
.CTL_BITS ( CTL_BITS ) .CTL_BITS ( CTL_BITS )
) )

12
ip_cores/util/src/rtl/karatsuba_ofman_mult.sv
View File

@ -53,13 +53,13 @@ logic [LEVEL*3-1:0][CTL_BITS-1:0] ctl;
always_comb begin always_comb begin
o_val = val[LEVEL*3-1]; o_val = val[LEVEL*3-1];
o_ctl = ctl[LEVEL*3-1]; o_ctl = ctl[LEVEL*3-1];
o_rdy = ~o_val || (o_val && i_rdy); o_rdy = i_rdy;
end end
always_ff @ (posedge i_clk) begin always_ff @ (posedge i_clk) begin
if (i_rst) begin if (i_rst) begin
val <= 0; val <= 0;
end else begin end else begin
if(~o_val || (o_val && i_rdy)) begin if(i_rdy) begin
val <= {val, i_val}; val <= {val, i_val};
end end
end end
@ -78,7 +78,7 @@ always_ff @ (posedge i_clk) begin
dat_b <= 0; dat_b <= 0;
sign <= 0; sign <= 0;
end else begin end else begin
if(~o_val || (o_val && i_rdy)) begin if(i_rdy) begin
o_dat <= q; o_dat <= q;
ctl <= {ctl, i_ctl}; ctl <= {ctl, i_ctl};
a0_ <= a0; a0_ <= a0;
@ -126,7 +126,7 @@ generate
.o_val ( ), .o_val ( ),
.i_ctl ( ctl[0] ), .i_ctl ( ctl[0] ),
.o_ctl ( ), .o_ctl ( ),
.i_rdy ( o_rdy ), .i_rdy ( i_rdy ),
.o_rdy ( ), .o_rdy ( ),
.o_dat ( m0 ) .o_dat ( m0 )
); );
@ -145,7 +145,7 @@ generate
.o_val (), .o_val (),
.i_ctl ( ctl[0] ), .i_ctl ( ctl[0] ),
.o_ctl (), .o_ctl (),
.i_rdy ( o_rdy ), .i_rdy ( i_rdy ),
.o_rdy (), .o_rdy (),
.o_dat ( m2 ) .o_dat ( m2 )
); );
@ -164,7 +164,7 @@ generate
.o_val (), .o_val (),
.i_ctl ( ctl[0] ), .i_ctl ( ctl[0] ),
.o_ctl (), .o_ctl (),
.i_rdy ( o_rdy ), .i_rdy ( i_rdy ),
.o_rdy (), .o_rdy (),
.o_dat ( m1 ) .o_dat ( m1 )
); );

9
zcash_fpga/src/tb/bls12_381_pairing_tb.sv
View File

@ -30,7 +30,7 @@ parameter P = bls12_381_pkg::P;
af_point_t G1 = {Gy, Gx}; af_point_t G1 = {Gy, Gx};
fp2_af_point_t G2 = {G2y, G2x}; fp2_af_point_t G2 = {G2y, G2x};
localparam CTL_BITS = 84; localparam CTL_BITS = 128;
localparam CLK_PERIOD = 100; localparam CLK_PERIOD = 100;
@ -52,6 +52,8 @@ if_axi_stream #(.DAT_BYTS(($bits(FE_TYPE)+7)/8), .CTL_BITS(CTL_BITS)) out_if(clk
if_axi_stream #(.DAT_BITS(2*$bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) mul_fe_o_if(clk); if_axi_stream #(.DAT_BITS(2*$bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) mul_fe_o_if(clk);
if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) mul_fe_i_if(clk); if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) mul_fe_i_if(clk);
if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) o_p_jb_if(clk);
if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) inv_fe_o_if(clk); if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) inv_fe_o_if(clk);
if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) inv_fe_i_if(clk); if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) inv_fe_i_if(clk);
if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) inv_fe2_o_if(clk); if_axi_stream #(.DAT_BITS($bits(FE_TYPE)), .CTL_BITS(CTL_BITS)) inv_fe2_o_if(clk);
@ -80,6 +82,9 @@ bls12_381_pairing_wrapper (
.o_rdy ( in_if.rdy ), .o_rdy ( in_if.rdy ),
.i_g1_af ( in_if.dat[0 +: $bits(af_point_t)] ), .i_g1_af ( in_if.dat[0 +: $bits(af_point_t)] ),
.i_g2_af ( in_if.dat[$bits(af_point_t) +: $bits(fp2_af_point_t)] ), .i_g2_af ( in_if.dat[$bits(af_point_t) +: $bits(fp2_af_point_t)] ),
.i_mode ( 1'd0 ),
.i_key ( 381'd0 ),
.o_p_jb_if ( o_p_jb_if ),
.o_fe12_if ( out_if ), .o_fe12_if ( out_if ),
.o_mul_fe_if ( mul_fe_o_if ), .o_mul_fe_if ( mul_fe_o_if ),
.i_mul_fe_if ( mul_fe_i_if ), .i_mul_fe_if ( mul_fe_i_if ),
@ -140,6 +145,8 @@ begin
for (int k = 0; k < 2; k++) for (int k = 0; k < 2; k++)
f_out[i][j][k] = get_dat[(i*6+j*2+k)*384 +: $bits(FE_TYPE)]; f_out[i][j][k] = get_dat[(i*6+j*2+k)*384 +: $bits(FE_TYPE)];
$display("Expected:"); $display("Expected:");
print_fe12(f_exp); print_fe12(f_exp);
$display("Was:"); $display("Was:");