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zcash-fpga
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updates to ec point add

This commit is contained in:
bsdevlin 2019-06-09 17:52:41 +08:00
parent e77f79c1eb
commit dcdbc97957
4 changed files with 58 additions and 46 deletions
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4
README.md
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@ -2,10 +2,6 @@
Repo for Zcash FPGA projects code and documents. Architecture document is [here]().
## Overview
These have been designed targetted for Xilinx boards (US+) and therefore contain Xilinx-specific IP.
## apps
This contains general apps used in generating data / interfacing with the FPGA

27
ip_cores/common/src/rtl/common_if.sv
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@ -160,6 +160,7 @@ interface if_axi_stream # (
endinterface
// This uses byte addressing
interface if_axi_mm # (
parameter D_BITS = 64,
parameter A_BITS = 8
@ -202,6 +203,19 @@ interface if_axi_mm # (
reset_source();
endtask
// For writing multiple words
task automatic put_data_multiple(input logic [common_pkg::MAX_SIM_BYTS*8-1:0] data,
input logic [A_BITS-1:0] addr);
while (data != 0) begin
put_data(data, addr);
data = data >> D_BITS;
addr = addr + D_BITS/8;
end
endtask
task automatic get_data(ref logic [D_BITS-1:0] data, input logic [A_BITS-1:0] addr_in);
reset_source();
@(posedge i_clk);
@ -221,14 +235,15 @@ endinterface
interface if_ram # (
parameter RAM_WIDTH = 32,
parameter RAM_DEPTH = 128
parameter RAM_DEPTH = 128,
parameter BYT_EN = 1
)(
input i_clk, i_rst
);
logic [$clog2(RAM_DEPTH)-1:0] a;
logic [RAM_DEPTH-1:0] a;
logic en;
logic we;
logic [BYT_EN -1:0] we;
logic re;
logic [RAM_WIDTH-1:0 ] d, q;
@ -244,11 +259,11 @@ interface if_ram # (
d <= 0;
endtask
task automatic write_data(input logic [$clog2(RAM_DEPTH)-1:0] addr,
task automatic write_data(input logic [RAM_DEPTH-1:0] addr,
input logic [common_pkg::MAX_SIM_BYTS*8-1:0] data);
integer len_bits = $clog2(data);
@(posedge i_clk);
a = addr;
while (len_bits > 0) begin

56
ip_cores/ec/src/rtl/ec_fp_point_add.sv → ip_cores/ec/src/rtl/ec_point_add.sv
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@ -17,22 +17,23 @@
along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
module ec_fp_point_add
module ec_point_add
#(
parameter P,
parameter type POINT_TYPE
parameter type FP_TYPE,
parameter type FE_TYPE
)(
input i_clk, i_rst,
// Input points
input POINT_TYPE i_p1,
input POINT_TYPE i_p2,
input logic i_val,
output logic o_rdy,
input FP_TYPE i_p1,
input FP_TYPE i_p2,
input logic i_val,
output logic o_rdy,
// Output point
output POINT_TYPE o_p,
input logic i_rdy,
output logic o_val,
output logic o_err,
output FP_TYPE o_p,
input logic i_rdy,
output logic o_val,
output logic o_err,
// Interface to multiplier (mod P)
if_axi_stream.source o_mult_if,
if_axi_stream.sink i_mult_if,
@ -41,10 +42,9 @@ module ec_fp_point_add
if_axi_stream.sink i_add_if,
// Interface to subtractor (mod P)
if_axi_stream.source o_sub_if,
if_axi_stream.sink i_sub_if
if_axi_stream.sink i_sub_if
);
localparam DAT_BITS = $clog2(P);
/*
These are the equations that need to be computed, they are issued as variables
@ -94,8 +94,8 @@ localparam DAT_BITS = $clog2(P);
logic [23:0] eq_val, eq_wait;
// Temporary variables
logic [DAT_BITS-1:0] A, B, C, D;
POINT_TYPE i_p1_l, i_p2_l;
FE_TYPE A, B, C, D;
FP_TYPE i_p1_l, i_p2_l;
enum {IDLE, START, FINISHED} state;
always_ff @ (posedge i_clk) begin
@ -124,7 +124,7 @@ always_ff @ (posedge i_clk) begin
if (o_mult_if.rdy) o_mult_if.val <= 0;
if (o_add_if.rdy) o_add_if.val <= 0;
if (o_sub_if.rdy) o_sub_if.val <= 0;
case(state)
{IDLE}: begin
o_rdy <= 1;
@ -190,7 +190,7 @@ always_ff @ (posedge i_clk) begin
default: o_err <= 1;
endcase
end
// Check any results from adder
if (i_add_if.val && i_add_if.rdy) begin
eq_val[i_add_if.ctl[5:0]] <= 1;
@ -198,8 +198,8 @@ always_ff @ (posedge i_clk) begin
16: i_p1_l.x <= i_add_if.dat;
default: o_err <= 1;
endcase
end
end
// Check any results from subtractor
if (i_sub_if.val && i_sub_if.rdy) begin
eq_val[i_sub_if.ctl[5:0]] <= 1;
@ -212,7 +212,7 @@ always_ff @ (posedge i_clk) begin
21: o_p.y <= i_sub_if.dat;
default: o_err <= 1;
endcase
end
end
// Issue new multiplies
if (~eq_wait[0]) begin // 0. A = i_p2.z*i_p2.z mod p
@ -322,33 +322,33 @@ always_ff @ (posedge i_clk) begin
end
// Task for subtractions
task subtraction(input int unsigned ctl, input logic [DAT_BITS-1:0] a, b);
task subtraction(input int unsigned ctl, input FE_TYPE a, b);
if (~o_sub_if.val || (o_sub_if.val && o_sub_if.rdy)) begin
o_sub_if.val <= 1;
o_sub_if.dat[0 +: DAT_BITS] <= a;
o_sub_if.dat[DAT_BITS +: DAT_BITS] <= b;
o_sub_if.dat[0 +: $bits(FE_TYPE)] <= a;
o_sub_if.dat[$bits(FE_TYPE) +: $bits(FE_TYPE)] <= b;
o_sub_if.ctl[5:0] <= ctl;
eq_wait[ctl] <= 1;
end
endtask
// Task for addition
task addition(input int unsigned ctl, input logic [DAT_BITS-1:0] a, b);
task addition(input int unsigned ctl, input FE_TYPE a, b);
if (~o_add_if.val || (o_add_if.val && o_add_if.rdy)) begin
o_add_if.val <= 1;
o_add_if.dat[0 +: DAT_BITS] <= a;
o_add_if.dat[DAT_BITS +: DAT_BITS] <= b;
o_add_if.dat[0 +: $bits(FE_TYPE)] <= a;
o_add_if.dat[$bits(FE_TYPE) +: $bits(FE_TYPE)] <= b;
o_add_if.ctl[5:0] <= ctl;
eq_wait[ctl] <= 1;
end
endtask
// Task for using multiplies
task multiply(input int unsigned ctl, input logic [DAT_BITS-1:0] a, b);
task multiply(input int unsigned ctl, input FE_TYPE a, b);
if (~o_mult_if.val || (o_mult_if.val && o_mult_if.rdy)) begin
o_mult_if.val <= 1;
o_mult_if.dat[0 +: DAT_BITS] <= a;
o_mult_if.dat[DAT_BITS +: DAT_BITS] <= b;
o_mult_if.dat[0 +: $bits(FE_TYPE)] <= a;
o_mult_if.dat[$bits(FE_TYPE) +: $bits(FE_TYPE)] <= b;
o_mult_if.ctl[5:0] <= ctl;
eq_wait[ctl] <= 1;
end

17
ip_cores/ec/src/tb/ec_fp_point_add_tb.sv → ip_cores/ec/src/tb/ec_point_add_tb.sv
View File

@ -16,7 +16,7 @@
*/
`timescale 1ps/1ps
module ec_fp_point_add_tb ();
module ec_point_add_tb ();
import common_pkg::*;
import bls12_381_pkg::*;
@ -66,11 +66,12 @@ always_ff @ (posedge clk)
if (out_if.val && out_if.err)
$error(1, "%m %t ERROR: output .err asserted", $time);
ec_fp_point_add #(
.P ( P ),
.POINT_TYPE ( jb_point_t )
ec_point_add #(
.P ( P ),
.FP_TYPE ( jb_point_t ),
.FE_TPYE ( fe_t )
)
ec_fp_point_add (
ec_point_add (
.i_clk ( clk ),
.i_rst ( rst ),
// Input points
@ -95,16 +96,16 @@ always_comb begin
mult_out_if.eop = 1;
mult_out_if.err = 0;
mult_out_if.mod = 1;
add_out_if.sop = 1;
add_out_if.eop = 1;
add_out_if.err = 0;
add_out_if.mod = 1;
sub_out_if.sop = 1;
sub_out_if.eop = 1;
sub_out_if.err = 0;
sub_out_if.mod = 1;
sub_out_if.mod = 1;
end