updating AWS test c program
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261842a774
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@ -170,15 +170,21 @@ int write_stream(uint8_t* data, unsigned int len) {
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while(len_send < len) {
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fpga_pci_poke64(pci_bar_handle_bar4, 0, *(uint64_t*)(&data[len_send]));
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len_send += 8;
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if (AXI4_enabled) {
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fpga_pci_poke64(pci_bar_handle_bar4, 0, *(uint64_t*)(&data[len_send]));
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len_send += 8;
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} else {
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rc = fpga_pci_poke(pci_bar_handle_bar0, AXI_FIFO_OFFSET+0x10ULL, *(uint32_t*)(&data[len_send])); // Reset ISR
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fail_on(rc, out, "Unable to write to FPGA!");
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len_send += 4;
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}
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}
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rc = fpga_pci_poke(pci_bar_handle_bar0, AXI_FIFO_OFFSET+0x14ULL, len); // Reset ISR
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fail_on(rc, out, "Unable to write to FPGA!");
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printf("INFO: write_stream::Wrote %d bytes of data", len);
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printf("INFO: write_stream::Wrote %d bytes of data\n", len);
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// Check transmit complete bit and reset it
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rc = fpga_pci_peek(pci_bar_handle_bar0, AXI_FIFO_OFFSET, &rdata);
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@ -224,9 +230,15 @@ int read_stream(uint8_t* data, unsigned int size) {
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fail_on(rc, out, "Unable to read from FPGA!");
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while(rdata > 0 && size >= read_len+8) {
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rc = fpga_pci_peek64(pci_bar_handle_bar4, 0x1000, (uint64_t*)(&data[read_len]));
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fail_on(rc, out, "Unable to read from FPGA PCIS!");
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read_len += 8;
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if (AXI4_enabled) {
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rc = fpga_pci_peek64(pci_bar_handle_bar4, 0x1000, (uint64_t*)(&data[read_len]));
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fail_on(rc, out, "Unable to read from FPGA PCIS!");
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read_len += 8;
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} else {
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rc = fpga_pci_peek(pci_bar_handle_bar0, AXI_FIFO_OFFSET + 0x20ULL, (uint32_t*)(&data[read_len]));
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fail_on(rc, out, "Unable to read from FPGA!");
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read_len += 4;
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}
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}
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printf("INFO: Read %d bytes from read_stream()\n", read_len);
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