New zcash AWS file cut down
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// Amazon FPGA Hardware Development Kit
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//
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// Copyright 2016-2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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//
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// Licensed under the Amazon Software License (the "License"). You may not use
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// this file except in compliance with the License. A copy of the License is
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// located at
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//
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// http://aws.amazon.com/asl/
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//
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// or in the "license" file accompanying this file. This file is distributed on
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// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
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// implied. See the License for the specific language governing permissions and
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// limitations under the License.
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// CL Streaming
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module zcash_cl
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(
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`include "cl_ports.vh"
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);
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logic clk;
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assign clk = clk_main_a0; // 125MHz
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assign rst_n = rst_main_n;
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`ifndef CL_VERSION
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`define CL_VERSION 32'h10df_f002
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`endif
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`include "cl_id_defines.vh"
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assign cl_sh_id0 = `CL_SH_ID0;
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assign cl_sh_id1 = `CL_SH_ID1;
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logic zcash_h2c_axis_valid;
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logic [511:0] zcash_h2c_axis_data;
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logic [63:0] zcash_h2c_axis_keep;
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logic zcash_h2c_axis_last;
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logic zcash_h2c_axis_ready;
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logic [2:0] zcash_h2c_axis_id;
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logic zcash_c2h_axis_valid;
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logic [511:0] zcash_c2h_axis_data;
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logic [63:0] zcash_c2h_axis_keep;
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logic zcash_c2h_axis_last;
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logic zcash_c2h_axis_ready;
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logic [2:0] zcash_c2h_axis_id;
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logic sh_ocl_awvalid_q;
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logic [31:0] sh_ocl_awaddr_q;
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logic ocl_sh_awready_q;
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logic sh_ocl_wvalid_q;
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logic [31:0] sh_ocl_wdata_q;
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logic [ 3:0] sh_ocl_wstrb_q;
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logic ocl_sh_wready_q;
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logic ocl_sh_bvalid_q;
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logic [ 1:0] ocl_sh_bresp_q;
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logic sh_ocl_bready_q;
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logic sh_ocl_arvalid_q;
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logic [31:0] sh_ocl_araddr_q;
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logic ocl_sh_arready_q;
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logic ocl_sh_rvalid_q;
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logic [31:0] ocl_sh_rdata_q;
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logic [ 1:0] ocl_sh_rresp_q;
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logic sh_ocl_rready_q;
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logic sh_ocl_awvalid_q2;
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logic [31:0] sh_ocl_awaddr_q2;
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logic ocl_sh_awready_q2;
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logic sh_ocl_wvalid_q2;
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logic [31:0] sh_ocl_wdata_q2;
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logic [ 3:0] sh_ocl_wstrb_q2;
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logic ocl_sh_wready_q2;
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logic ocl_sh_bvalid_q2;
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logic [ 1:0] ocl_sh_bresp_q2;
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logic sh_ocl_bready_q2;
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logic sh_ocl_arvalid_q2;
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logic [31:0] sh_ocl_araddr_q2;
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logic ocl_sh_arready_q2;
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logic ocl_sh_rvalid_q2;
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logic [31:0] ocl_sh_rdata_q2;
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logic [ 1:0] ocl_sh_rresp_q2;
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logic sh_ocl_rready_q2;
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logic [15:0] sh_cl_dma_pcis_awid_q ;
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logic [63:0] sh_cl_dma_pcis_awaddr_q ;
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logic [7:0] sh_cl_dma_pcis_awlen_q ;
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logic [2:0] sh_cl_dma_pcis_awsize_q ;
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logic sh_cl_dma_pcis_awvalid_q;
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logic cl_sh_dma_pcis_awready_q;
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logic [511:0] sh_cl_dma_pcis_wdata_q ;
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logic [63:0] sh_cl_dma_pcis_wstrb_q ;
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logic sh_cl_dma_pcis_wlast_q ;
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logic sh_cl_dma_pcis_wvalid_q ;
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logic cl_sh_dma_pcis_wready_q ;
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logic [15:0] cl_sh_dma_pcis_bid_q ;
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logic [1:0] cl_sh_dma_pcis_bresp_q ;
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logic cl_sh_dma_pcis_bvalid_q ;
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logic sh_cl_dma_pcis_bready_q ;
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logic [15:0] sh_cl_dma_pcis_arid_q ;
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logic [63:0] sh_cl_dma_pcis_araddr_q ;
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logic [7:0] sh_cl_dma_pcis_arlen_q ;
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logic [2:0] sh_cl_dma_pcis_arsize_q ;
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logic sh_cl_dma_pcis_arvalid_q;
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logic cl_sh_dma_pcis_arready_q;
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logic [15:0] cl_sh_dma_pcis_rid_q ;
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logic [511:0] cl_sh_dma_pcis_rdata_q ;
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logic [1:0] cl_sh_dma_pcis_rresp_q ;
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logic cl_sh_dma_pcis_rlast_q ;
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logic cl_sh_dma_pcis_rvalid_q ;
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logic sh_cl_dma_pcis_rready_q ;
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logic [15:0] sh_cl_dma_pcis_awid_q2 ;
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logic [63:0] sh_cl_dma_pcis_awaddr_q2 ;
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logic [7:0] sh_cl_dma_pcis_awlen_q2 ;
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logic [2:0] sh_cl_dma_pcis_awsize_q2 ;
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logic sh_cl_dma_pcis_awvalid_q2;
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logic cl_sh_dma_pcis_awready_q2;
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logic [511:0] sh_cl_dma_pcis_wdata_q2 ;
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logic [63:0] sh_cl_dma_pcis_wstrb_q2 ;
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logic sh_cl_dma_pcis_wlast_q2 ;
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logic sh_cl_dma_pcis_wvalid_q2 ;
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logic cl_sh_dma_pcis_wready_q2 ;
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logic [15:0] cl_sh_dma_pcis_bid_q2 ;
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logic [1:0] cl_sh_dma_pcis_bresp_q2 ;
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logic cl_sh_dma_pcis_bvalid_q2 ;
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logic sh_cl_dma_pcis_bready_q2 ;
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logic [15:0] sh_cl_dma_pcis_arid_q2 ;
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logic [63:0] sh_cl_dma_pcis_araddr_q2 ;
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logic [7:0] sh_cl_dma_pcis_arlen_q2 ;
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logic [2:0] sh_cl_dma_pcis_arsize_q2 ;
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logic sh_cl_dma_pcis_arvalid_q2;
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logic cl_sh_dma_pcis_arready_q2;
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logic [15:0] cl_sh_dma_pcis_rid_q2 ;
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logic [511:0] cl_sh_dma_pcis_rdata_q2 ;
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logic [1:0] cl_sh_dma_pcis_rresp_q2 ;
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logic cl_sh_dma_pcis_rlast_q2 ;
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logic cl_sh_dma_pcis_rvalid_q2 ;
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logic sh_cl_dma_pcis_rready_q2 ;
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logic rst_main_n_sync;
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`include "unused_flr_template.inc"
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`include "unused_ddr_a_b_d_template.inc"
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`include "unused_ddr_c_template.inc"
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`include "unused_cl_sda_template.inc"
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`include "unused_sh_bar1_template.inc"
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`include "unused_apppf_irq_template.inc"
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`include "unused_pcim_template.inc"
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//-------------------------------------------------
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// Reset Synchronization
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//-------------------------------------------------
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logic pre_sync_rst_n;
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always @(posedge clk_main_a0)
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if (!rst_main_n)
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begin
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pre_sync_rst_n <= 0;
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rst_main_n_sync <= 0;
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end
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else
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begin
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pre_sync_rst_n <= 1;
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rst_main_n_sync <= pre_sync_rst_n;
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end
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//////////////////////////////////////////////////////////////////////////////////
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// zcash logic
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logic cfg_wire_zcash_enb;
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localparam DAT_BYTS = 8;
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logic clk_if, clk_100, clk_200, clk_300;
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logic rst_if, rst_100, rst_200, rst_300;
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always_comb begin
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clk_if = clk_main_a0;
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clk_100 = clk_main_a0; // 125MHz
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clk_200 = clk_main_a0; // 187MHz
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clk_300 = clk_extra_b0; // 300MHz
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end
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always_ff @(posedge clk_if) rst_if <= !rst_main_n;
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always_ff @(posedge clk_100) rst_100 <= !rst_main_n;
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always_ff @(posedge clk_200) rst_200 <= !rst_main_n;
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always_ff @(posedge clk_300) rst_300 <= !rst_main_n;
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if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(1)) zcash_if_rx (clk_if);
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if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(1)) zcash_if_tx (clk_if);
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if_axi_stream #(.DAT_BYTS(64), .CTL_BITS(1)) aws_if_rx (clk_if);
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if_axi_stream #(.DAT_BYTS(64), .CTL_BITS(1)) aws_if_tx (clk_if);
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zcash_aws_wrapper zcash_aws_wrapper (
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.i_rst ( rst_if ),
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.i_clk ( clk_if ),
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.rx_aws_if ( aws_if_tx ),
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.tx_aws_if ( aws_if_rx ),
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.rx_zcash_if ( zcash_if_tx ),
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.tx_zcash_if ( zcash_if_rx )
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);
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zcash_fpga_top #(
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.DAT_BYTS ( DAT_BYTS )
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)
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zcash_fpga_top (
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// Clocks and resets
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.i_clk_100 ( clk_100 ),
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.i_rst_100 ( rst_100 ),
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.i_clk_200 ( clk_200 ),
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.i_rst_200 ( rst_200 ),
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.i_clk_300 ( clk_300 ),
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.i_rst_300 ( rst_300 ),
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.i_clk_if ( clk_if ),
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.i_rst_if ( rst_if ),
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.rx_if ( zcash_if_rx ),
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.tx_if ( zcash_if_tx )
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);
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(* dont_touch = "true" *) logic rst_main_n_sync_bot_slr;
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lib_pipe #(.WIDTH(1), .STAGES(2)) PIPE_RST_N_BOT_SLR (.clk(clk_main_a0), .rst_n(1'b1), .in_bus(rst_main_n_sync), .out_bus(rst_main_n_sync_bot_slr));
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(* dont_touch = "true" *) logic rst_main_n_sync_mid_slr;
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lib_pipe #(.WIDTH(1), .STAGES(4)) PIPE_RST_N_MID_SLR (.clk(clk_main_a0), .rst_n(1'b1), .in_bus(rst_main_n_sync), .out_bus(rst_main_n_sync_mid_slr));
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logic cfg_sde_rst;
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logic sde_rst_n_d;
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logic sde_rst_n;
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logic cfg_sde_wire_loopback;
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assign sde_rst_n_d = ~cfg_sde_rst & rst_main_n_sync_mid_slr;
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lib_pipe #(.WIDTH(1), .STAGES(1)) SDE_RST_LIB_PIPE
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(.clk (clk_main_a0), .rst_n(1'b1), .in_bus(sde_rst_n_d), .out_bus(sde_rst_n));
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logic pcim_wr_incomplete_error;
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logic pcim_wr_last_error;
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always @(posedge clk_main_a0)
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if (!sde_rst_n)
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pcim_wr_incomplete_error <= 0;
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else
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pcim_wr_incomplete_error <= pcim_wr_last_error; /*sh_cl_ctl1[8];*/
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always_comb begin
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sde_awvalid_q = 0;
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sde_awid_q = 0;
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sde_awaddr_q = 0;
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sde_wvalid_q = 0;
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sde_bready_q = 0;
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sde_arvalid_q = 0;
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sde_rready_q = 0;
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end
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// Test loopback
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always_comb begin
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// Defaults
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zcash_c2h_axis_valid = 0;
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zcash_h2c_axis_ready = 1;
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aws_if_tx.val = 0;
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aws_if_rx.rdy = 1;
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if (cfg_sde_wire_loopback) begin
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zcash_c2h_axis_valid = zcash_h2c_axis_valid;
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zcash_h2c_axis_ready = zcash_c2h_axis_ready;
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zcash_c2h_axis_data = zcash_h2c_axis_data;
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zcash_c2h_axis_keep = zcash_h2c_axis_keep;
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zcash_c2h_axis_last = zcash_h2c_axis_last;
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zcash_c2h_axis_id = zcash_h2c_axis_id;
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end
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if (cfg_wire_zcash_enb) begin
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zcash_c2h_axis_valid = aws_if_rx.val;
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aws_if_rx.rdy = zcash_c2h_axis_ready;
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zcash_c2h_axis_data = aws_if_rx.dat;
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zcash_c2h_axis_keep = aws_if_rx.get_keep_from_mod();
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zcash_c2h_axis_last = aws_if_rx.eop;
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zcash_c2h_axis_id = 3'd0;
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aws_if_tx.val = zcash_h2c_axis_valid;
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zcash_h2c_axis_ready = aws_if_tx.rdy;
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aws_if_tx.dat = zcash_h2c_axis_data;
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aws_if_tx.set_mod_from_keep(zcash_h2c_axis_keep);
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aws_if_tx.eop = zcash_h2c_axis_last;
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end
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end
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axi_mm2s_mapper axi_mm2s_mapper (
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.aclk ( clk_main_a0), // input wire aclk
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.aresetn ( sde_rst_n ), // input wire aresetn
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.s_axi_awid (sh_cl_dma_pcis_awid_q2), // input wire [15 : 0] s_axi_awid
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.s_axi_awaddr (sh_cl_dma_pcis_awaddr_q2), // input wire [63 : 0] s_axi_awaddr
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.s_axi_awlen (sh_cl_dma_pcis_awlen_q2), // input wire [7 : 0] s_axi_awlen
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.s_axi_awsize (sh_cl_dma_pcis_awsize_q2), // input wire [2 : 0] s_axi_awsize
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.s_axi_awburst( 2'd0 ), // input wire [1 : 0] s_axi_awburst
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.s_axi_awlock ( 1'd0 ), // input wire [0 : 0] s_axi_awlock
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.s_axi_awcache( 4'd0 ), // input wire [3 : 0] s_axi_awcache
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.s_axi_awprot ( 3'd0 ), // input wire [2 : 0] s_axi_awprot
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.s_axi_awqos ( 4'd0 ), // input wire [3 : 0] s_axi_awqos
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.s_axi_awvalid(sh_cl_dma_pcis_awvalid_q2), // input wire s_axi_awvalid
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.s_axi_awready(cl_sh_dma_pcis_awready_q2), // output wire s_axi_awready
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.s_axi_wdata (sh_cl_dma_pcis_wdata_q2), // input wire [511 : 0] s_axi_wdata
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.s_axi_wstrb (sh_cl_dma_pcis_wstrb_q2), // input wire [63 : 0] s_axi_wstrb
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.s_axi_wlast (sh_cl_dma_pcis_wlast_q2), // input wire s_axi_wlast
|
||||||
|
.s_axi_wvalid (sh_cl_dma_pcis_wvalid_q2), // input wire s_axi_wvalid
|
||||||
|
.s_axi_wready (cl_sh_dma_pcis_wready_q2), // output wire s_axi_wready
|
||||||
|
.s_axi_bid (cl_sh_dma_pcis_bid_q2), // output wire [15 : 0] s_axi_bid
|
||||||
|
.s_axi_bresp (cl_sh_dma_pcis_bresp_q2), // output wire [1 : 0] s_axi_bresp
|
||||||
|
.s_axi_bvalid (cl_sh_dma_pcis_bvalid_q2), // output wire s_axi_bvalid
|
||||||
|
.s_axi_bready (sh_cl_dma_pcis_bready_q2), // input wire s_axi_bready
|
||||||
|
.s_axi_arid (sh_cl_dma_pcis_arid_q2), // input wire [15 : 0] s_axi_arid
|
||||||
|
.s_axi_araddr (sh_cl_dma_pcis_araddr_q2), // input wire [63 : 0] s_axi_araddr
|
||||||
|
.s_axi_arlen (sh_cl_dma_pcis_arlen_q2), // input wire [7 : 0] s_axi_arlen
|
||||||
|
.s_axi_arsize (sh_cl_dma_pcis_arsize_q2), // input wire [2 : 0] s_axi_arsize
|
||||||
|
.s_axi_arburst( 2'd0 ), // input wire [1 : 0] s_axi_arburst
|
||||||
|
.s_axi_arlock ( 1'd0 ), // input wire [0 : 0] s_axi_arlock
|
||||||
|
.s_axi_arcache( 4'd0 ), // input wire [3 : 0] s_axi_arcache
|
||||||
|
.s_axi_arprot ( 3'd0 ), // input wire [2 : 0] s_axi_arprot
|
||||||
|
.s_axi_arqos ( 4'd0 ), // input wire [3 : 0] s_axi_arqos
|
||||||
|
.s_axi_arvalid(sh_cl_dma_pcis_arvalid_q2), // input wire s_axi_arvalid
|
||||||
|
.s_axi_arready(cl_sh_dma_pcis_arready_q2), // output wire s_axi_arready
|
||||||
|
.s_axi_rid (cl_sh_dma_pcis_rid_q2), // output wire [15 : 0] s_axi_rid
|
||||||
|
.s_axi_rdata (cl_sh_dma_pcis_rdata_q2), // output wire [511 : 0] s_axi_rdata
|
||||||
|
.s_axi_rresp (cl_sh_dma_pcis_rresp_q2), // output wire [1 : 0] s_axi_rresp
|
||||||
|
.s_axi_rlast (cl_sh_dma_pcis_rlast_q2), // output wire s_axi_rlast
|
||||||
|
.s_axi_rvalid (cl_sh_dma_pcis_rvalid_q2), // output wire s_axi_rvalid
|
||||||
|
.s_axi_rready (sh_cl_dma_pcis_rready_q2), // input wire s_axi_rready
|
||||||
|
|
||||||
|
.s_axis_tvalid (zcash_c2h_axis_valid), // input wire s_axis_tvalid
|
||||||
|
.s_axis_tready (zcash_c2h_axis_ready), // output wire s_axis_tready
|
||||||
|
.s_axis_tdata (zcash_c2h_axis_data), // input wire [511 : 0] s_axis_tdata
|
||||||
|
.s_axis_tkeep (zcash_c2h_axis_keep), // input wire [63 : 0] s_axis_tkeep
|
||||||
|
.s_axis_tlast (zcash_c2h_axis_last), // input wire s_axis_tlast
|
||||||
|
.s_axis_tid (zcash_c2h_axis_id), // input wire [2 : 0] s_axis_tid
|
||||||
|
|
||||||
|
.m_axis_tvalid (zcash_h2c_axis_valid), // output wire m_axis_tvalid
|
||||||
|
.m_axis_tready (zcash_h2c_axis_ready), // input wire m_axis_tready
|
||||||
|
.m_axis_tdata (zcash_h2c_axis_data), // output wire [511 : 0] m_axis_tdata
|
||||||
|
.m_axis_tkeep (zcash_h2c_axis_keep), // output wire [63 : 0] m_axis_tkeep
|
||||||
|
.m_axis_tlast (zcash_h2c_axis_last), // output wire m_axis_tlast
|
||||||
|
.m_axis_tid (zcash_h2c_axis_id) // output wire [2 : 0] m_axis_tid
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
//-------------------------------------
|
||||||
|
// OCL AXI-L Handling (CSRs)
|
||||||
|
//-------------------------------------
|
||||||
|
//--------------------------------------------------------------
|
||||||
|
// PCIe OCL AXI-L Slave Accesses (accesses from PCIe AppPF BAR0)
|
||||||
|
//--------------------------------------------------------------
|
||||||
|
// Only supports single-beat accesses.
|
||||||
|
|
||||||
|
// Address Range
|
||||||
|
// 0x0000 - 0x0ffc : CL_SDE_SRM
|
||||||
|
// 0x2000 - General Purpose Config Reg 0
|
||||||
|
// Bit 0 - Reset SDE
|
||||||
|
//
|
||||||
|
// 0x2004 - General Purpose Config Reg 1
|
||||||
|
// 0x2008 - General Purpose Config Reg 2
|
||||||
|
// 0x200c - General Purpose Config Reg 3
|
||||||
|
|
||||||
|
logic awvalid;
|
||||||
|
logic [31:0] awaddr;
|
||||||
|
logic wvalid;
|
||||||
|
logic [31:0] wdata;
|
||||||
|
logic [3:0] wstrb;
|
||||||
|
logic bready;
|
||||||
|
logic arvalid;
|
||||||
|
logic [31:0] araddr;
|
||||||
|
logic rready;
|
||||||
|
|
||||||
|
logic awready;
|
||||||
|
logic wready;
|
||||||
|
logic bvalid;
|
||||||
|
logic [1:0] bresp;
|
||||||
|
logic arready;
|
||||||
|
logic rvalid;
|
||||||
|
logic [31:0] rdata;
|
||||||
|
logic [1:0] rresp;
|
||||||
|
|
||||||
|
// Inputs
|
||||||
|
assign awvalid = sh_ocl_awvalid_q2;
|
||||||
|
assign awaddr[31:0] = sh_ocl_awaddr_q2;
|
||||||
|
assign wvalid = sh_ocl_wvalid_q2;
|
||||||
|
assign wdata[31:0] = sh_ocl_wdata_q2;
|
||||||
|
assign wstrb[3:0] = sh_ocl_wstrb_q2;
|
||||||
|
assign bready = sh_ocl_bready_q2;
|
||||||
|
assign arvalid = sh_ocl_arvalid_q2;
|
||||||
|
assign araddr[31:0] = sh_ocl_araddr_q2;
|
||||||
|
assign rready = sh_ocl_rready_q2;
|
||||||
|
|
||||||
|
// Outputs
|
||||||
|
assign ocl_sh_awready_q2 = awready;
|
||||||
|
assign ocl_sh_wready_q2 = wready;
|
||||||
|
assign ocl_sh_bvalid_q2 = bvalid;
|
||||||
|
assign ocl_sh_bresp_q2 = bresp[1:0];
|
||||||
|
assign ocl_sh_arready_q2 = arready;
|
||||||
|
assign ocl_sh_rvalid_q2 = rvalid;
|
||||||
|
assign ocl_sh_rdata_q2 = rdata;
|
||||||
|
assign ocl_sh_rresp_q2 = rresp[1:0];
|
||||||
|
|
||||||
|
// Write Request
|
||||||
|
logic wr_active;
|
||||||
|
logic [31:0] wr_addr;
|
||||||
|
logic wr_req; //Note these are pulses
|
||||||
|
logic rd_req; //Note these are pulses
|
||||||
|
logic[31:0] wdata_q;
|
||||||
|
|
||||||
|
logic wr_req_lvl; //Level versions of the requests
|
||||||
|
logic rd_req_lvl;
|
||||||
|
|
||||||
|
logic arvalid_q;
|
||||||
|
logic [31:0] araddr_q;
|
||||||
|
|
||||||
|
|
||||||
|
logic wr_done;
|
||||||
|
logic rd_done;
|
||||||
|
logic[31:0] cfg_ctl_reg[3:0] = '{default:'0};
|
||||||
|
|
||||||
|
always @(posedge clk_main_a0)
|
||||||
|
if (!rst_main_n_sync_mid_slr) begin
|
||||||
|
wr_active <= 0;
|
||||||
|
wr_addr <= 0;
|
||||||
|
wr_req <= 0;
|
||||||
|
wdata_q <= 0;
|
||||||
|
wr_req_lvl <= 0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
wr_active <= wr_active && bvalid && bready ? 1'b0 :
|
||||||
|
~wr_active && awvalid ? 1'b1 :
|
||||||
|
wr_active;
|
||||||
|
wr_addr <= awvalid && ~wr_active ? awaddr : wr_addr ;
|
||||||
|
|
||||||
|
//Request is a pulse
|
||||||
|
wr_req <= (wr_active && wvalid && wready);
|
||||||
|
|
||||||
|
wdata_q <= (wvalid && wready)? wdata: wdata_q;
|
||||||
|
|
||||||
|
wr_req_lvl <= (wr_active && wvalid && wready) || (wr_req_lvl && !wr_done);
|
||||||
|
end
|
||||||
|
|
||||||
|
assign awready = ~wr_active;
|
||||||
|
assign wready = wr_active && wvalid;
|
||||||
|
|
||||||
|
// Write Response
|
||||||
|
always @(posedge clk_main_a0)
|
||||||
|
if (!rst_main_n_sync_mid_slr)
|
||||||
|
bvalid <= 0;
|
||||||
|
else
|
||||||
|
bvalid <= bvalid && bready ? 1'b0 :
|
||||||
|
~bvalid && wr_done ? 1'b1 :
|
||||||
|
bvalid;
|
||||||
|
assign bresp = 0;
|
||||||
|
|
||||||
|
|
||||||
|
// Read Request
|
||||||
|
always @(posedge clk_main_a0)
|
||||||
|
if (!rst_main_n_sync_mid_slr) begin
|
||||||
|
arvalid_q <= 0;
|
||||||
|
araddr_q <= 0;
|
||||||
|
rd_req <= 0;
|
||||||
|
rd_req_lvl <= 0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
arvalid_q <= arvalid;
|
||||||
|
araddr_q <= arvalid ? araddr : araddr_q;
|
||||||
|
rd_req <= (arvalid && arready);
|
||||||
|
rd_req_lvl <= (arvalid && arready) || (rd_req_lvl && !rd_done);
|
||||||
|
end
|
||||||
|
|
||||||
|
assign arready = !arvalid_q && !rvalid;
|
||||||
|
// Read Response
|
||||||
|
always @(posedge clk_main_a0)
|
||||||
|
if (!rst_main_n_sync_mid_slr)
|
||||||
|
begin
|
||||||
|
rvalid <= 0;
|
||||||
|
rdata <= 0;
|
||||||
|
rresp <= 0;
|
||||||
|
end
|
||||||
|
else if (rvalid && rready)
|
||||||
|
begin
|
||||||
|
rvalid <= 0;
|
||||||
|
rdata <= 0;
|
||||||
|
rresp <= 0;
|
||||||
|
end
|
||||||
|
else if (rd_done)
|
||||||
|
begin
|
||||||
|
rvalid <= 1;
|
||||||
|
rdata <= {16'hbeef, cfg_ctl_reg[araddr_q[3:2]][15:0]};
|
||||||
|
end
|
||||||
|
|
||||||
|
assign rd_done = rd_req;
|
||||||
|
assign wr_done = wr_req;
|
||||||
|
|
||||||
|
|
||||||
|
//5 general purpose control registers
|
||||||
|
always @(posedge clk_main_a0)
|
||||||
|
if (wr_req)
|
||||||
|
cfg_ctl_reg[wr_addr[3:2]] <= wdata_q;
|
||||||
|
|
||||||
|
assign cfg_sde_wire_loopback = cfg_ctl_reg[0][1];
|
||||||
|
assign cfg_wire_zcash_enb = cfg_ctl_reg[2][0];
|
||||||
|
|
||||||
|
|
||||||
|
//Needed for board_tb simulation
|
||||||
|
logic[3:0] all_ddr_is_ready;
|
||||||
|
|
||||||
|
endmodule // cl_sde
|
Loading…
Reference in New Issue