Width change fifo update

ip_cores/fifo/src/rtl/width_change_cdc_fifo.sv

@@ -52,6 +52,52 @@ if_axi_stream #(.DAT_BYTS(IN_DAT_BYTS), .CTL_BITS(CTL_BITS)) o_axi_int (i_clk_b)
 logic [$clog2(MAX_BYTS)-1:0] byt_cnt;
 logic sop_l;
 
+generate if (SHIFT_DOWN) begin
+
+  always_ff @ (posedge i_clk_b) begin
+    if (i_rst_b) begin
+      o_axi_b.reset_source();
+      byt_cnt <= 0;
+      sop_l <= 0;
+      o_axi_int.rdy <= 0;
+    end else begin
+
+      o_axi_int.rdy <= 0;
+
+      if (~o_axi_b.val || (o_axi_b.val && o_axi_b.rdy)) begin
+
+        if (o_axi_int.val) begin
+
+          if (~sop_l) begin
+            o_axi_b.ctl <= o_axi_int.ctl;
+            o_axi_b.err <= o_axi_int.err;
+            sop_l <= 1;
+          end
+          o_axi_b.dat <= o_axi_int.dat[byt_cnt*8 +: OUT_DAT_BITS];
+          o_axi_b.sop <= ~sop_l;
+          o_axi_b.val <= 1;
+
+          byt_cnt <= byt_cnt + OUT_DAT_BYTS;
+
+          // Detect the last data
+          if ((byt_cnt + OUT_DAT_BYTS == IN_DAT_BYTS) || (o_axi_int.eop && o_axi_int.mod != 0 && (byt_cnt + OUT_DAT_BYTS >= o_axi_int.mod))) begin
+            byt_cnt <= 0;
+            o_axi_int.rdy <= 1;
+            if (o_axi_int.eop) begin
+              o_axi_b.eop <= 1;
+              o_axi_b.mod <= o_axi_int.mod == 0 ? 0 : (o_axi_int.mod % OUT_DAT_BYTS);
+              sop_l <= 0;
+            end
+          end
+        end
+
+      end
+    end
+  end
+
+
+end else begin
+
 // Logic to take words out of the CDC and form packets
 always_comb begin
   if (SHIFT_DOWN) begin
@@ -127,6 +173,9 @@ always_ff @ (posedge i_clk_b) begin
   end
 end
 
+end
+endgenerate
+
 cdc_fifo #(
   .SIZE     ( 1<<FIFO_ABITS                              ),
   .DAT_BITS ( IN_DAT_BYTS*8 + IN_MOD_BITS + CTL_BITS + 3 ),