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zcash-fpga
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bug fixes for fpga c++

This commit is contained in:
ben devlin 2019-07-01 02:40:51 -04:00
parent 5ed7af923a
commit f06a82cf55
2 changed files with 90 additions and 88 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

153
aws/cl_zcash/software/runtime/zcash_fpga.cpp
View File

@ -7,18 +7,19 @@
#include <fpga_pci.h>
zcash_fpga::zcash_fpga() {
if (zfpga.init_fpga() != 0)
if (init_fpga() != 0)
printf("ERROR: Unable to initialize to FPGA!\n");
}
zcash_fpga::~zcash_fpga() {
int rc;
/* clean up */
if (m_pci_bar_handle_bar0 >= 0) {
rc = fpga_pci_detach(pci_bar_handle_bar0);
rc = fpga_pci_detach(m_pci_bar_handle_bar0);
if (rc) printf("ERROR: Failure while detaching bar0 from the fpga.\n");
}
if (m_pci_bar_handle_bar4 >= 0) {
rc = fpga_pci_detach(pci_bar_handle_bar4);
rc = fpga_pci_detach(m_pci_bar_handle_bar4);
if (rc) printf("ERROR: Failure while detaching bar4 from the fpga.\n");
}
}
@ -30,8 +31,8 @@ zcash_fpga& zcash_fpga::get_instance() {
int zcash_fpga::init_fpga(int slot_id) {
// Initialize the FPGA
if (initialized) {
printf("INFO: FPGA already initialized, skipping initialization\n");
if (m_initialized) {
printf("INFO: FPGA already m_initialized, skipping initialization\n");
return 0;
}
@ -46,60 +47,60 @@ int zcash_fpga::init_fpga(int slot_id) {
fail_on(rc, out, "ERROR: AFI not ready");
// We need to attach to the FPGA BAR0 (OCL) and BAR4 (PCIS)
rc = fpga_pci_attach(slot_id, FPGA_APP_PF, APP_PF_BAR0, 0, &pci_bar_handle_bar0);
rc = fpga_pci_attach(slot_id, FPGA_APP_PF, APP_PF_BAR0, 0, &m_pci_bar_handle_bar0);
fail_on(rc, out, "ERROR: Unable to attach to the AFI BAR0 on slot id %d", slot_id);
rc = fpga_pci_attach(slot_id, FPGA_APP_PF, APP_PF_BAR4, BURST_CAPABLE, &pci_bar_handle_bar4);
rc = fpga_pci_attach(slot_id, FPGA_APP_PF, APP_PF_BAR4, BURST_CAPABLE, &m_pci_bar_handle_bar4);
fail_on(rc, out, "ERROR: Unable to attach to the AFI BAR4 on slot id %d", slot_id);
// Now setup the streaming interface
rc = fpga_pci_peek(pci_bar_handle_bar0, AXI_FIFO_OFFSET, &rdata); //ISR
rc = fpga_pci_peek(m_pci_bar_handle_bar0, AXI_FIFO_OFFSET, &rdata); //ISR
fail_on(rc, out, "ERROR: Unable to read from FPGA!");
printf("INFO: Read 0x%x from ISR register.\n", rdata);
if (rdata != 0x01D00000) {
printf("WARNING: Expected 0x01D00000.\n");
}
rc = fpga_pci_poke(pci_bar_handle_bar0, AXI_FIFO_OFFSET, 0xFFFFFFFF); // Reset ISR
rc = fpga_pci_poke(m_pci_bar_handle_bar0, AXI_FIFO_OFFSET, 0xFFFFFFFF); // Reset ISR
fail_on(rc, out, "Unable to write to FPGA!");
rc = fpga_pci_peek(pci_bar_handle_bar0, AXI_FIFO_OFFSET+0xCULL, &rdata); //TDFV
rc = fpga_pci_peek(m_pci_bar_handle_bar0, AXI_FIFO_OFFSET+0xCULL, &rdata); //TDFV
fail_on(rc, out, "Unable to read from FPGA!");
printf("INFO: Read 0x%x from TDFV register.\n", rdata);
if (rdata != 0x000001FC) {
printf("WARNING: Expected 0x000001FC.\n");
}
rc = fpga_pci_peek(pci_bar_handle_bar0, AXI_FIFO_OFFSET+0x1CULL, &rdata); //RDFO
rc = fpga_pci_peek(m_pci_bar_handle_bar0, AXI_FIFO_OFFSET+0x1CULL, &rdata); //RDFO
fail_on(rc, out, "ERROR: Unable to read from FPGA!");
printf("INFO: Read 0x%x from RDFO register.\n", rdata);
if (rdata != 0x00000000) {
printf("WARNING: Expected 0x00000000.\n");
}
rc = fpga_pci_poke(pci_bar_handle_bar0, AXI_FIFO_OFFSET+0x4ULL, 0x0C000000); // Clear IER
rc = fpga_pci_poke(m_pci_bar_handle_bar0, AXI_FIFO_OFFSET+0x4ULL, 0x0C000000); // Clear IER
fail_on(rc, out, "ERROR: Unable to write to FPGA!");
// Check if we have AXI4 mode enabled or not
rc = fpga_pci_peek(pci_bar_handle_bar0, AXI_FIFO_OFFSET+0x44ULL, &rdata); //RDFO
rc = fpga_pci_peek(m_pci_bar_handle_bar0, AXI_FIFO_OFFSET+0x44ULL, &rdata); //RDFO
fail_on(rc, out, "ERROR: Unable to write to FPGA!");
AXI4_enabled = (1 << 31) & rdata;
if (AXI4_enabled)
m_axi4_enabled = (1 << 31) & rdata;
if (m_axi4_enabled)
printf("INFO: AXI4 mode is set ENABLED\n");
else
printf("INFO: AXI4 mode is set DISABLED\n");
initialized = true;
m_initialized = true;
// Send a Status message to FPGA to get configuration info
fpga_status_rpl_t fpga_status_rpl;
rc = get_status(fpga_status_rpl_t status_rpl);
fpga_status_rpl_t status_rpl;
rc = get_status(status_rpl);
fail_on(rc, out, "ERROR: Unable to get FPGA status!");
printf("INFO: FPGA version: 0x%x, built on 0x%xxl\n", status_rpl.version, status_rpl.build_date);
printf("INFO: FPGA capability register: 0x%lx [ENB_VERIFY_EQUIHASH_200_9: %d, ENB_VERIFY_EQUIHASH_144_5 %d, ENB_VERIFY_SECP256K1_SIG %d, ENB_BLS12_381 %d]\n",
printf("INFO: FPGA version: 0x%x, built on 0x%lx\n", status_rpl.version, status_rpl.build_date);
printf("INFO: FPGA capability register: 0x%lx [ENB_VERIFY_EQUIHASH_200_9: %lu, ENB_VERIFY_EQUIHASH_144_5 %lu, ENB_VERIFY_SECP256K1_SIG %lu, ENB_BLS12_381 %lu]\n",
status_rpl.cmd_cap,
status_rpl.cmd_cap & (1 << ENB_VERIFY_EQUIHASH_200_9),
status_rpl.cmd_cap & (1 << ENB_VERIFY_EQUIHASH_144_5),
@ -107,19 +108,19 @@ int zcash_fpga::init_fpga(int slot_id) {
status_rpl.cmd_cap & (1 << ENB_BLS12_381));
if (status_rpl.cmd_cap & (1 << ENB_BLS12_381)) {
rc = fpga_pci_peek(pci_bar_handle_bar0, BLS12_381_OFFSET + 0, &rdata);
rc = fpga_pci_peek(m_pci_bar_handle_bar0, BLS12_381_OFFSET + 0, &rdata);
fail_on(rc, out, "ERROR: Unable to read from FPGA!\n");
m_bls12_381_inst_axil_offset = rdata;
rc = fpga_pci_peek(pci_bar_handle_bar0, BLS12_381_OFFSET + 1*4, &rdata);
rc = fpga_pci_peek(m_pci_bar_handle_bar0, BLS12_381_OFFSET + 1*4, &rdata);
fail_on(rc, out, "ERROR: Unable to read from FPGA!\n");
m_bls12_381_data_axil_offset = rdata;
rc = fpga_pci_peek(pci_bar_handle_bar0, BLS12_381_OFFSET + 2*4, &rdata);
rc = fpga_pci_peek(m_pci_bar_handle_bar0, BLS12_381_OFFSET + 2*4, &rdata);
fail_on(rc, out, "ERROR: Unable to read from FPGA!\n");
m_bls12_381_data_size = 1 << rdata;
rc = fpga_pci_peek(pci_bar_handle_bar0, BLS12_381_OFFSET + 3*4, &rdata);
rc = fpga_pci_peek(m_pci_bar_handle_bar0, BLS12_381_OFFSET + 3*4, &rdata);
fail_on(rc, out, "ERROR: Unable to read from FPGA!\n");
m_bls12_381_inst_size = 1 << rdata;
}
@ -129,14 +130,14 @@ int zcash_fpga::init_fpga(int slot_id) {
return rc;
out:
initialized = false;
m_initialized = false;
/* clean up */
if (pci_bar_handle_bar0 >= 0) {
rc = fpga_pci_detach(pci_bar_handle_bar0);
if (m_pci_bar_handle_bar0 >= 0) {
rc = fpga_pci_detach(m_pci_bar_handle_bar0);
if (rc) printf("ERROR: Failure while detaching bar0 from the fpga.\n");
}
if (pci_bar_handle_bar4 >= 0) {
rc = fpga_pci_detach(pci_bar_handle_bar4);
if (m_pci_bar_handle_bar4 >= 0) {
rc = fpga_pci_detach(m_pci_bar_handle_bar4);
if (rc) printf("ERROR: Failure while detaching bar4 from the fpga.\n");
}
return 1;
@ -161,8 +162,8 @@ int zcash_fpga::check_afi_ready(int slot_id) {
info.spec.map[FPGA_APP_PF].device_id);
/* confirm that the AFI that we expect is in fact loaded */
if (info.spec.map[FPGA_APP_PF].vendor_id != pci_vendor_id ||
info.spec.map[FPGA_APP_PF].device_id != pci_device_id) {
if (info.spec.map[FPGA_APP_PF].vendor_id != s_pci_vendor_id ||
info.spec.map[FPGA_APP_PF].device_id != s_pci_device_id) {
printf("INFO: AFI does not show expected PCI vendor id and device ID. If the AFI "
"was just loaded, it might need a rescan. Rescanning now.\n");
@ -177,8 +178,8 @@ int zcash_fpga::check_afi_ready(int slot_id) {
info.spec.map[FPGA_APP_PF].device_id);
/* confirm that the AFI that we expect is in fact loaded after rescan */
if (info.spec.map[FPGA_APP_PF].vendor_id != pci_vendor_id ||
info.spec.map[FPGA_APP_PF].device_id != pci_device_id) {
if (info.spec.map[FPGA_APP_PF].vendor_id != s_pci_vendor_id ||
info.spec.map[FPGA_APP_PF].device_id != s_pci_device_id) {
rc = 1;
fail_on(rc, out, "ERROR: The PCI vendor id and device of the loaded AFI are not "
"the expected values.");
@ -196,8 +197,8 @@ int zcash_fpga::get_status(fpga_status_rpl_t& status_rpl) {
unsigned int timeout = 0;
unsigned int read_len = 0;
if (!initialized) {
printf("ERROR: FPGA not initialized!\n");
if (!m_initialized) {
printf("ERROR: FPGA not m_initialized!\n");
goto out;
}
@ -231,13 +232,13 @@ int zcash_fpga::write_stream(char* data, unsigned int len) {
uint32_t rdata;
unsigned int len_send = 0;
if (!initialized) {
printf("ERROR: FPGA not initialized!\n");
if (!m_initialized) {
printf("ERROR: FPGA not m_initialized!\n");
goto out;
}
rc = fpga_pci_peek(pci_bar_handle_bar0, AXI_FIFO_OFFSET + 0xCULL, &rdata);
rc = fpga_pci_peek(m_pci_bar_handle_bar0, AXI_FIFO_OFFSET + 0xCULL, &rdata);
fail_on(rc, out, "ERROR: Unable to read from FPGA!");
if (len > rdata) {
printf("ERROR: write_stream does not have enough space to write %d bytes! (%d free)\n", len, rdata);
@ -246,30 +247,30 @@ int zcash_fpga::write_stream(char* data, unsigned int len) {
while(len_send < len) {
if (AXI4_enabled) {
fpga_pci_poke64(pci_bar_handle_bar4, 0, *(uint64_t*)(&data[len_send]));
if (m_axi4_enabled) {
fpga_pci_poke64(m_pci_bar_handle_bar4, 0, *(uint64_t*)(&data[len_send]));
len_send += 8;
} else {
rc = fpga_pci_poke(pci_bar_handle_bar0, AXI_FIFO_OFFSET+0x10ULL, *(uint32_t*)(&data[len_send])); // Reset ISR
rc = fpga_pci_poke(m_pci_bar_handle_bar0, AXI_FIFO_OFFSET+0x10ULL, *(uint32_t*)(&data[len_send])); // Reset ISR
fail_on(rc, out, "ERROR: Unable to write to FPGA!");
len_send += 4;
}
}
rc = fpga_pci_poke(pci_bar_handle_bar0, AXI_FIFO_OFFSET+0x14ULL, len); // Reset ISR
rc = fpga_pci_poke(m_pci_bar_handle_bar0, AXI_FIFO_OFFSET+0x14ULL, len); // Reset ISR
fail_on(rc, out, "ERROR: Unable to write to FPGA!");
printf("INFO: write_stream::Wrote %d bytes of data\n", len);
// Check transmit complete bit and reset it
rc = fpga_pci_peek(pci_bar_handle_bar0, AXI_FIFO_OFFSET, &rdata);
rc = fpga_pci_peek(m_pci_bar_handle_bar0, AXI_FIFO_OFFSET, &rdata);
fail_on(rc, out, "ERROR: Unable to read from FPGA!");
if ((rdata & (1 << 27)) == 0) {
printf("WARNING: write_stream transmit bit not set, register returned 0x%x\n", rdata);
}
rc = fpga_pci_poke(pci_bar_handle_bar0, AXI_FIFO_OFFSET, 0x08000000); // Reset ISR
rc = fpga_pci_poke(m_pci_bar_handle_bar0, AXI_FIFO_OFFSET, 0x08000000); // Reset ISR
fail_on(rc, out, "Unable to write to FPGA!");
return rc;
@ -283,27 +284,27 @@ int zcash_fpga::read_stream(char* data, unsigned int size) {
unsigned int read_len = 0;
int rc;
if (!initialized) {
printf("ERROR: FPGA not initialized!\n");
if (!m_initialized) {
printf("ERROR: FPGA not m_initialized!\n");
goto out;
}
rc = fpga_pci_peek(pci_bar_handle_bar0, AXI_FIFO_OFFSET, &rdata);
rc = fpga_pci_peek(m_pci_bar_handle_bar0, AXI_FIFO_OFFSET, &rdata);
fail_on(rc, out, "ERROR: Unable to read from FPGA!");
if ((rdata & (1 << 26)) == 0) return 0; // Nothing to read
rc = fpga_pci_poke(pci_bar_handle_bar0, AXI_FIFO_OFFSET, 0x04000000); // clear ISR
rc = fpga_pci_poke(m_pci_bar_handle_bar0, AXI_FIFO_OFFSET, 0x04000000); // clear ISR
fail_on(rc, out, "ERROR: Unable to write to FPGA!");
rc = fpga_pci_peek(pci_bar_handle_bar0, AXI_FIFO_OFFSET + 0x1CULL, &rdata); //RDFO should be non-zero (slots used in FIFO)
rc = fpga_pci_peek(m_pci_bar_handle_bar0, AXI_FIFO_OFFSET + 0x1CULL, &rdata); //RDFO should be non-zero (slots used in FIFO)
fail_on(rc, out, "ERROR: Unable to read from FPGA!");
if (rdata == 0) {
printf("WARNING: Read FIFO shows data but length was 0!\n");
return 0;
}
rc = fpga_pci_peek(pci_bar_handle_bar0, AXI_FIFO_OFFSET + 0x24ULL, &rdata); //RLR - length of packet in bytes
rc = fpga_pci_peek(m_pci_bar_handle_bar0, AXI_FIFO_OFFSET + 0x24ULL, &rdata); //RLR - length of packet in bytes
fail_on(rc, out, "Unable to read from FPGA!");
printf("INFO: Read FIFO shows %d waiting to be read from FPGA\n", rdata);
@ -313,12 +314,12 @@ int zcash_fpga::read_stream(char* data, unsigned int size) {
}
while(read_len < rdata) {
if (AXI4_enabled) {
rc = fpga_pci_peek(pci_bar_handle_bar4, 0x1000, (uint32_t*)(&data[read_len]));
if (m_axi4_enabled) {
rc = fpga_pci_peek(m_pci_bar_handle_bar4, 0x1000, (uint32_t*)(&data[read_len]));
fail_on(rc, out, "ERROR: Unable to read from FPGA PCIS!");
read_len += 8;
} else {
rc = fpga_pci_peek(pci_bar_handle_bar0, AXI_FIFO_OFFSET + 0x20ULL, (uint32_t*)(&data[read_len]));
rc = fpga_pci_peek(m_pci_bar_handle_bar0, AXI_FIFO_OFFSET + 0x20ULL, (uint32_t*)(&data[read_len]));
fail_on(rc, out, "ERROR: Unable to read from FPGA!");
read_len += 4;
}
@ -334,8 +335,8 @@ int zcash_fpga::read_stream(char* data, unsigned int size) {
int zcash_fpga::bls12_381_write_data_slot(unsigned int id, bls12_381_slot_t slot_data) {
char data[48];
int rc = 0;
if (!initialized) {
printf("ERROR: FPGA not initialized!\n");
if (!m_initialized) {
printf("ERROR: FPGA not m_initialized!\n");
goto out;
}
if (id >= m_bls12_381_data_size) {
@ -349,7 +350,7 @@ int zcash_fpga::bls12_381_write_data_slot(unsigned int id, bls12_381_slot_t slot
data[47] |= (slot_data.point_type << 5);
for(int i = 0; i < 48/4; i=i+4) {
rc = fpga_pci_poke(pci_bar_handle_bar0, BLS12_381_OFFSET + m_bls12_381_data_axil_offset + id*64 + i, *((uint32_t*)&data[i]));
rc = fpga_pci_poke(m_pci_bar_handle_bar0, BLS12_381_OFFSET + m_bls12_381_data_axil_offset + id*64 + i, *((uint32_t*)&data[i]));
fail_on(rc, out, "ERROR: Unable to write to FPGA!\n");
}
return 0;
@ -359,8 +360,8 @@ int zcash_fpga::bls12_381_write_data_slot(unsigned int id, bls12_381_slot_t slot
int zcash_fpga::bls12_381_read_data_slot(unsigned int id, bls12_381_slot_t& slot_data) {
int rc = 0;
if (!initialized) {
printf("ERROR: FPGA not initialized!\n");
if (!m_initialized) {
printf("ERROR: FPGA not m_initialized!\n");
goto out;
}
if (id >= m_bls12_381_data_size) {
@ -369,7 +370,7 @@ int zcash_fpga::bls12_381_read_data_slot(unsigned int id, bls12_381_slot_t& slot
}
for(int i = 0; i < 48/4; i=i+4) {
rc = fpga_pci_peek(pci_bar_handle_bar0, BLS12_381_OFFSET + m_bls12_381_data_axil_offset + id*64 + i, (uint32_t*)(&slot_data));
rc = fpga_pci_peek(m_pci_bar_handle_bar0, BLS12_381_OFFSET + m_bls12_381_data_axil_offset + id*64 + i, (uint32_t*)(&slot_data));
fail_on(rc, out, "ERROR: Unable to read from FPGA!\n");
}
@ -384,8 +385,8 @@ int zcash_fpga::bls12_381_read_data_slot(unsigned int id, bls12_381_slot_t& slot
int zcash_fpga::bls12_381_write_inst_slot(unsigned int id, bls12_381_inst_t inst_data) {
int rc = 0;
if (!initialized) {
printf("ERROR: FPGA not initialized!\n");
if (!m_initialized) {
printf("ERROR: FPGA not m_initialized!\n");
goto out;
}
if (id >= m_bls12_381_inst_size) {
@ -394,7 +395,7 @@ int zcash_fpga::bls12_381_write_inst_slot(unsigned int id, bls12_381_inst_t inst
}
for(int i = 0; i < 2; i=i+1) {
rc = fpga_pci_poke(pci_bar_handle_bar0, BLS12_381_OFFSET + m_bls12_381_inst_axil_offset + id*8 + i*4, *((uint32_t*)&inst_data) + i);
rc = fpga_pci_poke(m_pci_bar_handle_bar0, BLS12_381_OFFSET + m_bls12_381_inst_axil_offset + id*8 + i*4, *((uint32_t*)&inst_data) + i);
fail_on(rc, out, "ERROR: Unable to write to FPGA!\n");
}
return 0;
@ -404,8 +405,8 @@ int zcash_fpga::bls12_381_write_inst_slot(unsigned int id, bls12_381_inst_t inst
int zcash_fpga::bls12_381_read_inst_slot(unsigned int id, bls12_381_inst_t& inst_data) {
int rc = 0;
if (!initialized) {
printf("ERROR: FPGA not initialized!\n");
if (!m_initialized) {
printf("ERROR: FPGA not m_initialized!\n");
goto out;
}
if (id >= m_bls12_381_inst_size) {
@ -414,7 +415,7 @@ int zcash_fpga::bls12_381_read_inst_slot(unsigned int id, bls12_381_inst_t& inst
}
for(int i = 0; i < 2; i=i+1) {
rc = fpga_pci_peek(pci_bar_handle_bar0, BLS12_381_OFFSET + m_bls12_381_inst_axil_offset + id*8 + i*4, ((uint32_t*)(&inst_data) + i));
rc = fpga_pci_peek(m_pci_bar_handle_bar0, BLS12_381_OFFSET + m_bls12_381_inst_axil_offset + id*8 + i*4, ((uint32_t*)(&inst_data) + i));
fail_on(rc, out, "ERROR: Unable to read from FPGA!\n");
}
@ -427,8 +428,8 @@ int zcash_fpga::bls12_381_set_curr_inst_slot(unsigned int id) {
int rc = 0;
unsigned int prev_id;
uint32_t rdata;
if (!initialized) {
printf("ERROR: FPGA not initialized!\n");
if (!m_initialized) {
printf("ERROR: FPGA not m_initialized!\n");
goto out;
}
if (id >= m_bls12_381_inst_size) {
@ -436,14 +437,14 @@ int zcash_fpga::bls12_381_set_curr_inst_slot(unsigned int id) {
goto out;
}
rc = fpga_pci_peek(pci_bar_handle_bar0, BLS12_381_OFFSET + 0x10, rdata);
rc = fpga_pci_peek(m_pci_bar_handle_bar0, BLS12_381_OFFSET + 0x10, &rdata);
fail_on(rc, out, "ERROR: Unable to read from FPGA!\n");
prev_id = rdata;
rc = fpga_pci_poke(pci_bar_handle_bar0, BLS12_381_OFFSET + 0x10, id);
rc = fpga_pci_poke(m_pci_bar_handle_bar0, BLS12_381_OFFSET + 0x10, id);
fail_on(rc, out, "ERROR: Unable to write to FPGA!\n");
rc = fpga_pci_peek(pci_bar_handle_bar0, BLS12_381_OFFSET + 0x10, rdata);
rc = fpga_pci_peek(m_pci_bar_handle_bar0, BLS12_381_OFFSET + 0x10, &rdata);
fail_on(rc, out, "ERROR: Unable to read from FPGA!\n");
if (rdata != id) {
@ -461,8 +462,8 @@ int zcash_fpga::bls12_381_set_curr_inst_slot(unsigned int id) {
int zcash_fpga::bls12_381_get_curr_inst_slot(unsigned int& id) {
int rc = 0;
if (!initialized) {
printf("ERROR: FPGA not initialized!\n");
if (!m_initialized) {
printf("ERROR: FPGA not m_initialized!\n");
goto out;
}
if (id >= m_bls12_381_inst_size) {
@ -470,7 +471,7 @@ int zcash_fpga::bls12_381_get_curr_inst_slot(unsigned int& id) {
goto out;
}
rc = fpga_pci_peek(pci_bar_handle_bar0, BLS12_381_OFFSET + 0x10, id);
rc = fpga_pci_peek(m_pci_bar_handle_bar0, BLS12_381_OFFSET + 0x10, &id);
fail_on(rc, out, "ERROR: Unable to read from FPGA!\n");
printf("INFO: BLS12_381 current instruction slot is %d\n", id);
@ -483,8 +484,8 @@ int zcash_fpga::bls12_381_get_curr_inst_slot(unsigned int& id) {
int zcash_fpga::bls12_381_reset_memory(bool inst_memory, bool data_memory) {
int rc = 0;
uint32_t data = 0;
if (!initialized) {
printf("ERROR: FPGA not initialized!\n");
if (!m_initialized) {
printf("ERROR: FPGA not m_initialized!\n");
goto out;
}
@ -498,7 +499,7 @@ int zcash_fpga::bls12_381_reset_memory(bool inst_memory, bool data_memory) {
printf("INFO: Resetting data memory reset\n");
}
rc = fpga_pci_poke(pci_bar_handle_bar0, BLS12_381_OFFSET, ;
rc = fpga_pci_poke(m_pci_bar_handle_bar0, BLS12_381_OFFSET, data);
fail_on(rc, out, "ERROR: Unable to write to FPGA!\n");
return 0;

25
aws/cl_zcash/software/runtime/zcash_fpga.hpp
View File

@ -27,6 +27,7 @@
#include <utils/lcd.h>
#include <utils/sh_dpi_tasks.h>
#define AXI_FIFO_OFFSET UINT64_C(0x0)
#define BLS12_381_OFFSET UINT64_C(0x1000)
@ -35,14 +36,14 @@ class zcash_fpga {
public:
enum uint64_t {
typedef enum : uint64_t {
ENB_BLS12_381 = 1 << 3,
ENB_VERIFY_SECP256K1_SIG = 1 << 2,
ENB_VERIFY_EQUIHASH_144_5 = 1 << 1,
ENB_VERIFY_EQUIHASH_200_9 = 1 << 0
} command_cap_e;
typedef enum uin32_t {
typedef enum : uint32_t {
RESET_FPGA = 0x00000000,
FPGA_STATUS = 0x00000001,
VERIFY_EQUIHASH = 0x00000100,
@ -57,7 +58,7 @@ class zcash_fpga {
BLS12_381_INTERRUPT_RPL = 0x80000200
} command_t;
typedef enum uint8_t {
typedef enum : uint8_t {
SCALAR = 0,
FE = 1,
FE2 = 2,
@ -74,7 +75,7 @@ class zcash_fpga {
point_type_t point_type;
} bls12_381_slot_t;
typedef enum uint8_t {
typedef enum : uint8_t {
NOOP_WAIT = 0x0,
COPY_REG = 0x1,
SEND_INTERRUPT = 0x6,
@ -87,15 +88,15 @@ class zcash_fpga {
POINT_MULT = 0x24,
FP_FPOINT_MULT = 0x25,
FP2_FPOINT_MULT = 0x26
} code_t;
} bls12_381_code_t;
// Instruction format
typedef struct __attribute__((__packed__)) {
code_t code;
uint16_t a;
uint16_t b;
uint16_t c;
} inst_t;
bls12_381_code_t code;
uint16_t a;
uint16_t b;
uint16_t c;
} bls12_381_inst_t;
typedef struct __attribute__((__packed__)) {
uint32_t len;
@ -141,7 +142,7 @@ class zcash_fpga {
unsigned int m_bls12_381_inst_size;
unsigned int m_bls12_381_data_size;
bool m_AXI4_enabled = false;
bool m_axi4_enabled = false;
bool m_initialized = false;
public:
@ -167,7 +168,7 @@ class zcash_fpga {
int bls12_381_read_data_slot(unsigned int id, bls12_381_slot_t& slot_data);
int bls12_381_write_inst_slot(unsigned int id, bls12_381_inst_t inst_data);
int bls12_381_read_inst_slot(unsigned int id, bls12_381_inst_t inst_data);
int bls12_381_read_inst_slot(unsigned int id, bls12_381_inst_t& inst_data);
int bls12_381_set_curr_inst_slot(unsigned int id);
int bls12_381_get_curr_inst_slot(unsigned int& id);