From f4a2eb2fe3146678c46c1a0aa8441d86edd12990 Mon Sep 17 00:00:00 2001 From: bsdevlin Date: Wed, 10 Apr 2019 12:15:04 -0400 Subject: [PATCH 1/2] Update constraints to move debug to seperate file --- bittware_xupvvh/synth/bittware_xupvvh_top.xdc | 158 +----------------- bittware_xupvvh/synth/debug.xdc | 153 +++++++++++++++++ 2 files changed, 155 insertions(+), 156 deletions(-) create mode 100644 bittware_xupvvh/synth/debug.xdc diff --git a/bittware_xupvvh/synth/bittware_xupvvh_top.xdc b/bittware_xupvvh/synth/bittware_xupvvh_top.xdc index 46432e5..3acbfef 100644 --- a/bittware_xupvvh/synth/bittware_xupvvh_top.xdc +++ b/bittware_xupvvh/synth/bittware_xupvvh_top.xdc @@ -28,146 +28,8 @@ set_property PACKAGE_PIN G21 [get_ports usb_uart_txd] set_property PACKAGE_PIN F21 [get_ports usb_uart_rxd] -#Debug -connect_debug_port u_ila_0/probe6 [get_nets [list interrupt_r]] -connect_debug_port u_ila_0/probe7 [get_nets [list tx]] -connect_debug_port u_ila_0/probe8 [get_nets [list tx2]] -connect_debug_port u_ila_0/probe15 [get_nets [list usb_uart_txd_IBUF]] -connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_pll/inst/clk_out300]] -connect_debug_port u_ila_0/probe2 [get_nets [list {check_rst[0]} {check_rst[1]} {check_rst[2]} {check_rst[3]} {check_rst[4]} {check_rst[5]} {check_rst[6]} {check_rst[7]}]] -connect_debug_port u_ila_0/probe5 [get_nets [list {clk_out300_rst_r[0]} {clk_out300_rst_r[1]} {clk_out300_rst_r[2]}]] -connect_debug_port u_ila_1/clk [get_nets [list clk_wiz_pll/inst/clk_out100]] -connect_debug_port u_ila_1/probe0 [get_nets [list {clk_out100_rst_r[0]} {clk_out100_rst_r[1]} {clk_out100_rst_r[2]}]] -connect_debug_port dbg_hub/clk [get_nets clk_out100] - - - -connect_debug_port u_ila_0/probe1 [get_nets [list {uart_state[0]} {uart_state[1]} {uart_state[2]} {uart_state[3]} {uart_state[4]} {uart_state[5]} {uart_state[6]} {uart_state[7]} {uart_state[8]} {uart_state[9]} {uart_state[10]} {uart_state[11]} {uart_state[12]} {uart_state[13]} {uart_state[14]} {uart_state[15]} {uart_state[16]} {uart_state[17]} {uart_state[18]} {uart_state[19]} {uart_state[20]} {uart_state[21]} {uart_state[22]} {uart_state[23]} {uart_state[24]} {uart_state[25]} {uart_state[26]} {uart_state[27]} {uart_state[28]} {uart_state[29]} {uart_state[30]} {uart_state[31]}]] -connect_debug_port u_ila_0/probe2 [get_nets [list {uart_axi_awaddr[0]} {uart_axi_awaddr[1]} {uart_axi_awaddr[2]} {uart_axi_awaddr[3]}]] -connect_debug_port u_ila_0/probe3 [get_nets [list {uart_axi_rdata[0]} {uart_axi_rdata[1]} {uart_axi_rdata[2]} {uart_axi_rdata[3]} {uart_axi_rdata[4]} {uart_axi_rdata[5]} {uart_axi_rdata[6]} {uart_axi_rdata[7]} {uart_axi_rdata[8]} {uart_axi_rdata[9]} {uart_axi_rdata[10]} {uart_axi_rdata[11]} {uart_axi_rdata[12]} {uart_axi_rdata[13]} {uart_axi_rdata[14]} {uart_axi_rdata[15]} {uart_axi_rdata[16]} {uart_axi_rdata[17]} {uart_axi_rdata[18]} {uart_axi_rdata[19]} {uart_axi_rdata[20]} {uart_axi_rdata[21]} {uart_axi_rdata[22]} {uart_axi_rdata[23]} {uart_axi_rdata[24]} {uart_axi_rdata[25]} {uart_axi_rdata[26]} {uart_axi_rdata[27]} {uart_axi_rdata[28]} {uart_axi_rdata[29]} {uart_axi_rdata[30]} {uart_axi_rdata[31]}]] -connect_debug_port u_ila_0/probe4 [get_nets [list {uart_axi_rresp[0]} {uart_axi_rresp[1]}]] -connect_debug_port u_ila_0/probe5 [get_nets [list {uart_axi_araddr[0]} {uart_axi_araddr[1]} {uart_axi_araddr[2]} {uart_axi_araddr[3]}]] -connect_debug_port u_ila_0/probe6 [get_nets [list {uart_axi_wdata[0]} {uart_axi_wdata[1]} {uart_axi_wdata[2]} {uart_axi_wdata[3]} {uart_axi_wdata[4]} {uart_axi_wdata[5]} {uart_axi_wdata[6]} {uart_axi_wdata[7]} {uart_axi_wdata[8]} {uart_axi_wdata[9]} {uart_axi_wdata[10]} {uart_axi_wdata[11]} {uart_axi_wdata[12]} {uart_axi_wdata[13]} {uart_axi_wdata[14]} {uart_axi_wdata[15]} {uart_axi_wdata[16]} {uart_axi_wdata[17]} {uart_axi_wdata[18]} {uart_axi_wdata[19]} {uart_axi_wdata[20]} {uart_axi_wdata[21]} {uart_axi_wdata[22]} {uart_axi_wdata[23]} {uart_axi_wdata[24]} {uart_axi_wdata[25]} {uart_axi_wdata[26]} {uart_axi_wdata[27]} {uart_axi_wdata[28]} {uart_axi_wdata[29]} {uart_axi_wdata[30]} {uart_axi_wdata[31]}]] -connect_debug_port u_ila_0/probe7 [get_nets [list eop_l]] -connect_debug_port u_ila_0/probe9 [get_nets [list interrupt]] -connect_debug_port u_ila_0/probe10 [get_nets [list sop_l]] -connect_debug_port u_ila_0/probe11 [get_nets [list uart_axi_arready]] -connect_debug_port u_ila_0/probe12 [get_nets [list uart_axi_arvalid]] -connect_debug_port u_ila_0/probe13 [get_nets [list uart_axi_awready]] -connect_debug_port u_ila_0/probe14 [get_nets [list uart_axi_awvalid]] -connect_debug_port u_ila_0/probe15 [get_nets [list uart_axi_rvalid]] -connect_debug_port u_ila_0/probe16 [get_nets [list uart_axi_wready]] - -connect_debug_port u_ila_1/probe5 [get_nets [list {uart_wrapper/uart_axi_wdata_0[0]} {uart_wrapper/uart_axi_wdata_0[1]} {uart_wrapper/uart_axi_wdata_0[2]} {uart_wrapper/uart_axi_wdata_0[3]} {uart_wrapper/uart_axi_wdata_0[4]} {uart_wrapper/uart_axi_wdata_0[5]} {uart_wrapper/uart_axi_wdata_0[6]} {uart_wrapper/uart_axi_wdata_0[7]} {uart_wrapper/uart_axi_wdata_0[8]} {uart_wrapper/uart_axi_wdata_0[9]} {uart_wrapper/uart_axi_wdata_0[10]} {uart_wrapper/uart_axi_wdata_0[11]} {uart_wrapper/uart_axi_wdata_0[12]} {uart_wrapper/uart_axi_wdata_0[13]} {uart_wrapper/uart_axi_wdata_0[14]} {uart_wrapper/uart_axi_wdata_0[15]} {uart_wrapper/uart_axi_wdata_0[16]} {uart_wrapper/uart_axi_wdata_0[17]} {uart_wrapper/uart_axi_wdata_0[18]} {uart_wrapper/uart_axi_wdata_0[19]} {uart_wrapper/uart_axi_wdata_0[20]} {uart_wrapper/uart_axi_wdata_0[21]} {uart_wrapper/uart_axi_wdata_0[22]} {uart_wrapper/uart_axi_wdata_0[23]} {uart_wrapper/uart_axi_wdata_0[24]} {uart_wrapper/uart_axi_wdata_0[25]} {uart_wrapper/uart_axi_wdata_0[26]} {uart_wrapper/uart_axi_wdata_0[27]} {uart_wrapper/uart_axi_wdata_0[28]} {uart_wrapper/uart_axi_wdata_0[29]} {uart_wrapper/uart_axi_wdata_0[30]} {uart_wrapper/uart_axi_wdata_0[31]}]] - -connect_debug_port u_ila_0/probe0 [get_nets [list {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[0]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[1]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[2]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[3]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[4]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[5]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[6]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[7]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[8]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[9]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[10]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[11]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[12]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[13]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[14]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[15]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[16]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[17]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[18]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[19]}]] -connect_debug_port u_ila_0/probe9 [get_nets [list zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_val_a]] -connect_debug_port u_ila_0/probe11 [get_nets [list zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/o_rdy_a]] -connect_debug_port u_ila_0/probe12 [get_nets [list zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/o_val_b]] -connect_debug_port u_ila_1/probe1 [get_nets [list {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[0]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[1]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[2]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[3]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[4]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[5]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[6]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[7]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[8]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[9]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[10]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[11]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[12]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[13]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[14]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[15]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[16]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[17]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[18]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[19]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[20]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[21]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[22]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[23]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[24]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[25]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[26]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[27]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[28]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[29]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[30]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[31]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[32]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[33]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[34]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[35]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[36]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[37]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[38]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[39]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[40]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[41]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[42]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[43]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[44]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[45]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[46]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[47]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[48]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[49]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[50]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[51]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[52]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[53]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[54]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[55]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[56]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[57]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[58]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[59]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[60]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[61]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[62]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[63]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[64]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[65]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[66]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[67]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[68]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[69]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[70]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[71]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[72]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[73]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[74]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[75]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[76]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[77]}]] -connect_debug_port u_ila_1/probe2 [get_nets [list zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_val_a]] -connect_debug_port u_ila_1/probe3 [get_nets [list zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/o_rdy_a]] -connect_debug_port u_ila_1/probe4 [get_nets [list zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/o_val_b]] - -connect_debug_port u_ila_0/probe8 [get_nets [list {zcash_fpga_top/control_top/debug_if/mod[0]} {zcash_fpga_top/control_top/debug_if/mod[-1]}]] - - -connect_debug_port u_ila_0/probe5 [get_nets [list zcash_fpga_top/control_top/debug_if2/mod]] - -connect_debug_port u_ila_0/probe2 [get_nets [list {uart_wrapper/uart_axi_wdata_0[0]} {uart_wrapper/uart_axi_wdata_0[1]} {uart_wrapper/uart_axi_wdata_0[2]} {uart_wrapper/uart_axi_wdata_0[3]} {uart_wrapper/uart_axi_wdata_0[4]} {uart_wrapper/uart_axi_wdata_0[5]} {uart_wrapper/uart_axi_wdata_0[6]} {uart_wrapper/uart_axi_wdata_0[7]} {uart_wrapper/uart_axi_wdata_0[8]} {uart_wrapper/uart_axi_wdata_0[9]} {uart_wrapper/uart_axi_wdata_0[10]} {uart_wrapper/uart_axi_wdata_0[11]} {uart_wrapper/uart_axi_wdata_0[12]} {uart_wrapper/uart_axi_wdata_0[13]} {uart_wrapper/uart_axi_wdata_0[14]} {uart_wrapper/uart_axi_wdata_0[15]} {uart_wrapper/uart_axi_wdata_0[16]} {uart_wrapper/uart_axi_wdata_0[17]} {uart_wrapper/uart_axi_wdata_0[18]} {uart_wrapper/uart_axi_wdata_0[19]} {uart_wrapper/uart_axi_wdata_0[20]} {uart_wrapper/uart_axi_wdata_0[21]} {uart_wrapper/uart_axi_wdata_0[22]} {uart_wrapper/uart_axi_wdata_0[23]} {uart_wrapper/uart_axi_wdata_0[24]} {uart_wrapper/uart_axi_wdata_0[25]} {uart_wrapper/uart_axi_wdata_0[26]} {uart_wrapper/uart_axi_wdata_0[27]} {uart_wrapper/uart_axi_wdata_0[28]} {uart_wrapper/uart_axi_wdata_0[29]} {uart_wrapper/uart_axi_wdata_0[30]} {uart_wrapper/uart_axi_wdata_0[31]}]] -connect_debug_port u_ila_0/probe8 [get_nets [list {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/o_dat_b[0]}]] -connect_debug_port u_ila_0/probe11 [get_nets [list uart_wrapper/eop_l]] -connect_debug_port u_ila_0/probe17 [get_nets [list uart_wrapper/sop_l]] -connect_debug_port u_ila_1/probe4 [get_nets [list {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/o_dat_b[0]}]] - - - -connect_debug_port u_ila_0/probe2 [get_nets [list {uart_wrapper/debug_if/dat[0]} {uart_wrapper/debug_if/dat[1]} {uart_wrapper/debug_if/dat[2]} {uart_wrapper/debug_if/dat[3]} {uart_wrapper/debug_if/dat[4]} {uart_wrapper/debug_if/dat[5]} {uart_wrapper/debug_if/dat[6]} {uart_wrapper/debug_if/dat[7]}]] -connect_debug_port u_ila_0/probe13 [get_nets [list uart_wrapper/debug_if/ctl]] -connect_debug_port u_ila_0/probe15 [get_nets [list uart_wrapper/debug_if/eop]] -connect_debug_port u_ila_0/probe16 [get_nets [list uart_wrapper/debug_if/err]] -connect_debug_port u_ila_0/probe19 [get_nets [list uart_wrapper/debug_if/mod]] -connect_debug_port u_ila_0/probe21 [get_nets [list uart_wrapper/debug_if/rdy]] -connect_debug_port u_ila_0/probe23 [get_nets [list uart_wrapper/debug_if/sop]] -connect_debug_port u_ila_0/probe31 [get_nets [list uart_wrapper/debug_if/val]] - - -connect_debug_port u_ila_0/probe11 [get_nets [list {zcash_fpga_top/control_top/debug_if/dat[0]} {zcash_fpga_top/control_top/debug_if/dat[1]} {zcash_fpga_top/control_top/debug_if/dat[2]} {zcash_fpga_top/control_top/debug_if/dat[3]} {zcash_fpga_top/control_top/debug_if/dat[4]} {zcash_fpga_top/control_top/debug_if/dat[5]} {zcash_fpga_top/control_top/debug_if/dat[6]} {zcash_fpga_top/control_top/debug_if/dat[7]}]] -connect_debug_port u_ila_0/probe13 [get_nets [list zcash_fpga_top/control_top/debug_if/ctl]] -connect_debug_port u_ila_0/probe14 [get_nets [list zcash_fpga_top/control_top/debug_if/eop]] -connect_debug_port u_ila_0/probe17 [get_nets [list zcash_fpga_top/control_top/debug_if/err]] -connect_debug_port u_ila_0/probe20 [get_nets [list zcash_fpga_top/control_top/debug_if/mod]] -connect_debug_port u_ila_0/probe22 [get_nets [list zcash_fpga_top/control_top/debug_if/rdy]] -connect_debug_port u_ila_0/probe23 [get_nets [list zcash_fpga_top/control_top/debug_if/sop]] -connect_debug_port u_ila_0/probe32 [get_nets [list zcash_fpga_top/control_top/debug_if/val]] -connect_debug_port u_ila_1/probe0 [get_nets [list {zcash_fpga_top/control_top/debug_if2/mod[0]} {zcash_fpga_top/control_top/debug_if2/mod[1]} {zcash_fpga_top/control_top/debug_if2/mod[2]}]] -connect_debug_port u_ila_1/probe1 [get_nets [list {zcash_fpga_top/control_top/debug_if2/dat[0]} {zcash_fpga_top/control_top/debug_if2/dat[1]} {zcash_fpga_top/control_top/debug_if2/dat[2]} {zcash_fpga_top/control_top/debug_if2/dat[3]} {zcash_fpga_top/control_top/debug_if2/dat[4]} {zcash_fpga_top/control_top/debug_if2/dat[5]} {zcash_fpga_top/control_top/debug_if2/dat[6]} {zcash_fpga_top/control_top/debug_if2/dat[7]} {zcash_fpga_top/control_top/debug_if2/dat[8]} {zcash_fpga_top/control_top/debug_if2/dat[9]} {zcash_fpga_top/control_top/debug_if2/dat[10]} {zcash_fpga_top/control_top/debug_if2/dat[11]} {zcash_fpga_top/control_top/debug_if2/dat[12]} {zcash_fpga_top/control_top/debug_if2/dat[13]} {zcash_fpga_top/control_top/debug_if2/dat[14]} {zcash_fpga_top/control_top/debug_if2/dat[15]} {zcash_fpga_top/control_top/debug_if2/dat[16]} {zcash_fpga_top/control_top/debug_if2/dat[17]} {zcash_fpga_top/control_top/debug_if2/dat[18]} {zcash_fpga_top/control_top/debug_if2/dat[19]} {zcash_fpga_top/control_top/debug_if2/dat[20]} {zcash_fpga_top/control_top/debug_if2/dat[21]} {zcash_fpga_top/control_top/debug_if2/dat[22]} {zcash_fpga_top/control_top/debug_if2/dat[23]} {zcash_fpga_top/control_top/debug_if2/dat[24]} {zcash_fpga_top/control_top/debug_if2/dat[25]} {zcash_fpga_top/control_top/debug_if2/dat[26]} {zcash_fpga_top/control_top/debug_if2/dat[27]} {zcash_fpga_top/control_top/debug_if2/dat[28]} {zcash_fpga_top/control_top/debug_if2/dat[29]} {zcash_fpga_top/control_top/debug_if2/dat[30]} {zcash_fpga_top/control_top/debug_if2/dat[31]} {zcash_fpga_top/control_top/debug_if2/dat[32]} {zcash_fpga_top/control_top/debug_if2/dat[33]} {zcash_fpga_top/control_top/debug_if2/dat[34]} {zcash_fpga_top/control_top/debug_if2/dat[35]} {zcash_fpga_top/control_top/debug_if2/dat[36]} {zcash_fpga_top/control_top/debug_if2/dat[37]} {zcash_fpga_top/control_top/debug_if2/dat[38]} {zcash_fpga_top/control_top/debug_if2/dat[39]} {zcash_fpga_top/control_top/debug_if2/dat[40]} {zcash_fpga_top/control_top/debug_if2/dat[41]} {zcash_fpga_top/control_top/debug_if2/dat[42]} {zcash_fpga_top/control_top/debug_if2/dat[43]} {zcash_fpga_top/control_top/debug_if2/dat[44]} {zcash_fpga_top/control_top/debug_if2/dat[45]} {zcash_fpga_top/control_top/debug_if2/dat[46]} {zcash_fpga_top/control_top/debug_if2/dat[47]} {zcash_fpga_top/control_top/debug_if2/dat[48]} {zcash_fpga_top/control_top/debug_if2/dat[49]} {zcash_fpga_top/control_top/debug_if2/dat[50]} {zcash_fpga_top/control_top/debug_if2/dat[51]} {zcash_fpga_top/control_top/debug_if2/dat[52]} {zcash_fpga_top/control_top/debug_if2/dat[53]} {zcash_fpga_top/control_top/debug_if2/dat[54]} {zcash_fpga_top/control_top/debug_if2/dat[55]} {zcash_fpga_top/control_top/debug_if2/dat[56]} {zcash_fpga_top/control_top/debug_if2/dat[57]} {zcash_fpga_top/control_top/debug_if2/dat[58]} {zcash_fpga_top/control_top/debug_if2/dat[59]} {zcash_fpga_top/control_top/debug_if2/dat[60]} {zcash_fpga_top/control_top/debug_if2/dat[61]} {zcash_fpga_top/control_top/debug_if2/dat[62]} {zcash_fpga_top/control_top/debug_if2/dat[63]}]] -connect_debug_port u_ila_1/probe2 [get_nets [list {zcash_fpga_top/control_top/debug_if3/dat[0]} {zcash_fpga_top/control_top/debug_if3/dat[1]} {zcash_fpga_top/control_top/debug_if3/dat[2]} {zcash_fpga_top/control_top/debug_if3/dat[3]} {zcash_fpga_top/control_top/debug_if3/dat[4]} {zcash_fpga_top/control_top/debug_if3/dat[5]} {zcash_fpga_top/control_top/debug_if3/dat[6]} {zcash_fpga_top/control_top/debug_if3/dat[7]} {zcash_fpga_top/control_top/debug_if3/dat[8]} {zcash_fpga_top/control_top/debug_if3/dat[9]} {zcash_fpga_top/control_top/debug_if3/dat[10]} {zcash_fpga_top/control_top/debug_if3/dat[11]} {zcash_fpga_top/control_top/debug_if3/dat[12]} {zcash_fpga_top/control_top/debug_if3/dat[13]} {zcash_fpga_top/control_top/debug_if3/dat[14]} {zcash_fpga_top/control_top/debug_if3/dat[15]} {zcash_fpga_top/control_top/debug_if3/dat[16]} {zcash_fpga_top/control_top/debug_if3/dat[17]} {zcash_fpga_top/control_top/debug_if3/dat[18]} {zcash_fpga_top/control_top/debug_if3/dat[19]} {zcash_fpga_top/control_top/debug_if3/dat[20]} {zcash_fpga_top/control_top/debug_if3/dat[21]} {zcash_fpga_top/control_top/debug_if3/dat[22]} {zcash_fpga_top/control_top/debug_if3/dat[23]} {zcash_fpga_top/control_top/debug_if3/dat[24]} {zcash_fpga_top/control_top/debug_if3/dat[25]} {zcash_fpga_top/control_top/debug_if3/dat[26]} {zcash_fpga_top/control_top/debug_if3/dat[27]} {zcash_fpga_top/control_top/debug_if3/dat[28]} {zcash_fpga_top/control_top/debug_if3/dat[29]} {zcash_fpga_top/control_top/debug_if3/dat[30]} {zcash_fpga_top/control_top/debug_if3/dat[31]} {zcash_fpga_top/control_top/debug_if3/dat[32]} {zcash_fpga_top/control_top/debug_if3/dat[33]} {zcash_fpga_top/control_top/debug_if3/dat[34]} {zcash_fpga_top/control_top/debug_if3/dat[35]} {zcash_fpga_top/control_top/debug_if3/dat[36]} {zcash_fpga_top/control_top/debug_if3/dat[37]} {zcash_fpga_top/control_top/debug_if3/dat[38]} {zcash_fpga_top/control_top/debug_if3/dat[39]} {zcash_fpga_top/control_top/debug_if3/dat[40]} {zcash_fpga_top/control_top/debug_if3/dat[41]} {zcash_fpga_top/control_top/debug_if3/dat[42]} {zcash_fpga_top/control_top/debug_if3/dat[43]} {zcash_fpga_top/control_top/debug_if3/dat[44]} {zcash_fpga_top/control_top/debug_if3/dat[45]} {zcash_fpga_top/control_top/debug_if3/dat[46]} {zcash_fpga_top/control_top/debug_if3/dat[47]} {zcash_fpga_top/control_top/debug_if3/dat[48]} {zcash_fpga_top/control_top/debug_if3/dat[49]} {zcash_fpga_top/control_top/debug_if3/dat[50]} {zcash_fpga_top/control_top/debug_if3/dat[51]} {zcash_fpga_top/control_top/debug_if3/dat[52]} {zcash_fpga_top/control_top/debug_if3/dat[53]} {zcash_fpga_top/control_top/debug_if3/dat[54]} {zcash_fpga_top/control_top/debug_if3/dat[55]} {zcash_fpga_top/control_top/debug_if3/dat[56]} {zcash_fpga_top/control_top/debug_if3/dat[57]} {zcash_fpga_top/control_top/debug_if3/dat[58]} {zcash_fpga_top/control_top/debug_if3/dat[59]} {zcash_fpga_top/control_top/debug_if3/dat[60]} {zcash_fpga_top/control_top/debug_if3/dat[61]} {zcash_fpga_top/control_top/debug_if3/dat[62]} {zcash_fpga_top/control_top/debug_if3/dat[63]}]] -connect_debug_port u_ila_1/probe3 [get_nets [list {zcash_fpga_top/control_top/debug_if3/mod[0]} {zcash_fpga_top/control_top/debug_if3/mod[1]} {zcash_fpga_top/control_top/debug_if3/mod[2]}]] -connect_debug_port u_ila_1/probe4 [get_nets [list zcash_fpga_top/control_top/debug_if2/ctl]] -connect_debug_port u_ila_1/probe5 [get_nets [list zcash_fpga_top/control_top/debug_if3/ctl]] -connect_debug_port u_ila_1/probe6 [get_nets [list zcash_fpga_top/control_top/debug_if3/eop]] -connect_debug_port u_ila_1/probe7 [get_nets [list zcash_fpga_top/control_top/debug_if2/eop]] -connect_debug_port u_ila_1/probe8 [get_nets [list zcash_fpga_top/control_top/debug_if2/err]] -connect_debug_port u_ila_1/probe9 [get_nets [list zcash_fpga_top/control_top/debug_if3/err]] -connect_debug_port u_ila_1/probe10 [get_nets [list zcash_fpga_top/control_top/debug_if3/rdy]] -connect_debug_port u_ila_1/probe11 [get_nets [list zcash_fpga_top/control_top/debug_if2/rdy]] -connect_debug_port u_ila_1/probe12 [get_nets [list zcash_fpga_top/control_top/debug_if3/sop]] -connect_debug_port u_ila_1/probe13 [get_nets [list zcash_fpga_top/control_top/debug_if2/sop]] -connect_debug_port u_ila_1/probe14 [get_nets [list zcash_fpga_top/control_top/debug_if2/val]] -connect_debug_port u_ila_1/probe15 [get_nets [list zcash_fpga_top/control_top/debug_if3/val]] - - - -connect_debug_port u_ila_1/probe10 [get_nets [list {uart_wrapper/uart_debug_if/dat[0]} {uart_wrapper/uart_debug_if/dat[1]} {uart_wrapper/uart_debug_if/dat[2]} {uart_wrapper/uart_debug_if/dat[3]} {uart_wrapper/uart_debug_if/dat[4]} {uart_wrapper/uart_debug_if/dat[5]} {uart_wrapper/uart_debug_if/dat[6]} {uart_wrapper/uart_debug_if/dat[7]}]] -connect_debug_port u_ila_1/probe12 [get_nets [list uart_wrapper/uart_debug_if/ctl]] -connect_debug_port u_ila_1/probe15 [get_nets [list uart_wrapper/uart_debug_if/eop]] -connect_debug_port u_ila_1/probe16 [get_nets [list uart_wrapper/uart_debug_if/err]] -connect_debug_port u_ila_1/probe19 [get_nets [list uart_wrapper/uart_debug_if/mod]] -connect_debug_port u_ila_1/probe21 [get_nets [list uart_wrapper/uart_debug_if/rdy]] -connect_debug_port u_ila_1/probe24 [get_nets [list uart_wrapper/uart_debug_if/sop]] -connect_debug_port u_ila_1/probe31 [get_nets [list uart_wrapper/uart_debug_if/val]] - -connect_debug_port u_ila_0/probe0 [get_nets [list {zcash_fpga_top/control_top/debug_if2/dat[0]} {zcash_fpga_top/control_top/debug_if2/dat[1]} {zcash_fpga_top/control_top/debug_if2/dat[2]} {zcash_fpga_top/control_top/debug_if2/dat[3]} {zcash_fpga_top/control_top/debug_if2/dat[4]} {zcash_fpga_top/control_top/debug_if2/dat[5]} {zcash_fpga_top/control_top/debug_if2/dat[6]} {zcash_fpga_top/control_top/debug_if2/dat[7]}]] -connect_debug_port u_ila_0/probe1 [get_nets [list {uart_wrapper/rx_byt_len[0]} {uart_wrapper/rx_byt_len[1]} {uart_wrapper/rx_byt_len[2]} {uart_wrapper/rx_byt_len[3]} {uart_wrapper/rx_byt_len[4]} {uart_wrapper/rx_byt_len[5]} {uart_wrapper/rx_byt_len[6]} {uart_wrapper/rx_byt_len[7]} {uart_wrapper/rx_byt_len[8]} {uart_wrapper/rx_byt_len[9]} {uart_wrapper/rx_byt_len[10]} {uart_wrapper/rx_byt_len[11]} {uart_wrapper/rx_byt_len[12]} {uart_wrapper/rx_byt_len[13]} {uart_wrapper/rx_byt_len[14]} {uart_wrapper/rx_byt_len[15]}]] -connect_debug_port u_ila_0/probe2 [get_nets [list {uart_wrapper/rx_byt_cnt[0]} {uart_wrapper/rx_byt_cnt[1]} {uart_wrapper/rx_byt_cnt[2]} {uart_wrapper/rx_byt_cnt[3]} {uart_wrapper/rx_byt_cnt[4]} {uart_wrapper/rx_byt_cnt[5]} {uart_wrapper/rx_byt_cnt[6]} {uart_wrapper/rx_byt_cnt[7]} {uart_wrapper/rx_byt_cnt[8]} {uart_wrapper/rx_byt_cnt[9]} {uart_wrapper/rx_byt_cnt[10]} {uart_wrapper/rx_byt_cnt[11]} {uart_wrapper/rx_byt_cnt[12]} {uart_wrapper/rx_byt_cnt[13]} {uart_wrapper/rx_byt_cnt[14]} {uart_wrapper/rx_byt_cnt[15]}]] -connect_debug_port u_ila_0/probe3 [get_nets [list {uart_wrapper/tx_byt_cnt[0]} {uart_wrapper/tx_byt_cnt[1]} {uart_wrapper/tx_byt_cnt[2]} {uart_wrapper/tx_byt_cnt[3]} {uart_wrapper/tx_byt_cnt[4]} {uart_wrapper/tx_byt_cnt[5]} {uart_wrapper/tx_byt_cnt[6]} {uart_wrapper/tx_byt_cnt[7]} {uart_wrapper/tx_byt_cnt[8]} {uart_wrapper/tx_byt_cnt[9]} {uart_wrapper/tx_byt_cnt[10]} {uart_wrapper/tx_byt_cnt[11]} {uart_wrapper/tx_byt_cnt[12]} {uart_wrapper/tx_byt_cnt[13]} {uart_wrapper/tx_byt_cnt[14]} {uart_wrapper/tx_byt_cnt[15]}]] -connect_debug_port u_ila_0/probe4 [get_nets [list {uart_wrapper/uart_axi_araddr[0]} {uart_wrapper/uart_axi_araddr[1]} {uart_wrapper/uart_axi_araddr[2]} {uart_wrapper/uart_axi_araddr[3]}]] -connect_debug_port u_ila_0/probe6 [get_nets [list {uart_wrapper/uart_axi_bresp[1]}]] -connect_debug_port u_ila_0/probe12 [get_nets [list {uart_wrapper/uart_axi_wdata[0]} {uart_wrapper/uart_axi_wdata[1]} {uart_wrapper/uart_axi_wdata[2]} {uart_wrapper/uart_axi_wdata[3]} {uart_wrapper/uart_axi_wdata[4]} {uart_wrapper/uart_axi_wdata[5]} {uart_wrapper/uart_axi_wdata[6]} {uart_wrapper/uart_axi_wdata[7]} {uart_wrapper/uart_axi_wdata[8]} {uart_wrapper/uart_axi_wdata[9]} {uart_wrapper/uart_axi_wdata[10]} {uart_wrapper/uart_axi_wdata[11]} {uart_wrapper/uart_axi_wdata[12]} {uart_wrapper/uart_axi_wdata[13]} {uart_wrapper/uart_axi_wdata[14]} {uart_wrapper/uart_axi_wdata[15]} {uart_wrapper/uart_axi_wdata[16]} {uart_wrapper/uart_axi_wdata[17]} {uart_wrapper/uart_axi_wdata[18]} {uart_wrapper/uart_axi_wdata[19]} {uart_wrapper/uart_axi_wdata[20]} {uart_wrapper/uart_axi_wdata[21]} {uart_wrapper/uart_axi_wdata[22]} {uart_wrapper/uart_axi_wdata[23]} {uart_wrapper/uart_axi_wdata[24]} {uart_wrapper/uart_axi_wdata[25]} {uart_wrapper/uart_axi_wdata[26]} {uart_wrapper/uart_axi_wdata[27]} {uart_wrapper/uart_axi_wdata[28]} {uart_wrapper/uart_axi_wdata[29]} {uart_wrapper/uart_axi_wdata[30]} {uart_wrapper/uart_axi_wdata[31]}]] -connect_debug_port u_ila_0/probe13 [get_nets [list {uart_wrapper/uart_state[0]} {uart_wrapper/uart_state[1]} {uart_wrapper/uart_state[2]} {uart_wrapper/uart_state[3]} {uart_wrapper/uart_state[4]} {uart_wrapper/uart_state[5]} {uart_wrapper/uart_state[6]} {uart_wrapper/uart_state[7]} {uart_wrapper/uart_state[8]} {uart_wrapper/uart_state[9]} {uart_wrapper/uart_state[10]} {uart_wrapper/uart_state[11]} {uart_wrapper/uart_state[12]} {uart_wrapper/uart_state[13]} {uart_wrapper/uart_state[14]} {uart_wrapper/uart_state[15]} {uart_wrapper/uart_state[16]} {uart_wrapper/uart_state[17]} {uart_wrapper/uart_state[18]} {uart_wrapper/uart_state[19]} {uart_wrapper/uart_state[20]} {uart_wrapper/uart_state[21]} {uart_wrapper/uart_state[22]} {uart_wrapper/uart_state[23]} {uart_wrapper/uart_state[24]} {uart_wrapper/uart_state[25]} {uart_wrapper/uart_state[26]} {uart_wrapper/uart_state[27]} {uart_wrapper/uart_state[28]} {uart_wrapper/uart_state[29]} {uart_wrapper/uart_state[30]} {uart_wrapper/uart_state[31]}]] -connect_debug_port u_ila_0/probe16 [get_nets [list zcash_fpga_top/control_top/debug_if2/ctl]] -connect_debug_port u_ila_0/probe19 [get_nets [list zcash_fpga_top/control_top/debug_if2/eop]] -connect_debug_port u_ila_0/probe21 [get_nets [list zcash_fpga_top/control_top/debug_if2/err]] -connect_debug_port u_ila_0/probe26 [get_nets [list zcash_fpga_top/control_top/debug_if2/mod]] -connect_debug_port u_ila_0/probe27 [get_nets [list zcash_fpga_top/control_top/debug_if2/rdy]] -connect_debug_port u_ila_0/probe30 [get_nets [list zcash_fpga_top/control_top/debug_if2/sop]] -connect_debug_port u_ila_0/probe34 [get_nets [list uart_wrapper/uart_axi_arvalid]] -connect_debug_port u_ila_0/probe36 [get_nets [list uart_wrapper/uart_axi_awvalid]] -connect_debug_port u_ila_0/probe38 [get_nets [list uart_wrapper/uart_axi_wready]] -connect_debug_port u_ila_0/probe40 [get_nets [list zcash_fpga_top/control_top/debug_if2/val]] -connect_debug_port u_ila_1/probe0 [get_nets [list {zcash_fpga_top/control_top/debug_if0/mod[0]} {zcash_fpga_top/control_top/debug_if0/mod[1]} {zcash_fpga_top/control_top/debug_if0/mod[2]}]] -connect_debug_port u_ila_1/probe1 [get_nets [list {zcash_fpga_top/control_top/debug_if1/dat[0]} {zcash_fpga_top/control_top/debug_if1/dat[1]} {zcash_fpga_top/control_top/debug_if1/dat[2]} {zcash_fpga_top/control_top/debug_if1/dat[3]} {zcash_fpga_top/control_top/debug_if1/dat[4]} {zcash_fpga_top/control_top/debug_if1/dat[5]} {zcash_fpga_top/control_top/debug_if1/dat[6]} {zcash_fpga_top/control_top/debug_if1/dat[7]} {zcash_fpga_top/control_top/debug_if1/dat[8]} {zcash_fpga_top/control_top/debug_if1/dat[9]} {zcash_fpga_top/control_top/debug_if1/dat[10]} {zcash_fpga_top/control_top/debug_if1/dat[11]} {zcash_fpga_top/control_top/debug_if1/dat[12]} {zcash_fpga_top/control_top/debug_if1/dat[13]} {zcash_fpga_top/control_top/debug_if1/dat[14]} {zcash_fpga_top/control_top/debug_if1/dat[15]} {zcash_fpga_top/control_top/debug_if1/dat[16]} {zcash_fpga_top/control_top/debug_if1/dat[17]} {zcash_fpga_top/control_top/debug_if1/dat[18]} {zcash_fpga_top/control_top/debug_if1/dat[19]} {zcash_fpga_top/control_top/debug_if1/dat[20]} {zcash_fpga_top/control_top/debug_if1/dat[21]} {zcash_fpga_top/control_top/debug_if1/dat[22]} {zcash_fpga_top/control_top/debug_if1/dat[23]} {zcash_fpga_top/control_top/debug_if1/dat[24]} {zcash_fpga_top/control_top/debug_if1/dat[25]} {zcash_fpga_top/control_top/debug_if1/dat[26]} {zcash_fpga_top/control_top/debug_if1/dat[27]} {zcash_fpga_top/control_top/debug_if1/dat[28]} {zcash_fpga_top/control_top/debug_if1/dat[29]} {zcash_fpga_top/control_top/debug_if1/dat[30]} {zcash_fpga_top/control_top/debug_if1/dat[31]} {zcash_fpga_top/control_top/debug_if1/dat[32]} {zcash_fpga_top/control_top/debug_if1/dat[33]} {zcash_fpga_top/control_top/debug_if1/dat[34]} {zcash_fpga_top/control_top/debug_if1/dat[35]} {zcash_fpga_top/control_top/debug_if1/dat[36]} {zcash_fpga_top/control_top/debug_if1/dat[37]} {zcash_fpga_top/control_top/debug_if1/dat[38]} {zcash_fpga_top/control_top/debug_if1/dat[39]} {zcash_fpga_top/control_top/debug_if1/dat[40]} {zcash_fpga_top/control_top/debug_if1/dat[41]} {zcash_fpga_top/control_top/debug_if1/dat[42]} {zcash_fpga_top/control_top/debug_if1/dat[43]} {zcash_fpga_top/control_top/debug_if1/dat[44]} {zcash_fpga_top/control_top/debug_if1/dat[45]} {zcash_fpga_top/control_top/debug_if1/dat[46]} {zcash_fpga_top/control_top/debug_if1/dat[47]} {zcash_fpga_top/control_top/debug_if1/dat[48]} {zcash_fpga_top/control_top/debug_if1/dat[49]} {zcash_fpga_top/control_top/debug_if1/dat[50]} {zcash_fpga_top/control_top/debug_if1/dat[51]} {zcash_fpga_top/control_top/debug_if1/dat[52]} {zcash_fpga_top/control_top/debug_if1/dat[53]} {zcash_fpga_top/control_top/debug_if1/dat[54]} {zcash_fpga_top/control_top/debug_if1/dat[55]} {zcash_fpga_top/control_top/debug_if1/dat[56]} {zcash_fpga_top/control_top/debug_if1/dat[57]} {zcash_fpga_top/control_top/debug_if1/dat[58]} {zcash_fpga_top/control_top/debug_if1/dat[59]} {zcash_fpga_top/control_top/debug_if1/dat[60]} {zcash_fpga_top/control_top/debug_if1/dat[61]} {zcash_fpga_top/control_top/debug_if1/dat[62]} {zcash_fpga_top/control_top/debug_if1/dat[63]}]] -connect_debug_port u_ila_1/probe2 [get_nets [list {zcash_fpga_top/control_top/debug_if1/mod[0]} {zcash_fpga_top/control_top/debug_if1/mod[1]} {zcash_fpga_top/control_top/debug_if1/mod[2]}]] -connect_debug_port u_ila_1/probe3 [get_nets [list {zcash_fpga_top/control_top/debug_if0/dat[0]} {zcash_fpga_top/control_top/debug_if0/dat[1]} {zcash_fpga_top/control_top/debug_if0/dat[2]} {zcash_fpga_top/control_top/debug_if0/dat[3]} {zcash_fpga_top/control_top/debug_if0/dat[4]} {zcash_fpga_top/control_top/debug_if0/dat[5]} {zcash_fpga_top/control_top/debug_if0/dat[6]} {zcash_fpga_top/control_top/debug_if0/dat[7]} {zcash_fpga_top/control_top/debug_if0/dat[8]} {zcash_fpga_top/control_top/debug_if0/dat[9]} {zcash_fpga_top/control_top/debug_if0/dat[10]} {zcash_fpga_top/control_top/debug_if0/dat[11]} {zcash_fpga_top/control_top/debug_if0/dat[12]} {zcash_fpga_top/control_top/debug_if0/dat[13]} {zcash_fpga_top/control_top/debug_if0/dat[14]} {zcash_fpga_top/control_top/debug_if0/dat[15]} {zcash_fpga_top/control_top/debug_if0/dat[16]} {zcash_fpga_top/control_top/debug_if0/dat[17]} {zcash_fpga_top/control_top/debug_if0/dat[18]} {zcash_fpga_top/control_top/debug_if0/dat[19]} {zcash_fpga_top/control_top/debug_if0/dat[20]} {zcash_fpga_top/control_top/debug_if0/dat[21]} {zcash_fpga_top/control_top/debug_if0/dat[22]} {zcash_fpga_top/control_top/debug_if0/dat[23]} {zcash_fpga_top/control_top/debug_if0/dat[24]} {zcash_fpga_top/control_top/debug_if0/dat[25]} {zcash_fpga_top/control_top/debug_if0/dat[26]} {zcash_fpga_top/control_top/debug_if0/dat[27]} {zcash_fpga_top/control_top/debug_if0/dat[28]} {zcash_fpga_top/control_top/debug_if0/dat[29]} {zcash_fpga_top/control_top/debug_if0/dat[30]} {zcash_fpga_top/control_top/debug_if0/dat[31]} {zcash_fpga_top/control_top/debug_if0/dat[32]} {zcash_fpga_top/control_top/debug_if0/dat[33]} {zcash_fpga_top/control_top/debug_if0/dat[34]} {zcash_fpga_top/control_top/debug_if0/dat[35]} {zcash_fpga_top/control_top/debug_if0/dat[36]} {zcash_fpga_top/control_top/debug_if0/dat[37]} {zcash_fpga_top/control_top/debug_if0/dat[38]} {zcash_fpga_top/control_top/debug_if0/dat[39]} {zcash_fpga_top/control_top/debug_if0/dat[40]} {zcash_fpga_top/control_top/debug_if0/dat[41]} {zcash_fpga_top/control_top/debug_if0/dat[42]} {zcash_fpga_top/control_top/debug_if0/dat[43]} {zcash_fpga_top/control_top/debug_if0/dat[44]} {zcash_fpga_top/control_top/debug_if0/dat[45]} {zcash_fpga_top/control_top/debug_if0/dat[46]} {zcash_fpga_top/control_top/debug_if0/dat[47]} {zcash_fpga_top/control_top/debug_if0/dat[48]} {zcash_fpga_top/control_top/debug_if0/dat[49]} {zcash_fpga_top/control_top/debug_if0/dat[50]} {zcash_fpga_top/control_top/debug_if0/dat[51]} {zcash_fpga_top/control_top/debug_if0/dat[52]} {zcash_fpga_top/control_top/debug_if0/dat[53]} {zcash_fpga_top/control_top/debug_if0/dat[54]} {zcash_fpga_top/control_top/debug_if0/dat[55]} {zcash_fpga_top/control_top/debug_if0/dat[56]} {zcash_fpga_top/control_top/debug_if0/dat[57]} {zcash_fpga_top/control_top/debug_if0/dat[58]} {zcash_fpga_top/control_top/debug_if0/dat[59]} {zcash_fpga_top/control_top/debug_if0/dat[60]} {zcash_fpga_top/control_top/debug_if0/dat[61]} {zcash_fpga_top/control_top/debug_if0/dat[62]} {zcash_fpga_top/control_top/debug_if0/dat[63]}]] -connect_debug_port u_ila_1/probe4 [get_nets [list zcash_fpga_top/control_top/debug_if0/ctl]] -connect_debug_port u_ila_1/probe5 [get_nets [list zcash_fpga_top/control_top/debug_if1/ctl]] -connect_debug_port u_ila_1/probe6 [get_nets [list zcash_fpga_top/control_top/debug_if1/eop]] -connect_debug_port u_ila_1/probe7 [get_nets [list zcash_fpga_top/control_top/debug_if0/eop]] -connect_debug_port u_ila_1/probe8 [get_nets [list zcash_fpga_top/control_top/debug_if0/err]] -connect_debug_port u_ila_1/probe9 [get_nets [list zcash_fpga_top/control_top/debug_if1/err]] -connect_debug_port u_ila_1/probe10 [get_nets [list zcash_fpga_top/control_top/debug_if0/rdy]] -connect_debug_port u_ila_1/probe11 [get_nets [list zcash_fpga_top/control_top/debug_if1/rdy]] -connect_debug_port u_ila_1/probe12 [get_nets [list zcash_fpga_top/control_top/debug_if1/sop]] -connect_debug_port u_ila_1/probe13 [get_nets [list zcash_fpga_top/control_top/debug_if0/sop]] -connect_debug_port u_ila_1/probe14 [get_nets [list zcash_fpga_top/control_top/debug_if0/val]] -connect_debug_port u_ila_1/probe15 [get_nets [list zcash_fpga_top/control_top/debug_if1/val]] - - - - -#Timing paths for CDC +# Timing paths for CDC set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] 2.500 set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] 2.500 set_bus_skew -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~ "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] 1.667 @@ -189,23 +51,7 @@ set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*dat_reg[0]*C" set_bus_skew -from [get_pins -filter { NAME =~ "*ram*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_out/* }]] -to [get_pins -filter { NAME =~ "*o_dat_b*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_out/* }]] 1.667 set_max_delay -datapath_only -from [get_pins -filter { NAME =~ "*ram*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_out/* }]] -to [get_pins -filter { NAME =~ "*o_dat_b*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_out/* }]] 1.667 - -connect_debug_port u_ila_1/probe0 [get_nets [list {zcash_fpga_top/secp256k1_top/debug_if_rx/mod[0]} {zcash_fpga_top/secp256k1_top/debug_if_rx/mod[1]} {zcash_fpga_top/secp256k1_top/debug_if_rx/mod[2]}]] -connect_debug_port u_ila_1/probe1 [get_nets [list {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[0]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[1]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[2]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[3]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[4]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[5]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[6]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[7]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[8]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[9]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[10]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[11]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[12]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[13]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[14]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[15]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[16]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[17]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[18]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[19]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[20]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[21]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[22]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[23]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[24]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[25]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[26]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[27]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[28]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[29]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[30]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[31]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[32]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[33]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[34]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[35]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[36]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[37]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[38]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[39]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[40]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[41]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[42]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[43]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[44]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[45]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[46]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[47]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[48]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[49]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[50]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[51]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[52]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[53]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[54]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[55]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[56]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[57]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[58]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[59]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[60]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[61]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[62]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[63]}]] -connect_debug_port u_ila_1/probe2 [get_nets [list {zcash_fpga_top/secp256k1_top/debug_if_tx/mod[0]} {zcash_fpga_top/secp256k1_top/debug_if_tx/mod[1]} {zcash_fpga_top/secp256k1_top/debug_if_tx/mod[2]}]] -connect_debug_port u_ila_1/probe3 [get_nets [list {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[0]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[1]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[2]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[3]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[4]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[5]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[6]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[7]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[8]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[9]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[10]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[11]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[12]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[13]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[14]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[15]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[16]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[17]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[18]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[19]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[20]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[21]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[22]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[23]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[24]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[25]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[26]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[27]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[28]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[29]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[30]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[31]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[32]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[33]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[34]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[35]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[36]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[37]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[38]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[39]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[40]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[41]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[42]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[43]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[44]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[45]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[46]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[47]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[48]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[49]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[50]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[51]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[52]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[53]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[54]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[55]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[56]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[57]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[58]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[59]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[60]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[61]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[62]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[63]}]] -connect_debug_port u_ila_1/probe11 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_rx/ctl]] -connect_debug_port u_ila_1/probe12 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_tx/ctl]] -connect_debug_port u_ila_1/probe13 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_rx/eop]] -connect_debug_port u_ila_1/probe15 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_tx/eop]] -connect_debug_port u_ila_1/probe18 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_rx/err]] -connect_debug_port u_ila_1/probe19 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_tx/err]] -connect_debug_port u_ila_1/probe23 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_rx/rdy]] -connect_debug_port u_ila_1/probe24 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_tx/rdy]] -connect_debug_port u_ila_1/probe25 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_rx/sop]] -connect_debug_port u_ila_1/probe27 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_tx/sop]] -connect_debug_port u_ila_1/probe30 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_tx/val]] -connect_debug_port u_ila_1/probe31 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_rx/val]] +# Reset syncs set_false_path -from [get_pins {zcash_fpga_top/core_rst1_sync/dat_reg[0][0]/C}] -to [get_pins {zcash_fpga_top/core_rst1_sync/dat_reg[2][0]_srl2/D}] set_false_path -from [get_pins {zcash_fpga_top/if_rst_sync/dat_reg[0][0]/C}] -to [get_pins {zcash_fpga_top/if_rst_sync/dat_reg[2][0]_srl2/D}] diff --git a/bittware_xupvvh/synth/debug.xdc b/bittware_xupvvh/synth/debug.xdc new file mode 100644 index 0000000..5ef54cf --- /dev/null +++ b/bittware_xupvvh/synth/debug.xdc @@ -0,0 +1,153 @@ +#Debug +connect_debug_port u_ila_0/probe6 [get_nets [list interrupt_r]] +connect_debug_port u_ila_0/probe7 [get_nets [list tx]] +connect_debug_port u_ila_0/probe8 [get_nets [list tx2]] +connect_debug_port u_ila_0/probe15 [get_nets [list usb_uart_txd_IBUF]] + +connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_pll/inst/clk_out300]] +connect_debug_port u_ila_0/probe2 [get_nets [list {check_rst[0]} {check_rst[1]} {check_rst[2]} {check_rst[3]} {check_rst[4]} {check_rst[5]} {check_rst[6]} {check_rst[7]}]] +connect_debug_port u_ila_0/probe5 [get_nets [list {clk_out300_rst_r[0]} {clk_out300_rst_r[1]} {clk_out300_rst_r[2]}]] +connect_debug_port u_ila_1/clk [get_nets [list clk_wiz_pll/inst/clk_out100]] +connect_debug_port u_ila_1/probe0 [get_nets [list {clk_out100_rst_r[0]} {clk_out100_rst_r[1]} {clk_out100_rst_r[2]}]] +connect_debug_port dbg_hub/clk [get_nets clk_out100] + + + +connect_debug_port u_ila_0/probe1 [get_nets [list {uart_state[0]} {uart_state[1]} {uart_state[2]} {uart_state[3]} {uart_state[4]} {uart_state[5]} {uart_state[6]} {uart_state[7]} {uart_state[8]} {uart_state[9]} {uart_state[10]} {uart_state[11]} {uart_state[12]} {uart_state[13]} {uart_state[14]} {uart_state[15]} {uart_state[16]} {uart_state[17]} {uart_state[18]} {uart_state[19]} {uart_state[20]} {uart_state[21]} {uart_state[22]} {uart_state[23]} {uart_state[24]} {uart_state[25]} {uart_state[26]} {uart_state[27]} {uart_state[28]} {uart_state[29]} {uart_state[30]} {uart_state[31]}]] +connect_debug_port u_ila_0/probe2 [get_nets [list {uart_axi_awaddr[0]} {uart_axi_awaddr[1]} {uart_axi_awaddr[2]} {uart_axi_awaddr[3]}]] +connect_debug_port u_ila_0/probe3 [get_nets [list {uart_axi_rdata[0]} {uart_axi_rdata[1]} {uart_axi_rdata[2]} {uart_axi_rdata[3]} {uart_axi_rdata[4]} {uart_axi_rdata[5]} {uart_axi_rdata[6]} {uart_axi_rdata[7]} {uart_axi_rdata[8]} {uart_axi_rdata[9]} {uart_axi_rdata[10]} {uart_axi_rdata[11]} {uart_axi_rdata[12]} {uart_axi_rdata[13]} {uart_axi_rdata[14]} {uart_axi_rdata[15]} {uart_axi_rdata[16]} {uart_axi_rdata[17]} {uart_axi_rdata[18]} {uart_axi_rdata[19]} {uart_axi_rdata[20]} {uart_axi_rdata[21]} {uart_axi_rdata[22]} {uart_axi_rdata[23]} {uart_axi_rdata[24]} {uart_axi_rdata[25]} {uart_axi_rdata[26]} {uart_axi_rdata[27]} {uart_axi_rdata[28]} {uart_axi_rdata[29]} {uart_axi_rdata[30]} {uart_axi_rdata[31]}]] +connect_debug_port u_ila_0/probe4 [get_nets [list {uart_axi_rresp[0]} {uart_axi_rresp[1]}]] +connect_debug_port u_ila_0/probe5 [get_nets [list {uart_axi_araddr[0]} {uart_axi_araddr[1]} {uart_axi_araddr[2]} {uart_axi_araddr[3]}]] +connect_debug_port u_ila_0/probe6 [get_nets [list {uart_axi_wdata[0]} {uart_axi_wdata[1]} {uart_axi_wdata[2]} {uart_axi_wdata[3]} {uart_axi_wdata[4]} {uart_axi_wdata[5]} {uart_axi_wdata[6]} {uart_axi_wdata[7]} {uart_axi_wdata[8]} {uart_axi_wdata[9]} {uart_axi_wdata[10]} {uart_axi_wdata[11]} {uart_axi_wdata[12]} {uart_axi_wdata[13]} {uart_axi_wdata[14]} {uart_axi_wdata[15]} {uart_axi_wdata[16]} {uart_axi_wdata[17]} {uart_axi_wdata[18]} {uart_axi_wdata[19]} {uart_axi_wdata[20]} {uart_axi_wdata[21]} {uart_axi_wdata[22]} {uart_axi_wdata[23]} {uart_axi_wdata[24]} {uart_axi_wdata[25]} {uart_axi_wdata[26]} {uart_axi_wdata[27]} {uart_axi_wdata[28]} {uart_axi_wdata[29]} {uart_axi_wdata[30]} {uart_axi_wdata[31]}]] +connect_debug_port u_ila_0/probe7 [get_nets [list eop_l]] +connect_debug_port u_ila_0/probe9 [get_nets [list interrupt]] +connect_debug_port u_ila_0/probe10 [get_nets [list sop_l]] +connect_debug_port u_ila_0/probe11 [get_nets [list uart_axi_arready]] +connect_debug_port u_ila_0/probe12 [get_nets [list uart_axi_arvalid]] +connect_debug_port u_ila_0/probe13 [get_nets [list uart_axi_awready]] +connect_debug_port u_ila_0/probe14 [get_nets [list uart_axi_awvalid]] +connect_debug_port u_ila_0/probe15 [get_nets [list uart_axi_rvalid]] +connect_debug_port u_ila_0/probe16 [get_nets [list uart_axi_wready]] + +connect_debug_port u_ila_1/probe5 [get_nets [list {uart_wrapper/uart_axi_wdata_0[0]} {uart_wrapper/uart_axi_wdata_0[1]} {uart_wrapper/uart_axi_wdata_0[2]} {uart_wrapper/uart_axi_wdata_0[3]} {uart_wrapper/uart_axi_wdata_0[4]} {uart_wrapper/uart_axi_wdata_0[5]} {uart_wrapper/uart_axi_wdata_0[6]} {uart_wrapper/uart_axi_wdata_0[7]} {uart_wrapper/uart_axi_wdata_0[8]} {uart_wrapper/uart_axi_wdata_0[9]} {uart_wrapper/uart_axi_wdata_0[10]} {uart_wrapper/uart_axi_wdata_0[11]} {uart_wrapper/uart_axi_wdata_0[12]} {uart_wrapper/uart_axi_wdata_0[13]} {uart_wrapper/uart_axi_wdata_0[14]} {uart_wrapper/uart_axi_wdata_0[15]} {uart_wrapper/uart_axi_wdata_0[16]} {uart_wrapper/uart_axi_wdata_0[17]} {uart_wrapper/uart_axi_wdata_0[18]} {uart_wrapper/uart_axi_wdata_0[19]} {uart_wrapper/uart_axi_wdata_0[20]} {uart_wrapper/uart_axi_wdata_0[21]} {uart_wrapper/uart_axi_wdata_0[22]} {uart_wrapper/uart_axi_wdata_0[23]} {uart_wrapper/uart_axi_wdata_0[24]} {uart_wrapper/uart_axi_wdata_0[25]} {uart_wrapper/uart_axi_wdata_0[26]} {uart_wrapper/uart_axi_wdata_0[27]} {uart_wrapper/uart_axi_wdata_0[28]} {uart_wrapper/uart_axi_wdata_0[29]} {uart_wrapper/uart_axi_wdata_0[30]} {uart_wrapper/uart_axi_wdata_0[31]}]] + +connect_debug_port u_ila_0/probe0 [get_nets [list {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[0]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[1]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[2]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[3]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[4]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[5]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[6]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[7]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[8]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[9]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[10]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[11]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[12]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[13]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[14]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[15]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[16]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[17]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[18]} {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_dat_a[19]}]] +connect_debug_port u_ila_0/probe9 [get_nets [list zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/i_val_a]] +connect_debug_port u_ila_0/probe11 [get_nets [list zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/o_rdy_a]] +connect_debug_port u_ila_0/probe12 [get_nets [list zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/o_val_b]] +connect_debug_port u_ila_1/probe1 [get_nets [list {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[0]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[1]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[2]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[3]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[4]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[5]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[6]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[7]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[8]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[9]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[10]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[11]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[12]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[13]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[14]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[15]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[16]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[17]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[18]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[19]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[20]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[21]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[22]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[23]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[24]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[25]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[26]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[27]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[28]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[29]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[30]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[31]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[32]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[33]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[34]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[35]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[36]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[37]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[38]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[39]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[40]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[41]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[42]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[43]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[44]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[45]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[46]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[47]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[48]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[49]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[50]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[51]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[52]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[53]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[54]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[55]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[56]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[57]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[58]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[59]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[60]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[61]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[62]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[63]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[64]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[65]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[66]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[67]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[68]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[69]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[70]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[71]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[72]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[73]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[74]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[75]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[76]} {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_dat_a[77]}]] +connect_debug_port u_ila_1/probe2 [get_nets [list zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/i_val_a]] +connect_debug_port u_ila_1/probe3 [get_nets [list zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/o_rdy_a]] +connect_debug_port u_ila_1/probe4 [get_nets [list zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/o_val_b]] + +connect_debug_port u_ila_0/probe8 [get_nets [list {zcash_fpga_top/control_top/debug_if/mod[0]} {zcash_fpga_top/control_top/debug_if/mod[-1]}]] + + +connect_debug_port u_ila_0/probe5 [get_nets [list zcash_fpga_top/control_top/debug_if2/mod]] + +connect_debug_port u_ila_0/probe2 [get_nets [list {uart_wrapper/uart_axi_wdata_0[0]} {uart_wrapper/uart_axi_wdata_0[1]} {uart_wrapper/uart_axi_wdata_0[2]} {uart_wrapper/uart_axi_wdata_0[3]} {uart_wrapper/uart_axi_wdata_0[4]} {uart_wrapper/uart_axi_wdata_0[5]} {uart_wrapper/uart_axi_wdata_0[6]} {uart_wrapper/uart_axi_wdata_0[7]} {uart_wrapper/uart_axi_wdata_0[8]} {uart_wrapper/uart_axi_wdata_0[9]} {uart_wrapper/uart_axi_wdata_0[10]} {uart_wrapper/uart_axi_wdata_0[11]} {uart_wrapper/uart_axi_wdata_0[12]} {uart_wrapper/uart_axi_wdata_0[13]} {uart_wrapper/uart_axi_wdata_0[14]} {uart_wrapper/uart_axi_wdata_0[15]} {uart_wrapper/uart_axi_wdata_0[16]} {uart_wrapper/uart_axi_wdata_0[17]} {uart_wrapper/uart_axi_wdata_0[18]} {uart_wrapper/uart_axi_wdata_0[19]} {uart_wrapper/uart_axi_wdata_0[20]} {uart_wrapper/uart_axi_wdata_0[21]} {uart_wrapper/uart_axi_wdata_0[22]} {uart_wrapper/uart_axi_wdata_0[23]} {uart_wrapper/uart_axi_wdata_0[24]} {uart_wrapper/uart_axi_wdata_0[25]} {uart_wrapper/uart_axi_wdata_0[26]} {uart_wrapper/uart_axi_wdata_0[27]} {uart_wrapper/uart_axi_wdata_0[28]} {uart_wrapper/uart_axi_wdata_0[29]} {uart_wrapper/uart_axi_wdata_0[30]} {uart_wrapper/uart_axi_wdata_0[31]}]] +connect_debug_port u_ila_0/probe8 [get_nets [list {zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/o_dat_b[0]}]] +connect_debug_port u_ila_0/probe11 [get_nets [list uart_wrapper/eop_l]] +connect_debug_port u_ila_0/probe17 [get_nets [list uart_wrapper/sop_l]] +connect_debug_port u_ila_1/probe4 [get_nets [list {zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/o_dat_b[0]}]] + + + +connect_debug_port u_ila_0/probe2 [get_nets [list {uart_wrapper/debug_if/dat[0]} {uart_wrapper/debug_if/dat[1]} {uart_wrapper/debug_if/dat[2]} {uart_wrapper/debug_if/dat[3]} {uart_wrapper/debug_if/dat[4]} {uart_wrapper/debug_if/dat[5]} {uart_wrapper/debug_if/dat[6]} {uart_wrapper/debug_if/dat[7]}]] +connect_debug_port u_ila_0/probe13 [get_nets [list uart_wrapper/debug_if/ctl]] +connect_debug_port u_ila_0/probe15 [get_nets [list uart_wrapper/debug_if/eop]] +connect_debug_port u_ila_0/probe16 [get_nets [list uart_wrapper/debug_if/err]] +connect_debug_port u_ila_0/probe19 [get_nets [list uart_wrapper/debug_if/mod]] +connect_debug_port u_ila_0/probe21 [get_nets [list uart_wrapper/debug_if/rdy]] +connect_debug_port u_ila_0/probe23 [get_nets [list uart_wrapper/debug_if/sop]] +connect_debug_port u_ila_0/probe31 [get_nets [list uart_wrapper/debug_if/val]] + + +connect_debug_port u_ila_0/probe11 [get_nets [list {zcash_fpga_top/control_top/debug_if/dat[0]} {zcash_fpga_top/control_top/debug_if/dat[1]} {zcash_fpga_top/control_top/debug_if/dat[2]} {zcash_fpga_top/control_top/debug_if/dat[3]} {zcash_fpga_top/control_top/debug_if/dat[4]} {zcash_fpga_top/control_top/debug_if/dat[5]} {zcash_fpga_top/control_top/debug_if/dat[6]} {zcash_fpga_top/control_top/debug_if/dat[7]}]] +connect_debug_port u_ila_0/probe13 [get_nets [list zcash_fpga_top/control_top/debug_if/ctl]] +connect_debug_port u_ila_0/probe14 [get_nets [list zcash_fpga_top/control_top/debug_if/eop]] +connect_debug_port u_ila_0/probe17 [get_nets [list zcash_fpga_top/control_top/debug_if/err]] +connect_debug_port u_ila_0/probe20 [get_nets [list zcash_fpga_top/control_top/debug_if/mod]] +connect_debug_port u_ila_0/probe22 [get_nets [list zcash_fpga_top/control_top/debug_if/rdy]] +connect_debug_port u_ila_0/probe23 [get_nets [list zcash_fpga_top/control_top/debug_if/sop]] +connect_debug_port u_ila_0/probe32 [get_nets [list zcash_fpga_top/control_top/debug_if/val]] +connect_debug_port u_ila_1/probe0 [get_nets [list {zcash_fpga_top/control_top/debug_if2/mod[0]} {zcash_fpga_top/control_top/debug_if2/mod[1]} {zcash_fpga_top/control_top/debug_if2/mod[2]}]] +connect_debug_port u_ila_1/probe1 [get_nets [list {zcash_fpga_top/control_top/debug_if2/dat[0]} {zcash_fpga_top/control_top/debug_if2/dat[1]} {zcash_fpga_top/control_top/debug_if2/dat[2]} {zcash_fpga_top/control_top/debug_if2/dat[3]} {zcash_fpga_top/control_top/debug_if2/dat[4]} {zcash_fpga_top/control_top/debug_if2/dat[5]} {zcash_fpga_top/control_top/debug_if2/dat[6]} {zcash_fpga_top/control_top/debug_if2/dat[7]} {zcash_fpga_top/control_top/debug_if2/dat[8]} {zcash_fpga_top/control_top/debug_if2/dat[9]} {zcash_fpga_top/control_top/debug_if2/dat[10]} {zcash_fpga_top/control_top/debug_if2/dat[11]} {zcash_fpga_top/control_top/debug_if2/dat[12]} {zcash_fpga_top/control_top/debug_if2/dat[13]} {zcash_fpga_top/control_top/debug_if2/dat[14]} {zcash_fpga_top/control_top/debug_if2/dat[15]} {zcash_fpga_top/control_top/debug_if2/dat[16]} {zcash_fpga_top/control_top/debug_if2/dat[17]} {zcash_fpga_top/control_top/debug_if2/dat[18]} {zcash_fpga_top/control_top/debug_if2/dat[19]} {zcash_fpga_top/control_top/debug_if2/dat[20]} {zcash_fpga_top/control_top/debug_if2/dat[21]} {zcash_fpga_top/control_top/debug_if2/dat[22]} {zcash_fpga_top/control_top/debug_if2/dat[23]} {zcash_fpga_top/control_top/debug_if2/dat[24]} {zcash_fpga_top/control_top/debug_if2/dat[25]} {zcash_fpga_top/control_top/debug_if2/dat[26]} {zcash_fpga_top/control_top/debug_if2/dat[27]} {zcash_fpga_top/control_top/debug_if2/dat[28]} {zcash_fpga_top/control_top/debug_if2/dat[29]} {zcash_fpga_top/control_top/debug_if2/dat[30]} {zcash_fpga_top/control_top/debug_if2/dat[31]} {zcash_fpga_top/control_top/debug_if2/dat[32]} {zcash_fpga_top/control_top/debug_if2/dat[33]} {zcash_fpga_top/control_top/debug_if2/dat[34]} {zcash_fpga_top/control_top/debug_if2/dat[35]} {zcash_fpga_top/control_top/debug_if2/dat[36]} {zcash_fpga_top/control_top/debug_if2/dat[37]} {zcash_fpga_top/control_top/debug_if2/dat[38]} {zcash_fpga_top/control_top/debug_if2/dat[39]} {zcash_fpga_top/control_top/debug_if2/dat[40]} {zcash_fpga_top/control_top/debug_if2/dat[41]} {zcash_fpga_top/control_top/debug_if2/dat[42]} {zcash_fpga_top/control_top/debug_if2/dat[43]} {zcash_fpga_top/control_top/debug_if2/dat[44]} {zcash_fpga_top/control_top/debug_if2/dat[45]} {zcash_fpga_top/control_top/debug_if2/dat[46]} {zcash_fpga_top/control_top/debug_if2/dat[47]} {zcash_fpga_top/control_top/debug_if2/dat[48]} {zcash_fpga_top/control_top/debug_if2/dat[49]} {zcash_fpga_top/control_top/debug_if2/dat[50]} {zcash_fpga_top/control_top/debug_if2/dat[51]} {zcash_fpga_top/control_top/debug_if2/dat[52]} {zcash_fpga_top/control_top/debug_if2/dat[53]} {zcash_fpga_top/control_top/debug_if2/dat[54]} {zcash_fpga_top/control_top/debug_if2/dat[55]} {zcash_fpga_top/control_top/debug_if2/dat[56]} {zcash_fpga_top/control_top/debug_if2/dat[57]} {zcash_fpga_top/control_top/debug_if2/dat[58]} {zcash_fpga_top/control_top/debug_if2/dat[59]} {zcash_fpga_top/control_top/debug_if2/dat[60]} {zcash_fpga_top/control_top/debug_if2/dat[61]} {zcash_fpga_top/control_top/debug_if2/dat[62]} {zcash_fpga_top/control_top/debug_if2/dat[63]}]] +connect_debug_port u_ila_1/probe2 [get_nets [list {zcash_fpga_top/control_top/debug_if3/dat[0]} {zcash_fpga_top/control_top/debug_if3/dat[1]} {zcash_fpga_top/control_top/debug_if3/dat[2]} {zcash_fpga_top/control_top/debug_if3/dat[3]} {zcash_fpga_top/control_top/debug_if3/dat[4]} {zcash_fpga_top/control_top/debug_if3/dat[5]} {zcash_fpga_top/control_top/debug_if3/dat[6]} {zcash_fpga_top/control_top/debug_if3/dat[7]} {zcash_fpga_top/control_top/debug_if3/dat[8]} {zcash_fpga_top/control_top/debug_if3/dat[9]} {zcash_fpga_top/control_top/debug_if3/dat[10]} {zcash_fpga_top/control_top/debug_if3/dat[11]} {zcash_fpga_top/control_top/debug_if3/dat[12]} {zcash_fpga_top/control_top/debug_if3/dat[13]} {zcash_fpga_top/control_top/debug_if3/dat[14]} {zcash_fpga_top/control_top/debug_if3/dat[15]} {zcash_fpga_top/control_top/debug_if3/dat[16]} {zcash_fpga_top/control_top/debug_if3/dat[17]} {zcash_fpga_top/control_top/debug_if3/dat[18]} {zcash_fpga_top/control_top/debug_if3/dat[19]} {zcash_fpga_top/control_top/debug_if3/dat[20]} {zcash_fpga_top/control_top/debug_if3/dat[21]} {zcash_fpga_top/control_top/debug_if3/dat[22]} {zcash_fpga_top/control_top/debug_if3/dat[23]} {zcash_fpga_top/control_top/debug_if3/dat[24]} {zcash_fpga_top/control_top/debug_if3/dat[25]} {zcash_fpga_top/control_top/debug_if3/dat[26]} {zcash_fpga_top/control_top/debug_if3/dat[27]} {zcash_fpga_top/control_top/debug_if3/dat[28]} {zcash_fpga_top/control_top/debug_if3/dat[29]} {zcash_fpga_top/control_top/debug_if3/dat[30]} {zcash_fpga_top/control_top/debug_if3/dat[31]} {zcash_fpga_top/control_top/debug_if3/dat[32]} {zcash_fpga_top/control_top/debug_if3/dat[33]} {zcash_fpga_top/control_top/debug_if3/dat[34]} {zcash_fpga_top/control_top/debug_if3/dat[35]} {zcash_fpga_top/control_top/debug_if3/dat[36]} {zcash_fpga_top/control_top/debug_if3/dat[37]} {zcash_fpga_top/control_top/debug_if3/dat[38]} {zcash_fpga_top/control_top/debug_if3/dat[39]} {zcash_fpga_top/control_top/debug_if3/dat[40]} {zcash_fpga_top/control_top/debug_if3/dat[41]} {zcash_fpga_top/control_top/debug_if3/dat[42]} {zcash_fpga_top/control_top/debug_if3/dat[43]} {zcash_fpga_top/control_top/debug_if3/dat[44]} {zcash_fpga_top/control_top/debug_if3/dat[45]} {zcash_fpga_top/control_top/debug_if3/dat[46]} {zcash_fpga_top/control_top/debug_if3/dat[47]} {zcash_fpga_top/control_top/debug_if3/dat[48]} {zcash_fpga_top/control_top/debug_if3/dat[49]} {zcash_fpga_top/control_top/debug_if3/dat[50]} {zcash_fpga_top/control_top/debug_if3/dat[51]} {zcash_fpga_top/control_top/debug_if3/dat[52]} {zcash_fpga_top/control_top/debug_if3/dat[53]} {zcash_fpga_top/control_top/debug_if3/dat[54]} {zcash_fpga_top/control_top/debug_if3/dat[55]} {zcash_fpga_top/control_top/debug_if3/dat[56]} {zcash_fpga_top/control_top/debug_if3/dat[57]} {zcash_fpga_top/control_top/debug_if3/dat[58]} {zcash_fpga_top/control_top/debug_if3/dat[59]} {zcash_fpga_top/control_top/debug_if3/dat[60]} {zcash_fpga_top/control_top/debug_if3/dat[61]} {zcash_fpga_top/control_top/debug_if3/dat[62]} {zcash_fpga_top/control_top/debug_if3/dat[63]}]] +connect_debug_port u_ila_1/probe3 [get_nets [list {zcash_fpga_top/control_top/debug_if3/mod[0]} {zcash_fpga_top/control_top/debug_if3/mod[1]} {zcash_fpga_top/control_top/debug_if3/mod[2]}]] +connect_debug_port u_ila_1/probe4 [get_nets [list zcash_fpga_top/control_top/debug_if2/ctl]] +connect_debug_port u_ila_1/probe5 [get_nets [list zcash_fpga_top/control_top/debug_if3/ctl]] +connect_debug_port u_ila_1/probe6 [get_nets [list zcash_fpga_top/control_top/debug_if3/eop]] +connect_debug_port u_ila_1/probe7 [get_nets [list zcash_fpga_top/control_top/debug_if2/eop]] +connect_debug_port u_ila_1/probe8 [get_nets [list zcash_fpga_top/control_top/debug_if2/err]] +connect_debug_port u_ila_1/probe9 [get_nets [list zcash_fpga_top/control_top/debug_if3/err]] +connect_debug_port u_ila_1/probe10 [get_nets [list zcash_fpga_top/control_top/debug_if3/rdy]] +connect_debug_port u_ila_1/probe11 [get_nets [list zcash_fpga_top/control_top/debug_if2/rdy]] +connect_debug_port u_ila_1/probe12 [get_nets [list zcash_fpga_top/control_top/debug_if3/sop]] +connect_debug_port u_ila_1/probe13 [get_nets [list zcash_fpga_top/control_top/debug_if2/sop]] +connect_debug_port u_ila_1/probe14 [get_nets [list zcash_fpga_top/control_top/debug_if2/val]] +connect_debug_port u_ila_1/probe15 [get_nets [list zcash_fpga_top/control_top/debug_if3/val]] + + + +connect_debug_port u_ila_1/probe10 [get_nets [list {uart_wrapper/uart_debug_if/dat[0]} {uart_wrapper/uart_debug_if/dat[1]} {uart_wrapper/uart_debug_if/dat[2]} {uart_wrapper/uart_debug_if/dat[3]} {uart_wrapper/uart_debug_if/dat[4]} {uart_wrapper/uart_debug_if/dat[5]} {uart_wrapper/uart_debug_if/dat[6]} {uart_wrapper/uart_debug_if/dat[7]}]] +connect_debug_port u_ila_1/probe12 [get_nets [list uart_wrapper/uart_debug_if/ctl]] +connect_debug_port u_ila_1/probe15 [get_nets [list uart_wrapper/uart_debug_if/eop]] +connect_debug_port u_ila_1/probe16 [get_nets [list uart_wrapper/uart_debug_if/err]] +connect_debug_port u_ila_1/probe19 [get_nets [list uart_wrapper/uart_debug_if/mod]] +connect_debug_port u_ila_1/probe21 [get_nets [list uart_wrapper/uart_debug_if/rdy]] +connect_debug_port u_ila_1/probe24 [get_nets [list uart_wrapper/uart_debug_if/sop]] +connect_debug_port u_ila_1/probe31 [get_nets [list uart_wrapper/uart_debug_if/val]] + +connect_debug_port u_ila_0/probe0 [get_nets [list {zcash_fpga_top/control_top/debug_if2/dat[0]} {zcash_fpga_top/control_top/debug_if2/dat[1]} {zcash_fpga_top/control_top/debug_if2/dat[2]} {zcash_fpga_top/control_top/debug_if2/dat[3]} {zcash_fpga_top/control_top/debug_if2/dat[4]} {zcash_fpga_top/control_top/debug_if2/dat[5]} {zcash_fpga_top/control_top/debug_if2/dat[6]} {zcash_fpga_top/control_top/debug_if2/dat[7]}]] +connect_debug_port u_ila_0/probe1 [get_nets [list {uart_wrapper/rx_byt_len[0]} {uart_wrapper/rx_byt_len[1]} {uart_wrapper/rx_byt_len[2]} {uart_wrapper/rx_byt_len[3]} {uart_wrapper/rx_byt_len[4]} {uart_wrapper/rx_byt_len[5]} {uart_wrapper/rx_byt_len[6]} {uart_wrapper/rx_byt_len[7]} {uart_wrapper/rx_byt_len[8]} {uart_wrapper/rx_byt_len[9]} {uart_wrapper/rx_byt_len[10]} {uart_wrapper/rx_byt_len[11]} {uart_wrapper/rx_byt_len[12]} {uart_wrapper/rx_byt_len[13]} {uart_wrapper/rx_byt_len[14]} {uart_wrapper/rx_byt_len[15]}]] +connect_debug_port u_ila_0/probe2 [get_nets [list {uart_wrapper/rx_byt_cnt[0]} {uart_wrapper/rx_byt_cnt[1]} {uart_wrapper/rx_byt_cnt[2]} {uart_wrapper/rx_byt_cnt[3]} {uart_wrapper/rx_byt_cnt[4]} {uart_wrapper/rx_byt_cnt[5]} {uart_wrapper/rx_byt_cnt[6]} {uart_wrapper/rx_byt_cnt[7]} {uart_wrapper/rx_byt_cnt[8]} {uart_wrapper/rx_byt_cnt[9]} {uart_wrapper/rx_byt_cnt[10]} {uart_wrapper/rx_byt_cnt[11]} {uart_wrapper/rx_byt_cnt[12]} {uart_wrapper/rx_byt_cnt[13]} {uart_wrapper/rx_byt_cnt[14]} {uart_wrapper/rx_byt_cnt[15]}]] +connect_debug_port u_ila_0/probe3 [get_nets [list {uart_wrapper/tx_byt_cnt[0]} {uart_wrapper/tx_byt_cnt[1]} {uart_wrapper/tx_byt_cnt[2]} {uart_wrapper/tx_byt_cnt[3]} {uart_wrapper/tx_byt_cnt[4]} {uart_wrapper/tx_byt_cnt[5]} {uart_wrapper/tx_byt_cnt[6]} {uart_wrapper/tx_byt_cnt[7]} {uart_wrapper/tx_byt_cnt[8]} {uart_wrapper/tx_byt_cnt[9]} {uart_wrapper/tx_byt_cnt[10]} {uart_wrapper/tx_byt_cnt[11]} {uart_wrapper/tx_byt_cnt[12]} {uart_wrapper/tx_byt_cnt[13]} {uart_wrapper/tx_byt_cnt[14]} {uart_wrapper/tx_byt_cnt[15]}]] +connect_debug_port u_ila_0/probe4 [get_nets [list {uart_wrapper/uart_axi_araddr[0]} {uart_wrapper/uart_axi_araddr[1]} {uart_wrapper/uart_axi_araddr[2]} {uart_wrapper/uart_axi_araddr[3]}]] +connect_debug_port u_ila_0/probe6 [get_nets [list {uart_wrapper/uart_axi_bresp[1]}]] +connect_debug_port u_ila_0/probe12 [get_nets [list {uart_wrapper/uart_axi_wdata[0]} {uart_wrapper/uart_axi_wdata[1]} {uart_wrapper/uart_axi_wdata[2]} {uart_wrapper/uart_axi_wdata[3]} {uart_wrapper/uart_axi_wdata[4]} {uart_wrapper/uart_axi_wdata[5]} {uart_wrapper/uart_axi_wdata[6]} {uart_wrapper/uart_axi_wdata[7]} {uart_wrapper/uart_axi_wdata[8]} {uart_wrapper/uart_axi_wdata[9]} {uart_wrapper/uart_axi_wdata[10]} {uart_wrapper/uart_axi_wdata[11]} {uart_wrapper/uart_axi_wdata[12]} {uart_wrapper/uart_axi_wdata[13]} {uart_wrapper/uart_axi_wdata[14]} {uart_wrapper/uart_axi_wdata[15]} {uart_wrapper/uart_axi_wdata[16]} {uart_wrapper/uart_axi_wdata[17]} {uart_wrapper/uart_axi_wdata[18]} {uart_wrapper/uart_axi_wdata[19]} {uart_wrapper/uart_axi_wdata[20]} {uart_wrapper/uart_axi_wdata[21]} {uart_wrapper/uart_axi_wdata[22]} {uart_wrapper/uart_axi_wdata[23]} {uart_wrapper/uart_axi_wdata[24]} {uart_wrapper/uart_axi_wdata[25]} {uart_wrapper/uart_axi_wdata[26]} {uart_wrapper/uart_axi_wdata[27]} {uart_wrapper/uart_axi_wdata[28]} {uart_wrapper/uart_axi_wdata[29]} {uart_wrapper/uart_axi_wdata[30]} {uart_wrapper/uart_axi_wdata[31]}]] +connect_debug_port u_ila_0/probe13 [get_nets [list {uart_wrapper/uart_state[0]} {uart_wrapper/uart_state[1]} {uart_wrapper/uart_state[2]} {uart_wrapper/uart_state[3]} {uart_wrapper/uart_state[4]} {uart_wrapper/uart_state[5]} {uart_wrapper/uart_state[6]} {uart_wrapper/uart_state[7]} {uart_wrapper/uart_state[8]} {uart_wrapper/uart_state[9]} {uart_wrapper/uart_state[10]} {uart_wrapper/uart_state[11]} {uart_wrapper/uart_state[12]} {uart_wrapper/uart_state[13]} {uart_wrapper/uart_state[14]} {uart_wrapper/uart_state[15]} {uart_wrapper/uart_state[16]} {uart_wrapper/uart_state[17]} {uart_wrapper/uart_state[18]} {uart_wrapper/uart_state[19]} {uart_wrapper/uart_state[20]} {uart_wrapper/uart_state[21]} {uart_wrapper/uart_state[22]} {uart_wrapper/uart_state[23]} {uart_wrapper/uart_state[24]} {uart_wrapper/uart_state[25]} {uart_wrapper/uart_state[26]} {uart_wrapper/uart_state[27]} {uart_wrapper/uart_state[28]} {uart_wrapper/uart_state[29]} {uart_wrapper/uart_state[30]} {uart_wrapper/uart_state[31]}]] +connect_debug_port u_ila_0/probe16 [get_nets [list zcash_fpga_top/control_top/debug_if2/ctl]] +connect_debug_port u_ila_0/probe19 [get_nets [list zcash_fpga_top/control_top/debug_if2/eop]] +connect_debug_port u_ila_0/probe21 [get_nets [list zcash_fpga_top/control_top/debug_if2/err]] +connect_debug_port u_ila_0/probe26 [get_nets [list zcash_fpga_top/control_top/debug_if2/mod]] +connect_debug_port u_ila_0/probe27 [get_nets [list zcash_fpga_top/control_top/debug_if2/rdy]] +connect_debug_port u_ila_0/probe30 [get_nets [list zcash_fpga_top/control_top/debug_if2/sop]] +connect_debug_port u_ila_0/probe34 [get_nets [list uart_wrapper/uart_axi_arvalid]] +connect_debug_port u_ila_0/probe36 [get_nets [list uart_wrapper/uart_axi_awvalid]] +connect_debug_port u_ila_0/probe38 [get_nets [list uart_wrapper/uart_axi_wready]] +connect_debug_port u_ila_0/probe40 [get_nets [list zcash_fpga_top/control_top/debug_if2/val]] +connect_debug_port u_ila_1/probe0 [get_nets [list {zcash_fpga_top/control_top/debug_if0/mod[0]} {zcash_fpga_top/control_top/debug_if0/mod[1]} {zcash_fpga_top/control_top/debug_if0/mod[2]}]] +connect_debug_port u_ila_1/probe1 [get_nets [list {zcash_fpga_top/control_top/debug_if1/dat[0]} {zcash_fpga_top/control_top/debug_if1/dat[1]} {zcash_fpga_top/control_top/debug_if1/dat[2]} {zcash_fpga_top/control_top/debug_if1/dat[3]} {zcash_fpga_top/control_top/debug_if1/dat[4]} {zcash_fpga_top/control_top/debug_if1/dat[5]} {zcash_fpga_top/control_top/debug_if1/dat[6]} {zcash_fpga_top/control_top/debug_if1/dat[7]} {zcash_fpga_top/control_top/debug_if1/dat[8]} {zcash_fpga_top/control_top/debug_if1/dat[9]} {zcash_fpga_top/control_top/debug_if1/dat[10]} {zcash_fpga_top/control_top/debug_if1/dat[11]} {zcash_fpga_top/control_top/debug_if1/dat[12]} {zcash_fpga_top/control_top/debug_if1/dat[13]} {zcash_fpga_top/control_top/debug_if1/dat[14]} {zcash_fpga_top/control_top/debug_if1/dat[15]} {zcash_fpga_top/control_top/debug_if1/dat[16]} {zcash_fpga_top/control_top/debug_if1/dat[17]} {zcash_fpga_top/control_top/debug_if1/dat[18]} {zcash_fpga_top/control_top/debug_if1/dat[19]} {zcash_fpga_top/control_top/debug_if1/dat[20]} {zcash_fpga_top/control_top/debug_if1/dat[21]} {zcash_fpga_top/control_top/debug_if1/dat[22]} {zcash_fpga_top/control_top/debug_if1/dat[23]} {zcash_fpga_top/control_top/debug_if1/dat[24]} {zcash_fpga_top/control_top/debug_if1/dat[25]} {zcash_fpga_top/control_top/debug_if1/dat[26]} {zcash_fpga_top/control_top/debug_if1/dat[27]} {zcash_fpga_top/control_top/debug_if1/dat[28]} {zcash_fpga_top/control_top/debug_if1/dat[29]} {zcash_fpga_top/control_top/debug_if1/dat[30]} {zcash_fpga_top/control_top/debug_if1/dat[31]} {zcash_fpga_top/control_top/debug_if1/dat[32]} {zcash_fpga_top/control_top/debug_if1/dat[33]} {zcash_fpga_top/control_top/debug_if1/dat[34]} {zcash_fpga_top/control_top/debug_if1/dat[35]} {zcash_fpga_top/control_top/debug_if1/dat[36]} {zcash_fpga_top/control_top/debug_if1/dat[37]} {zcash_fpga_top/control_top/debug_if1/dat[38]} {zcash_fpga_top/control_top/debug_if1/dat[39]} {zcash_fpga_top/control_top/debug_if1/dat[40]} {zcash_fpga_top/control_top/debug_if1/dat[41]} {zcash_fpga_top/control_top/debug_if1/dat[42]} {zcash_fpga_top/control_top/debug_if1/dat[43]} {zcash_fpga_top/control_top/debug_if1/dat[44]} {zcash_fpga_top/control_top/debug_if1/dat[45]} {zcash_fpga_top/control_top/debug_if1/dat[46]} {zcash_fpga_top/control_top/debug_if1/dat[47]} {zcash_fpga_top/control_top/debug_if1/dat[48]} {zcash_fpga_top/control_top/debug_if1/dat[49]} {zcash_fpga_top/control_top/debug_if1/dat[50]} {zcash_fpga_top/control_top/debug_if1/dat[51]} {zcash_fpga_top/control_top/debug_if1/dat[52]} {zcash_fpga_top/control_top/debug_if1/dat[53]} {zcash_fpga_top/control_top/debug_if1/dat[54]} {zcash_fpga_top/control_top/debug_if1/dat[55]} {zcash_fpga_top/control_top/debug_if1/dat[56]} {zcash_fpga_top/control_top/debug_if1/dat[57]} {zcash_fpga_top/control_top/debug_if1/dat[58]} {zcash_fpga_top/control_top/debug_if1/dat[59]} {zcash_fpga_top/control_top/debug_if1/dat[60]} {zcash_fpga_top/control_top/debug_if1/dat[61]} {zcash_fpga_top/control_top/debug_if1/dat[62]} {zcash_fpga_top/control_top/debug_if1/dat[63]}]] +connect_debug_port u_ila_1/probe2 [get_nets [list {zcash_fpga_top/control_top/debug_if1/mod[0]} {zcash_fpga_top/control_top/debug_if1/mod[1]} {zcash_fpga_top/control_top/debug_if1/mod[2]}]] +connect_debug_port u_ila_1/probe3 [get_nets [list {zcash_fpga_top/control_top/debug_if0/dat[0]} {zcash_fpga_top/control_top/debug_if0/dat[1]} {zcash_fpga_top/control_top/debug_if0/dat[2]} {zcash_fpga_top/control_top/debug_if0/dat[3]} {zcash_fpga_top/control_top/debug_if0/dat[4]} {zcash_fpga_top/control_top/debug_if0/dat[5]} {zcash_fpga_top/control_top/debug_if0/dat[6]} {zcash_fpga_top/control_top/debug_if0/dat[7]} {zcash_fpga_top/control_top/debug_if0/dat[8]} {zcash_fpga_top/control_top/debug_if0/dat[9]} {zcash_fpga_top/control_top/debug_if0/dat[10]} {zcash_fpga_top/control_top/debug_if0/dat[11]} {zcash_fpga_top/control_top/debug_if0/dat[12]} {zcash_fpga_top/control_top/debug_if0/dat[13]} {zcash_fpga_top/control_top/debug_if0/dat[14]} {zcash_fpga_top/control_top/debug_if0/dat[15]} {zcash_fpga_top/control_top/debug_if0/dat[16]} {zcash_fpga_top/control_top/debug_if0/dat[17]} {zcash_fpga_top/control_top/debug_if0/dat[18]} {zcash_fpga_top/control_top/debug_if0/dat[19]} {zcash_fpga_top/control_top/debug_if0/dat[20]} {zcash_fpga_top/control_top/debug_if0/dat[21]} {zcash_fpga_top/control_top/debug_if0/dat[22]} {zcash_fpga_top/control_top/debug_if0/dat[23]} {zcash_fpga_top/control_top/debug_if0/dat[24]} {zcash_fpga_top/control_top/debug_if0/dat[25]} {zcash_fpga_top/control_top/debug_if0/dat[26]} {zcash_fpga_top/control_top/debug_if0/dat[27]} {zcash_fpga_top/control_top/debug_if0/dat[28]} {zcash_fpga_top/control_top/debug_if0/dat[29]} {zcash_fpga_top/control_top/debug_if0/dat[30]} {zcash_fpga_top/control_top/debug_if0/dat[31]} {zcash_fpga_top/control_top/debug_if0/dat[32]} {zcash_fpga_top/control_top/debug_if0/dat[33]} {zcash_fpga_top/control_top/debug_if0/dat[34]} {zcash_fpga_top/control_top/debug_if0/dat[35]} {zcash_fpga_top/control_top/debug_if0/dat[36]} {zcash_fpga_top/control_top/debug_if0/dat[37]} {zcash_fpga_top/control_top/debug_if0/dat[38]} {zcash_fpga_top/control_top/debug_if0/dat[39]} {zcash_fpga_top/control_top/debug_if0/dat[40]} {zcash_fpga_top/control_top/debug_if0/dat[41]} {zcash_fpga_top/control_top/debug_if0/dat[42]} {zcash_fpga_top/control_top/debug_if0/dat[43]} {zcash_fpga_top/control_top/debug_if0/dat[44]} {zcash_fpga_top/control_top/debug_if0/dat[45]} {zcash_fpga_top/control_top/debug_if0/dat[46]} {zcash_fpga_top/control_top/debug_if0/dat[47]} {zcash_fpga_top/control_top/debug_if0/dat[48]} {zcash_fpga_top/control_top/debug_if0/dat[49]} {zcash_fpga_top/control_top/debug_if0/dat[50]} {zcash_fpga_top/control_top/debug_if0/dat[51]} {zcash_fpga_top/control_top/debug_if0/dat[52]} {zcash_fpga_top/control_top/debug_if0/dat[53]} {zcash_fpga_top/control_top/debug_if0/dat[54]} {zcash_fpga_top/control_top/debug_if0/dat[55]} {zcash_fpga_top/control_top/debug_if0/dat[56]} {zcash_fpga_top/control_top/debug_if0/dat[57]} {zcash_fpga_top/control_top/debug_if0/dat[58]} {zcash_fpga_top/control_top/debug_if0/dat[59]} {zcash_fpga_top/control_top/debug_if0/dat[60]} {zcash_fpga_top/control_top/debug_if0/dat[61]} {zcash_fpga_top/control_top/debug_if0/dat[62]} {zcash_fpga_top/control_top/debug_if0/dat[63]}]] +connect_debug_port u_ila_1/probe4 [get_nets [list zcash_fpga_top/control_top/debug_if0/ctl]] +connect_debug_port u_ila_1/probe5 [get_nets [list zcash_fpga_top/control_top/debug_if1/ctl]] +connect_debug_port u_ila_1/probe6 [get_nets [list zcash_fpga_top/control_top/debug_if1/eop]] +connect_debug_port u_ila_1/probe7 [get_nets [list zcash_fpga_top/control_top/debug_if0/eop]] +connect_debug_port u_ila_1/probe8 [get_nets [list zcash_fpga_top/control_top/debug_if0/err]] +connect_debug_port u_ila_1/probe9 [get_nets [list zcash_fpga_top/control_top/debug_if1/err]] +connect_debug_port u_ila_1/probe10 [get_nets [list zcash_fpga_top/control_top/debug_if0/rdy]] +connect_debug_port u_ila_1/probe11 [get_nets [list zcash_fpga_top/control_top/debug_if1/rdy]] +connect_debug_port u_ila_1/probe12 [get_nets [list zcash_fpga_top/control_top/debug_if1/sop]] +connect_debug_port u_ila_1/probe13 [get_nets [list zcash_fpga_top/control_top/debug_if0/sop]] +connect_debug_port u_ila_1/probe14 [get_nets [list zcash_fpga_top/control_top/debug_if0/val]] +connect_debug_port u_ila_1/probe15 [get_nets [list zcash_fpga_top/control_top/debug_if1/val]] + + +connect_debug_port u_ila_1/probe0 [get_nets [list {zcash_fpga_top/secp256k1_top/debug_if_rx/mod[0]} {zcash_fpga_top/secp256k1_top/debug_if_rx/mod[1]} {zcash_fpga_top/secp256k1_top/debug_if_rx/mod[2]}]] +connect_debug_port u_ila_1/probe1 [get_nets [list {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[0]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[1]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[2]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[3]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[4]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[5]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[6]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[7]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[8]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[9]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[10]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[11]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[12]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[13]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[14]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[15]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[16]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[17]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[18]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[19]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[20]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[21]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[22]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[23]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[24]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[25]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[26]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[27]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[28]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[29]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[30]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[31]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[32]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[33]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[34]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[35]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[36]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[37]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[38]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[39]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[40]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[41]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[42]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[43]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[44]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[45]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[46]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[47]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[48]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[49]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[50]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[51]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[52]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[53]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[54]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[55]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[56]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[57]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[58]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[59]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[60]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[61]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[62]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[63]}]] +connect_debug_port u_ila_1/probe2 [get_nets [list {zcash_fpga_top/secp256k1_top/debug_if_tx/mod[0]} {zcash_fpga_top/secp256k1_top/debug_if_tx/mod[1]} {zcash_fpga_top/secp256k1_top/debug_if_tx/mod[2]}]] +connect_debug_port u_ila_1/probe3 [get_nets [list {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[0]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[1]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[2]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[3]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[4]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[5]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[6]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[7]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[8]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[9]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[10]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[11]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[12]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[13]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[14]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[15]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[16]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[17]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[18]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[19]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[20]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[21]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[22]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[23]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[24]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[25]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[26]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[27]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[28]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[29]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[30]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[31]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[32]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[33]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[34]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[35]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[36]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[37]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[38]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[39]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[40]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[41]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[42]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[43]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[44]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[45]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[46]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[47]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[48]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[49]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[50]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[51]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[52]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[53]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[54]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[55]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[56]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[57]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[58]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[59]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[60]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[61]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[62]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[63]}]] +connect_debug_port u_ila_1/probe11 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_rx/ctl]] +connect_debug_port u_ila_1/probe12 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_tx/ctl]] +connect_debug_port u_ila_1/probe13 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_rx/eop]] +connect_debug_port u_ila_1/probe15 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_tx/eop]] +connect_debug_port u_ila_1/probe18 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_rx/err]] +connect_debug_port u_ila_1/probe19 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_tx/err]] +connect_debug_port u_ila_1/probe23 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_rx/rdy]] +connect_debug_port u_ila_1/probe24 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_tx/rdy]] +connect_debug_port u_ila_1/probe25 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_rx/sop]] +connect_debug_port u_ila_1/probe27 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_tx/sop]] +connect_debug_port u_ila_1/probe30 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_tx/val]] +connect_debug_port u_ila_1/probe31 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_rx/val]] \ No newline at end of file From a0769dd985ef7c36d40c96542cd849aa06936d60 Mon Sep 17 00:00:00 2001 From: bsdevlin Date: Wed, 10 Apr 2019 14:52:11 -0400 Subject: [PATCH 2/2] Updates to help with timing --- ip_cores/util/src/rtl/barret_mod.sv | 7 ++++++- zcash_fpga/src/rtl/secp256k1/secp256k1_mod.sv | 11 +++++------ 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/ip_cores/util/src/rtl/barret_mod.sv b/ip_cores/util/src/rtl/barret_mod.sv index 26d545e..bd745db 100644 --- a/ip_cores/util/src/rtl/barret_mod.sv +++ b/ip_cores/util/src/rtl/barret_mod.sv @@ -44,6 +44,7 @@ module barret_mod #( localparam MAX_IN_BITS = 2*K; localparam [MAX_IN_BITS:0] U = (1 << (2*K)) / P; localparam [MAX_IN_BITS-1:0] P_ = P; +logic [2:0][CTL_BITS-1:0] ctl_r; if_axi_stream #(.DAT_BITS(2*(OUT_BITS+2))) mult_in_if(i_clk); if_axi_stream #(.DAT_BITS(2*(OUT_BITS+2))) mult_out_if(i_clk); @@ -68,6 +69,7 @@ always_ff @ (posedge i_clk) begin mult_in_if.reset_source(); mult_out_if.rdy <= 1; o_ctl <= 0; + ctl_r <= 0; end else begin mult_out_if.rdy <= 1; case (state) @@ -79,7 +81,7 @@ always_ff @ (posedge i_clk) begin o_rdy <= 0; state <= WAIT_MULT; mult_in_if.val <= 1; - o_ctl <= i_ctl; + ctl_r[0] <= i_ctl; mult_in_if.dat[0 +: OUT_BITS+1] <= i_dat >> (K-1); mult_in_if.dat[OUT_BITS+1 +: OUT_BITS+1] <= U; prev_state <= S0; @@ -89,6 +91,7 @@ always_ff @ (posedge i_clk) begin {S0}: begin c3 <= c2 >> (K + 1); state <= S1; + ctl_r[1] <= ctl_r[0]; end {S1}: begin mult_in_if.val <= 1; @@ -96,6 +99,7 @@ always_ff @ (posedge i_clk) begin mult_in_if.dat[OUT_BITS+1 +: OUT_BITS+1] <= P; state <= WAIT_MULT; prev_state <= S2; + ctl_r[2] <= ctl_r[1]; end {S2}: begin if (c4 >= P_) begin @@ -104,6 +108,7 @@ always_ff @ (posedge i_clk) begin state <= FINISHED; o_dat <= c4; o_val <= 1; + o_ctl <= ctl_r[2]; end end {FINISHED}: begin diff --git a/zcash_fpga/src/rtl/secp256k1/secp256k1_mod.sv b/zcash_fpga/src/rtl/secp256k1/secp256k1_mod.sv index c9c6f51..8c2bee7 100644 --- a/zcash_fpga/src/rtl/secp256k1/secp256k1_mod.sv +++ b/zcash_fpga/src/rtl/secp256k1/secp256k1_mod.sv @@ -55,7 +55,7 @@ generate c = (1 << 32) + (1 << 9) + (1 << 8) + (1 << 7) + (1 << 6) + (1 << 4) + 1; end always_ff @ (posedge i_clk) begin - if (~o_val || (o_val && i_rdy)) begin + if (~o_val || (i_rdy && o_val)) begin res0 <= i_dat[511:256]*c + i_dat[255:0]; res1 <= res0[511:256]*c + res0[255:0]; end @@ -67,7 +67,7 @@ generate res1_ = (res0[511:256] << 32) + (res0[511:256] << 9) + (res0[511:256] << 8) + (res0[511:256] << 7) + (res0[511:256] << 6) + (res0[511:256] << 4) + res0[511:256]+ res0[255:0]; end always_ff @ (posedge i_clk) begin - if (~o_val || (o_val && i_rdy)) begin + if (~o_val || (i_rdy && o_val)) begin res0 <= res0_; res1 <= res1_; end @@ -85,16 +85,15 @@ always_ff @ (posedge i_clk) begin ctl <= 0; o_err <= 0; end else begin - //o_val <= 0; - if (~o_val || (o_val && i_rdy)) begin + if (~o_val || (i_rdy && o_val)) begin val <= val << 1; ctl <= {ctl, i_ctl}; err <= err << 1; val[0] <= i_val && o_rdy; err[0] <= i_err; + o_dat <= res1[255:0]; - o_dat <= res1 >= p_eq ? res1 - p_eq : res1; - o_err <= err[1] || (res1 >= 2*p_eq); + o_err <= err[1] || res1 >= p_eq; o_val <= val[1]; o_ctl <= ctl[1]; end