diff --git a/zcash_fpga/src/rtl/bls12_381/bls12_381_axi_bridge.sv b/zcash_fpga/src/rtl/bls12_381/bls12_381_axi_bridge.sv
index 4b41ff9..8518b98 100644
--- a/zcash_fpga/src/rtl/bls12_381/bls12_381_axi_bridge.sv
+++ b/zcash_fpga/src/rtl/bls12_381/bls12_381_axi_bridge.sv
@@ -27,7 +27,9 @@ module bls12_381_axi_bridge (
   input [31:0] i_curr_inst_pt,
   input [31:0] i_last_inst_cnt,
   output logic [31:0] o_new_inst_pt,
-  output logic        o_new_inst_pt_val
+  output logic        o_new_inst_pt_val,
+  output logic        o_reset_inst_ram,
+  output logic        o_reset_data_ram
 );
 
 import bls12_381_pkg::*;
@@ -57,8 +59,12 @@ always_ff @ (posedge i_clk) begin
     wr_addr <= 0;
     o_new_inst_pt_val <= 0;
     o_new_inst_pt <= 0;
+    o_reset_inst_ram <= 0;
+    o_reset_data_ram <= 0;
   end else begin
 
+    o_reset_inst_ram <= 0;
+    o_reset_data_ram <= 0;
     o_new_inst_pt_val <= 0;
 
     data_ram_read <= data_ram_read << 1;
@@ -138,21 +144,24 @@ always_ff @ (posedge i_clk) begin
             o_new_inst_pt_val <= 1;
             o_new_inst_pt <= axi_lite_if.wdata;
           end
+          32'h0: begin
+            o_reset_inst_ram <= axi_lite_if.wdata[0]; // This will reset the instruction ram
+            o_reset_data_ram <= axi_lite_if.wdata[1]; // This will reset the data ram
+          end
         endcase
       end else
-      // TODO change this to be atomic writes
       if (wr_addr < DATA_AXIL_START) begin
         // Instruction memory
-        inst_ram_if.we <= 0;
-        inst_ram_if.d <= axi_lite_if.wdata << (((wr_addr - INST_AXIL_START) % INST_RAM_ALIGN_BYTE)/INST_RAM_USR_WIDTH)*32;
-        inst_ram_if.we[4*((wr_addr - INST_AXIL_START) % INST_RAM_ALIGN_BYTE)/INST_RAM_USR_WIDTH +: 4] <= {4{1'd1}};
+        inst_ram_if.d[(((wr_addr - INST_AXIL_START) % INST_RAM_ALIGN_BYTE)/INST_RAM_USR_WIDTH)*32 +: 32] <= axi_lite_if.wdata;
         inst_ram_if.a <= (wr_addr - INST_AXIL_START) / INST_RAM_ALIGN_BYTE;
+        // Only write on the last work to make this atomic
+        if ((wr_addr - INST_AXIL_START) % 8 == 4) inst_ram_if.we <= 1;
       end else begin
         // Data memory
-        data_ram_if.we <= 0;
-        data_ram_if.d <= axi_lite_if.wdata << (((wr_addr - DATA_AXIL_START) % DATA_RAM_ALIGN_BYTE)/DATA_RAM_USR_WIDTH)*32;
-        data_ram_if.we[4*((wr_addr - DATA_AXIL_START) % DATA_RAM_ALIGN_BYTE)/DATA_RAM_USR_WIDTH +: 4] <= {4{1'd1}};
+        data_ram_if.d[(((wr_addr - DATA_AXIL_START) % DATA_RAM_ALIGN_BYTE)/DATA_RAM_USR_WIDTH)*32 +: 32] <= axi_lite_if.wdata;
         data_ram_if.a <= (wr_addr - DATA_AXIL_START) / DATA_RAM_ALIGN_BYTE;
+        // Only write on the last work to make this atomic
+        if ((wr_addr - DATA_AXIL_START) % 64 == 44) data_ram_if.we <= 1;
       end
     end
   end
diff --git a/zcash_fpga/src/rtl/bls12_381/bls12_381_top.sv b/zcash_fpga/src/rtl/bls12_381/bls12_381_top.sv
index f677bd6..84fc7e4 100644
--- a/zcash_fpga/src/rtl/bls12_381/bls12_381_top.sv
+++ b/zcash_fpga/src/rtl/bls12_381/bls12_381_top.sv
@@ -39,17 +39,18 @@ bls12_381_interrupt_rpl_t interrupt_rpl;
 enum {WAIT_FIFO, SEND_HDR, SEND_DATA} interrupt_state;
 logic [7:0] interrupt_hdr_byt;
 
-// Instruction RAM
-logic [READ_CYCLE:0] inst_ram_read;
-logic [READ_CYCLE:0] data_ram_read;
 
-if_ram #(.RAM_WIDTH(bls12_381_pkg::INST_RAM_WIDTH), .RAM_DEPTH(bls12_381_pkg::INST_RAM_DEPTH), .BYT_EN(7)) inst_ram_sys_if(.i_clk(i_clk), .i_rst(i_rst));
-if_ram #(.RAM_WIDTH(bls12_381_pkg::INST_RAM_WIDTH), .RAM_DEPTH(bls12_381_pkg::INST_RAM_DEPTH), .BYT_EN(7)) inst_ram_usr_if(.i_clk(i_clk), .i_rst(i_rst));
+logic [READ_CYCLE:0] inst_ram_read, data_ram_read;
+logic reset_inst_ram, reset_data_ram;
+
+// Instruction RAM
+if_ram #(.RAM_WIDTH(bls12_381_pkg::INST_RAM_WIDTH), .RAM_DEPTH(bls12_381_pkg::INST_RAM_DEPTH)) inst_ram_sys_if(.i_clk(i_clk), .i_rst(i_rst || reset_inst_ram));
+if_ram #(.RAM_WIDTH(bls12_381_pkg::INST_RAM_WIDTH), .RAM_DEPTH(bls12_381_pkg::INST_RAM_DEPTH)) inst_ram_usr_if(.i_clk(i_clk), .i_rst(i_rst || reset_inst_ram));
 inst_t curr_inst;
 
 // Data RAM
-if_ram #(.RAM_WIDTH(bls12_381_pkg::DATA_RAM_WIDTH), .RAM_DEPTH(bls12_381_pkg::DATA_RAM_DEPTH), .BYT_EN(48)) data_ram_sys_if(.i_clk(i_clk), .i_rst(i_rst));
-if_ram #(.RAM_WIDTH(bls12_381_pkg::DATA_RAM_WIDTH), .RAM_DEPTH(bls12_381_pkg::DATA_RAM_DEPTH), .BYT_EN(48)) data_ram_usr_if(.i_clk(i_clk), .i_rst(i_rst));
+if_ram #(.RAM_WIDTH(bls12_381_pkg::DATA_RAM_WIDTH), .RAM_DEPTH(bls12_381_pkg::DATA_RAM_DEPTH)) data_ram_sys_if(.i_clk(i_clk), .i_rst(i_rst || reset_data_ram));
+if_ram #(.RAM_WIDTH(bls12_381_pkg::DATA_RAM_WIDTH), .RAM_DEPTH(bls12_381_pkg::DATA_RAM_DEPTH)) data_ram_usr_if(.i_clk(i_clk), .i_rst(i_rst || reset_data_ram));
 data_t curr_data, new_data;
 
 // Loading the fifo with slots and outputting an interrupt
@@ -191,7 +192,9 @@ bls12_381_axi_bridge bls12_381_axi_bridge (
   .i_curr_inst_pt     ( curr_inst_pt    ),
   .i_last_inst_cnt    ( last_inst_cnt   ),
   .o_new_inst_pt      ( new_inst_pt     ),
-  .o_new_inst_pt_val  ( new_inst_pt_val )
+  .o_new_inst_pt_val  ( new_inst_pt_val ),
+  .o_reset_inst_ram   ( reset_inst_ram  ),
+  .o_reset_data_ram   ( reset_data_ram  )
 );
 
 always_comb begin
@@ -410,7 +413,7 @@ task task_copy_reg();
   if (data_ram_read[READ_CYCLE]) begin
     data_ram_sys_if.a <=  curr_inst.b;
     new_data <= curr_data;
-    data_ram_sys_if.we <= -1;
+    data_ram_sys_if.we <= 1;
   end
 endtask
 
@@ -434,7 +437,7 @@ task task_scalar_inv();
         data_ram_sys_if.a <= curr_inst.b;
         new_data.pt <= curr_data.pt;
         new_data.dat <= binv_o_if.dat;
-        data_ram_sys_if.we <= -1;
+        data_ram_sys_if.we <= 1;
         cnt <= cnt + 1;
       end
     end
@@ -481,7 +484,7 @@ task task_point_mult();
       if (fp2_pt_mult_out_if.val) begin
          new_data.pt <= FP_JB;
          new_data.dat <= fp2_pt_mult_out_if.dat >> ((cnt-2)*2*DAT_BITS);
-         data_ram_sys_if.we <= -1;
+         data_ram_sys_if.we <= 1;
          data_ram_sys_if.a <= data_ram_sys_if.a + 1;
          cnt <= cnt + 1;
          if (cnt == 4) begin
@@ -520,7 +523,7 @@ task task_fp_fpoint_mult();
       if (fp2_pt_mult_out_if.val) begin
          new_data.pt <= FP_JB;
          new_data.dat <= fp2_pt_mult_out_if.dat >> ((cnt-2)*2*DAT_BITS);
-         data_ram_sys_if.we <= -1;
+         data_ram_sys_if.we <= 1;
          if (cnt > 2) data_ram_sys_if.a <= data_ram_sys_if.a + 1;
          cnt <= cnt + 1;
          if (cnt == 4) begin
@@ -557,7 +560,7 @@ task task_fp2_fpoint_mult();
       if (fp2_pt_mult_out_if.val) begin
          new_data.pt <= FP2_JB;
          new_data.dat <= fp2_pt_mult_out_if.dat >> ((cnt-2)*DAT_BITS);
-         data_ram_sys_if.we <= -1;
+         data_ram_sys_if.we <= 1;
          if (cnt > 2) data_ram_sys_if.a <= data_ram_sys_if.a + 1;
          cnt <= cnt + 1;
          if (cnt == 7) begin
diff --git a/zcash_fpga/src/tb/bls12_381_top_tb.sv b/zcash_fpga/src/tb/bls12_381_top_tb.sv
index b3f65c3..842f562 100644
--- a/zcash_fpga/src/tb/bls12_381_top_tb.sv
+++ b/zcash_fpga/src/tb/bls12_381_top_tb.sv
@@ -52,7 +52,7 @@ bls12_381_top bls12_381_top (
 );
 
 
-task test_fp_point_mult();
+task test_fp_fpoint_mult();
 begin
   integer signed get_len;
   logic [common_pkg::MAX_SIM_BYTS*8-1:0] get_dat;
@@ -67,7 +67,7 @@ begin
   failed = 0;
   in_k = 381'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa;
   exp_p =  point_mult(in_k, g_point);
-  $display("Running test_fp_point_mult...");
+  $display("Running test_fp_fpoint_mult...");
 
   axi_lite_if.peek(.addr(0), .data(rdata));
   assert(rdata == INST_AXIL_START) else $fatal("ERROR: AXI lite register returned wrong value");
@@ -127,13 +127,13 @@ begin
   $display("INFO: Last cycle count was %d", rdata);
 
   if(failed)
-   $fatal(1, "ERROR: test_fp_point_mult FAILED");
+   $fatal(1, "ERROR: test_fp_fpoint_mult FAILED");
   else
-   $display("INFO: test_fp_point_mult PASSED");
+   $display("INFO: test_fp_fpoint_mult PASSED");
 end
 endtask;
 
-task test_fp2_point_mult();
+task test_fp2_fpoint_mult();
 begin
   integer signed get_len;
   logic [common_pkg::MAX_SIM_BYTS*8-1:0] get_dat;
@@ -148,7 +148,7 @@ begin
   failed = 0;
   in_k = 381'h33333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333;
   exp_p =  fp2_point_mult(in_k, g2_point);
-  $display("Running test_fp2_point_mult...");
+  $display("Running test_fp2_fpoint_mult...");
 
   // See what current instruction pointer is
   axi_lite_if.peek(.addr(32'h10), .data(rdata));
@@ -200,21 +200,21 @@ begin
 
   // See what current instruction pointer is
   axi_lite_if.peek(.addr(32'h10), .data(rdata));
-  
+
   $display("INFO: Current instruction pointer is 0x%x, setting to 0 and writing NULL instruction", rdata);
-  
+
   inst = '{code:NOOP_WAIT, a:16'd0, b:16'h0, c:16'd0};
   axi_lite_if.put_data_multiple(.data(inst), .addr(INST_AXIL_START), .len(8));
- 
+
   axi_lite_if.poke(.addr(32'h10), .data(32'd0));
   repeat(10) @(posedge clk);
   axi_lite_if.peek(.addr(32'h10), .data(rdata));
   assert(rdata == 32'd0) else $fatal(1, "ERROR: could not set instruction pointer");
 
   if(failed)
-   $fatal(1, "ERROR: test_fp2_point_mult FAILED");
+   $fatal(1, "ERROR: test_fp2_fpoint_mult FAILED");
   else
-   $display("INFO: test_fp2_point_mult PASSED");
+   $display("INFO: test_fp2_fpoint_mult PASSED");
 end
 endtask;
 
@@ -227,8 +227,9 @@ initial begin
        !bls12_381_top.data_uram_reset.reset_done)
     @(posedge clk);
 
-  test_fp_point_mult();
-  test_fp2_point_mult();
+  test_fp_fpoint_mult();
+  test_fp2_fpoint_mult();
+
 
   #1us $finish();
 end