bsdevlin
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b94b2a7c5d
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Added 256 bit multiplier and testbenches
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2019-03-18 16:05:55 -04:00 |
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bsdevlin
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e1705a1d5b
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Update to control block and test bench
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2019-03-17 10:49:16 -04:00 |
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bsdevlin
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571bfb2dc0
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Updates to top control, secp256k1 core.
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2019-03-17 00:31:12 -04:00 |
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bsdevlin
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051f3e68b5
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Update to top level with interface and test bench
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2019-03-12 23:48:28 -04:00 |
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bsdevlin
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069e52c84b
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Top level test bench
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2019-03-12 15:10:42 -04:00 |
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bsdevlin
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56ad30d051
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Updates to common IP
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2019-03-12 15:10:18 -04:00 |
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bsdevlin
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2bee4f7513
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Updates to top level
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2019-03-12 15:09:53 -04:00 |
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bsdevlin
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86a8db4df3
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Large update to new architecture and board files
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2019-03-11 15:21:45 -04:00 |
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bsdevlin
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8128e982ee
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Large update for new architecture
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2019-03-11 15:21:06 -04:00 |
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bsdevlin
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c38f9cdb18
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Delete blank line
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2019-02-28 19:06:49 -05:00 |
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bsdevlin
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632f4397d0
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Bugfix for signals not cleared properly
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2019-02-28 19:04:11 -05:00 |
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bsdevlin
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e08b46f30d
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Bugfix for SHA256 core
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2019-02-28 18:33:03 -05:00 |
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bsdevlin
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2251338f1d
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Update for difficulty check
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2019-02-28 18:32:48 -05:00 |
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bsdevlin
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e8b6d4b19c
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Updates to SHA256 core and a difficulty module
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2019-02-28 13:07:24 -05:00 |
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bsdevlin
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547a557a14
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SHA256 core
First cut of SHA256 core
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2019-02-27 19:45:00 -05:00 |
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bsdevlin
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1abb875397
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Fix bug with fnd.
Fix bug with fnd signal not going high when adding hash entries
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2019-02-27 19:44:40 -05:00 |
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bsdevlin
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e94df14cda
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Added test for checking errors.
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2019-02-26 17:35:47 -05:00 |
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bsdevlin
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a10bb8df71
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Verilog code for order check
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2019-02-26 16:58:19 -05:00 |
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bsdevlin
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73c20415f8
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Added equihash check for index ordering
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2019-02-26 16:57:18 -05:00 |
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bsdevlin
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39892b7732
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Added code for hash map and checking for duplicated index in the
equihash solution.
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2019-02-25 21:41:50 -05:00 |
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bsdevlin
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3cc1446afc
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Updated equihash verifier code, is able to verify XOR == 0 and order of
0 bits increasing from left.
Need to check for unique index and certain ordering.
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2019-02-22 15:55:25 -05:00 |
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bsdevlin
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9d7cdac233
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Added test for personalization string
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2019-02-22 15:54:04 -05:00 |
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bsdevlin
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149074bde6
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Update files for Equihash solution checking
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2019-02-21 16:15:15 -05:00 |
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bsdevlin
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8b853a7159
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Updates to verfi module
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2019-02-21 06:44:42 -05:00 |
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bsdevlin
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c8f1c9223f
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Updates to testbench to fix bugs.
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2019-02-20 17:16:13 -05:00 |
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bsdevlin
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7140da7da0
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Rename binary block file
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2019-02-20 17:15:45 -05:00 |
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bsdevlin
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033d31de09
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Updating files for equihash verifier
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2019-02-20 13:02:09 -05:00 |
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bsdevlin
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cb39d92778
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Update blake2b blocks and testbench.
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2019-02-20 09:25:26 -05:00 |
bsdevlin
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210f6837dc
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Add memory templates for Xilinx
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2019-02-20 21:15:34 +08:00 |
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bsdevlin
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4cc2399d0f
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Updated Blake2b pipelined version so now it is passing the testbench.
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2019-02-19 20:59:37 -05:00 |
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bsdevlin
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523c1c7388
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Updates to FIFO and bug fix for unrolled pipe version of Blake2b
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2019-02-19 19:28:13 -05:00 |
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bsdevlin
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05f5913fce
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Updates to files and testbenches for the equihash verif block.
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2019-02-19 15:45:13 -05:00 |
bsdevlin
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4b9ff85954
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Merge pull request #3 from bsdevlin/blake2b
Blake2b
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2019-02-19 09:39:26 -05:00 |
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bsdevlin
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ada37ef413
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Update fold name to verif
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2019-02-19 09:36:28 -05:00 |
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bsdevlin
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e437c8bd74
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Update readme file
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2019-02-19 09:32:24 -05:00 |
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bsdevlin
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ca60668859
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Parsing files
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2019-02-19 09:31:46 -05:00 |
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bsdevlin
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3244deeaac
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Updates to naming of verif project, and extra blocks for testbench,
example block file.
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2019-02-19 09:31:31 -05:00 |
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bsdevlin
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0d84ffd424
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Add IP for an AXI interface fifo. Add the blake2b_pipe which is a high
performance version of blake2b pipeline unrolled.
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2019-02-16 01:23:49 -05:00 |
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bsdevlin
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ab3e37782e
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Update license
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2019-02-15 01:58:34 -05:00 |
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bsdevlin
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c8f0740129
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Merge pull request #2 from bsdevlin/add-license-2
Create LICENSE
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2019-02-15 01:24:56 -05:00 |
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bsdevlin
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bd9677ebd6
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Create LICENSE
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2019-02-15 01:24:46 -05:00 |
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bsdevlin
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77c0b8bace
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Delete LICENSE
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2019-02-15 01:23:09 -05:00 |
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bsdevlin
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f6c0c33d40
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Merge pull request #1 from bsdevlin/add-license-1
Create LICENSE
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2019-02-14 08:09:56 -05:00 |
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bsdevlin
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49a9eee523
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Create LICENSE
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2019-02-14 08:09:42 -05:00 |
bsdevlin
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66aad005df
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Add script for generating project when synthesizing in Vivado
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2019-02-13 17:14:15 -05:00 |
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bsdevlin
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70e1598c45
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Bug updates, now working correctly for all test cases
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2019-02-13 16:43:19 -05:00 |
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bsdevlin
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18c08450df
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Rename modules in files to blake2b
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2019-02-13 15:27:13 -05:00 |
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bsdevlin
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e86828b771
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Correct name from blake2 -> blake2b
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2019-02-13 15:24:46 -05:00 |
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bsdevlin
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1992538306
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Update to blake2 core to work correctly with messages larger than 128
bytes, added testbench for checking this.
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2019-02-13 15:23:22 -05:00 |
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bsdevlin
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d391cbc992
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Updates to testbench to include helper functions,
updated synthesis file to meet timing (200MHz)
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2019-02-13 10:53:19 -05:00 |