317 lines
11 KiB
Systemverilog
317 lines
11 KiB
Systemverilog
// Amazon FPGA Hardware Development Kit
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//
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// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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//
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// Licensed under the Amazon Software License (the "License"). You may not use
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// this file except in compliance with the License. A copy of the License is
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// located at
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//
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// http://aws.amazon.com/asl/
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//
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// or in the "license" file accompanying this file. This file is distributed on
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// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
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// implied. See the License for the specific language governing permissions and
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// limitations under the License.
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module cl_zcash
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(
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`include "cl_ports.vh" // Fixed port definition
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);
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`include "cl_common_defines.vh" // CL Defines for all examples
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`include "cl_id_defines.vh" // Defines for ID0 and ID1 (PCI ID's)
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`include "cl_zcash_defines.vh" // CL Defines for cl_hello_world
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localparam USE_AXI4 = "NO";
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localparam USE_ILA = "NO";
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logic rst_main_n_sync;
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logic clk_if, clk_100, clk_200, clk_300;
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logic rst_if, rst_100, rst_200, rst_300;
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if_axi_stream #(.DAT_BYTS(8), .CTL_BITS(1)) zcash_if_rx (clk_if);
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if_axi_stream #(.DAT_BYTS(8), .CTL_BITS(1)) zcash_if_tx (clk_if);
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if_axi_lite #(.A_BITS(32)) zcash_axi_lite_if (clk_if);
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if_axi_lite #(.A_BITS(32)) rx_axi_lite_if (clk_if);
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if_axi4 #(.A_WIDTH(64), .D_WIDTH(512), .ID_WIDTH(6)) rx_axi4_if (clk_if);
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//--------------------------------------------0
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// Start with Tie-Off of Unused Interfaces
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//---------------------------------------------
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// the developer should use the next set of `include
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// to properly tie-off any unused interface
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// The list is put in the top of the module
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// to avoid cases where developer may forget to
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// remove it from the end of the file
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`include "unused_flr_template.inc"
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`include "unused_ddr_a_b_d_template.inc"
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`include "unused_ddr_c_template.inc"
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`include "unused_pcim_template.inc"
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if (USE_AXI4 == "NO")
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`include "unused_dma_pcis_template.inc"
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`include "unused_cl_sda_template.inc"
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`include "unused_sh_bar1_template.inc"
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`include "unused_apppf_irq_template.inc"
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//-------------------------------------------------
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// ID Values (cl_id_defines.vh)
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//-------------------------------------------------
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assign cl_sh_id0[31:0] = `CL_SH_ID0;
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assign cl_sh_id1[31:0] = `CL_SH_ID1;
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//-------------------------------------------------
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// Reset Synchronization
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//-------------------------------------------------
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logic pre_sync_rst_n;
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always_ff @(negedge rst_main_n or posedge clk_main_a0)
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if (!rst_main_n)
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begin
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pre_sync_rst_n <= 0;
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rst_main_n_sync <= 0;
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end
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else
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begin
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pre_sync_rst_n <= 1;
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rst_main_n_sync <= pre_sync_rst_n;
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end
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//-------------------------------------------------
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// PCIe OCL AXI-L (SH to CL) Timing Flops
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//-------------------------------------------------
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// Write address
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logic sh_ocl_awvalid_q;
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logic [31:0] sh_ocl_awaddr_q;
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logic ocl_sh_awready_q;
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// Write data
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logic sh_ocl_wvalid_q;
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logic [31:0] sh_ocl_wdata_q;
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logic [ 3:0] sh_ocl_wstrb_q;
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logic ocl_sh_wready_q;
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// Write response
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logic ocl_sh_bvalid_q;
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logic [ 1:0] ocl_sh_bresp_q;
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logic sh_ocl_bready_q;
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// Read address
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logic sh_ocl_arvalid_q;
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logic [31:0] sh_ocl_araddr_q;
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logic ocl_sh_arready_q;
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// Read data/response
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logic ocl_sh_rvalid_q;
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logic [31:0] ocl_sh_rdata_q;
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logic [ 1:0] ocl_sh_rresp_q;
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logic sh_ocl_rready_q;
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axi_register_slice_light AXIL_OCL_REG_SLC (
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.aclk (clk_main_a0),
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.aresetn (rst_main_n_sync),
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.s_axi_awaddr (sh_ocl_awaddr),
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.s_axi_awprot (2'h0),
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.s_axi_awvalid (sh_ocl_awvalid),
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.s_axi_awready (ocl_sh_awready),
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.s_axi_wdata (sh_ocl_wdata),
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.s_axi_wstrb (sh_ocl_wstrb),
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.s_axi_wvalid (sh_ocl_wvalid),
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.s_axi_wready (ocl_sh_wready),
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.s_axi_bresp (ocl_sh_bresp),
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.s_axi_bvalid (ocl_sh_bvalid),
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.s_axi_bready (sh_ocl_bready),
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.s_axi_araddr (sh_ocl_araddr),
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.s_axi_arvalid (sh_ocl_arvalid),
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.s_axi_arready (ocl_sh_arready),
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.s_axi_rdata (ocl_sh_rdata),
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.s_axi_rresp (ocl_sh_rresp),
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.s_axi_rvalid (ocl_sh_rvalid),
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.s_axi_rready (sh_ocl_rready),
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.m_axi_awaddr (rx_axi_lite_if.awaddr),
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.m_axi_awprot (),
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.m_axi_awvalid (rx_axi_lite_if.awvalid),
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.m_axi_awready (rx_axi_lite_if.awready),
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.m_axi_wdata (rx_axi_lite_if.wdata),
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.m_axi_wstrb (rx_axi_lite_if.wstrb),
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.m_axi_wvalid (rx_axi_lite_if.wvalid),
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.m_axi_wready (rx_axi_lite_if.wready),
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.m_axi_bresp (rx_axi_lite_if.bresp),
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.m_axi_bvalid (rx_axi_lite_if.bvalid),
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.m_axi_bready (rx_axi_lite_if.bready),
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.m_axi_araddr (rx_axi_lite_if.araddr),
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.m_axi_arvalid (rx_axi_lite_if.arvalid),
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.m_axi_arready (rx_axi_lite_if.arready),
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.m_axi_rdata (rx_axi_lite_if.rdata),
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.m_axi_rresp (rx_axi_lite_if.rresp),
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.m_axi_rvalid (rx_axi_lite_if.rvalid),
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.m_axi_rready (rx_axi_lite_if.rready)
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);
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always_comb begin
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clk_if = clk_main_a0;
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clk_100 = clk_main_a0; // 125MHz
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clk_200 = clk_main_a0; // 187MHz
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clk_300 = clk_extra_b0; // 300MHz
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end
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always_ff @(posedge clk_if) rst_if <= !rst_main_n;
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always_ff @(posedge clk_100) rst_100 <= !rst_main_n;
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always_ff @(posedge clk_200) rst_200 <= !rst_main_n;
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always_ff @(posedge clk_300) rst_300 <= !rst_main_n;
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generate
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if (USE_AXI4 == "YES") begin: AXI4_GEN
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always_comb begin
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rx_axi4_if.awid = sh_cl_dma_pcis_awid;
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rx_axi4_if.awaddr = sh_cl_dma_pcis_awaddr;
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rx_axi4_if.awlen = sh_cl_dma_pcis_awlen;
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rx_axi4_if.awsize = sh_cl_dma_pcis_awsize;
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rx_axi4_if.awvalid = sh_cl_dma_pcis_awvalid;
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cl_sh_dma_pcis_awready = rx_axi4_if.awready;
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rx_axi4_if.wdata = sh_cl_dma_pcis_wdata;
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rx_axi4_if.wstrb = sh_cl_dma_pcis_wstrb;
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rx_axi4_if.wlast = sh_cl_dma_pcis_wlast;
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rx_axi4_if.wvalid = sh_cl_dma_pcis_wvalid;
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cl_sh_dma_pcis_wready = rx_axi4_if.wready;
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cl_sh_dma_pcis_bid = rx_axi4_if.bid;
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cl_sh_dma_pcis_bresp = rx_axi4_if.bresp;
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cl_sh_dma_pcis_bvalid = rx_axi4_if.bvalid;
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rx_axi4_if.bready = sh_cl_dma_pcis_bready;
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rx_axi4_if.arid = sh_cl_dma_pcis_arid;
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rx_axi4_if.araddr = sh_cl_dma_pcis_araddr;
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rx_axi4_if.arlen = sh_cl_dma_pcis_arlen;
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rx_axi4_if.arsize = sh_cl_dma_pcis_arsize;
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rx_axi4_if.arvalid = sh_cl_dma_pcis_arvalid;
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cl_sh_dma_pcis_arready = rx_axi4_if.arready;
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cl_sh_dma_pcis_rid = rx_axi4_if.rid;
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cl_sh_dma_pcis_rdata = rx_axi4_if.rdata;
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cl_sh_dma_pcis_rresp = rx_axi4_if.rresp;
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cl_sh_dma_pcis_rlast = rx_axi4_if.rlast;
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cl_sh_dma_pcis_rvalid = rx_axi4_if.rvalid;
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rx_axi4_if.rready = sh_cl_dma_pcis_rready;
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end
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end
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endgenerate
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cl_zcash_aws_wrapper #(
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.USE_AXI4 ( USE_AXI4 )
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)
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cl_zcash_aws_wrapper (
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.i_rst ( rst_if ),
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.i_clk ( clk_if ),
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.rx_axi_lite_if ( rx_axi_lite_if ),
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.rx_axi4_if ( rx_axi4_if ),
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.zcash_axi_lite_if ( zcash_axi_lite_if ),
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.rx_zcash_if ( zcash_if_tx ),
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.tx_zcash_if ( zcash_if_rx )
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);
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zcash_fpga_top #(
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.DAT_BYTS ( 8 )
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)
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zcash_fpga_top (
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// Clocks and resets
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.i_clk_100 ( clk_100 ),
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.i_rst_100 ( rst_100 ),
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.i_clk_200 ( clk_200 ),
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.i_rst_200 ( rst_200 ),
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.i_clk_300 ( clk_300 ),
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.i_rst_300 ( rst_300 ),
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.i_clk_if ( clk_if ),
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.i_rst_if ( rst_if ),
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.rx_if ( zcash_if_rx ),
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.tx_if ( zcash_if_tx ),
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.axi_lite_if (zcash_axi_lite_if)
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);
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generate
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if (USE_ILA == "YES") begin: ILA_GEN
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// Integrated Logic Analyzers (ILA)
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ila_0 CL_ILA_0 (
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.clk (clk_main_a0),
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.probe0 (sh_ocl_awvalid_q),
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.probe1 (sh_ocl_awaddr_q ),
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.probe2 (ocl_sh_awready_q),
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.probe3 (sh_ocl_arvalid_q),
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.probe4 (sh_ocl_araddr_q ),
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.probe5 (ocl_sh_arready_q)
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);
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ila_0 CL_ILA_1 (
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.clk (clk_main_a0),
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.probe0 (ocl_sh_bvalid_q),
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.probe1 (sh_cl_glcount0_q),
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.probe2 (sh_ocl_bready_q),
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.probe3 (ocl_sh_rvalid_q),
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.probe4 ({32'b0,ocl_sh_rdata_q[31:0]}),
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.probe5 (sh_ocl_rready_q)
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);
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ila_2 CL_ILA_2 (
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.clk(clk_main_a0),
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.probe0(zcash_fpga_top.bls12_381_top.tx_if.val), // input wire [0:0] probe0
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.probe1(zcash_fpga_top.bls12_381_top.tx_if.sop), // input wire [0:0] probe1
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.probe2(zcash_fpga_top.bls12_381_top.tx_if.eop), // input wire [0:0] probe2
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.probe3(zcash_fpga_top.bls12_381_top.tx_if.rdy), // input wire [0:0] probe3
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.probe4(zcash_fpga_top.bls12_381_top.tx_if.dat), // input wire [63:0] probe4
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.probe5(zcash_fpga_top.bls12_381_top.interrupt_state), // input wire [7:0] probe5
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.probe6(zcash_fpga_top.bls12_381_top.idx_out_if.val), // input wire [0:0] probe6
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.probe7(zcash_fpga_top.bls12_381_top.idx_out_if.sop), // input wire [0:0] probe7
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.probe8(zcash_fpga_top.bls12_381_top.idx_out_if.eop), // input wire [0:0] probe8
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.probe9(zcash_fpga_top.bls12_381_top.idx_out_if.rdy), // input wire [0:0] probe9
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.probe10(zcash_fpga_top.bls12_381_top.idx_out_if.dat), // input wire [18:0] probe10
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.probe11(zcash_fpga_top.bls12_381_top.interrupt_in_if.val), // input wire [0:0] probe11
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.probe12(zcash_fpga_top.bls12_381_top.interrupt_in_if.sop), // input wire [0:0] probe12
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.probe13(zcash_fpga_top.bls12_381_top.interrupt_in_if.eop), // input wire [0:0] probe13
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.probe14(zcash_fpga_top.bls12_381_top.interrupt_in_if.rdy), // input wire [0:0] probe14
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.probe15(zcash_fpga_top.bls12_381_top.interrupt_in_if.dat), // input wire [380:0] probe15
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.probe16(zcash_fpga_top.bls12_381_top.interrupt_out_if.val), // input wire [0:0] probe16
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.probe17(zcash_fpga_top.bls12_381_top.interrupt_out_if.sop), // input wire [0:0] probe17
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.probe18(zcash_fpga_top.bls12_381_top.interrupt_out_if.eop), // input wire [0:0] probe18
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.probe19(zcash_fpga_top.bls12_381_top.interrupt_out_if.rdy), // input wire [0:0] probe19
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.probe20(zcash_fpga_top.bls12_381_top.interrupt_out_if.dat), // input wire [63:0] probe20
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.probe21(zcash_fpga_top.bls12_381_top.curr_inst_pt), // input wire [31:0] probe21
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.probe22(zcash_fpga_top.bls12_381_top.inst_state), // input wire [7:0] probe22
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.probe23(), // input wire [0:0] probe23
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.probe24(), // input wire [0:0] probe24
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.probe25(), // input wire [0:0] probe25
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.probe26(), // input wire [0:0] probe26
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.probe27(), // input wire [0:0] probe27
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.probe28(), // input wire [0:0] probe28
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.probe29(), // input wire [0:0] probe29
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.probe30(), // input wire [0:0] probe30
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.probe31() // input wire [0:0] probe31
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);
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// Debug Bridge
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cl_debug_bridge CL_DEBUG_BRIDGE (
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.clk(clk_main_a0),
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.S_BSCAN_drck(drck),
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.S_BSCAN_shift(shift),
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.S_BSCAN_tdi(tdi),
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.S_BSCAN_update(update),
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.S_BSCAN_sel(sel),
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.S_BSCAN_tdo(tdo),
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.S_BSCAN_tms(tms),
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.S_BSCAN_tck(tck),
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.S_BSCAN_runtest(runtest),
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.S_BSCAN_reset(reset),
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.S_BSCAN_capture(capture),
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.S_BSCAN_bscanid_en(bscanid_en)
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);
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end
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endgenerate
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endmodule
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