submitted v0.1
This commit is contained in:
parent
9228821f8b
commit
7cae5ddffd
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@ -4,6 +4,7 @@
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.vscode/launch.json
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.vscode/ipch
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.vscode/configurationCache.log
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logs/
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# For PCBs designed using KiCad: https://www.kicad.org/
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# Format documentation: https://kicad.org/help/file-formats/
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File diff suppressed because it is too large
Load Diff
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@ -11,7 +11,7 @@
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(via_costs 50)
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(plane_via_costs 5)
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(start_ripup_costs 100)
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(start_pass_no 14898)
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(start_pass_no 19955)
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(layer_rule F.Cu
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(active on)
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(preferred_direction horizontal)
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@ -376,8 +376,6 @@ $EndComp
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Wire Wire Line
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9050 3250 8950 3250
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Connection ~ 8950 3250
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Wire Wire Line
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8950 3250 8800 3250
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$Comp
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L power:+3.3V #PWR0116
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U 1 1 61C5BDCA
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@ -484,30 +482,6 @@ F 3 "~" H 8950 3350 50 0001 C CNN
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1 8950 3350
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-1 0 0 -1
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$EndComp
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Wire Wire Line
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7350 2350 7200 2350
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Wire Wire Line
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7200 2350 7200 3000
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Wire Wire Line
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8800 1150 7850 1150
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Wire Wire Line
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8950 1150 8800 1150
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Connection ~ 8800 1150
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Wire Wire Line
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7200 3000 8800 3000
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Wire Wire Line
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8800 3000 8800 1150
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Wire Wire Line
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7350 4450 7200 4450
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Wire Wire Line
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7200 4450 7200 5100
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Wire Wire Line
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7200 5100 8800 5100
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Wire Wire Line
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8800 5100 8800 3250
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Connection ~ 8800 3250
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Wire Wire Line
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8800 3250 7850 3250
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Wire Wire Line
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1650 3250 1850 3250
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NoConn ~ 2300 4050
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@ -681,4 +655,14 @@ F 3 "" H 1450 3250 50 0001 C CNN
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1 1450 3250
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0 -1 -1 0
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$EndComp
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Wire Wire Line
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7850 1150 8950 1150
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Wire Wire Line
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7350 2350 7350 2450
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Connection ~ 7350 2450
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Wire Wire Line
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7850 3250 8950 3250
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Wire Wire Line
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7350 4450 7350 4550
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Connection ~ 7350 4550
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$EndSCHEMATC
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