Uploaded_3_22_2020
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MicroCoreLabs
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//
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//
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// File Name : MCL65.c
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// Used on :
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// Author : Ted Fried, MicroCore Labs
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// Creation : 3/22/2020
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// Code Type : C code
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//
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// Description:
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// ============
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//
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// C Code emulating the MCL65 Microsequencer of the MOS 6502 microprocessor
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// This is a C version of the MCL65 which is written in Verilog. It runs the
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// exact same microcode. NMI and Interrupts are suppored.
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// Each loop of the code below is equivalent to one microsequencer clock
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// and will execute a new micro-instruction each time.
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// The user code and data RAM are held in a 64KB array.
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//
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//------------------------------------------------------------------------
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//
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// Modification History:
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// =====================
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//
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// Revision 1 3/22/2020
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// Initial revision
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//
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//
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//------------------------------------------------------------------------
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//
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// Copyright (c) 2020 Ted Fried
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all
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// copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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//
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//------------------------------------------------------------------------
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#include <stdio.h>
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#include "mcl65.h"
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#define rdwr_n ( system_output & 0x1 ) >> 0 // system_output[0]
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#define flag_i ( register_flags & 0x04 ) >> 2 // register_flags[2]
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#define opcode_type ( rom_data & 0xF0000000 ) >> 28 // rom_data[30:28];
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#define opcode_dst_sel ( rom_data & 0x0F000000 ) >> 24 // rom_data[27:24];
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#define opcode_op0_sel ( rom_data & 0x00F00000 ) >> 20 // rom_data[23:20];
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#define opcode_op1_sel ( rom_data & 0x000F0000 ) >> 16 // rom_data[19:16];
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#define opcode_immediate ( rom_data & 0x0000FFFF ) >> 00 // rom_data[15:0];
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#define opcode_jump_call ( rom_data & 0x01000000 ) >> 24 // rom_data[24];
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#define opcode_jump_src ( rom_data & 0x00700000 ) >> 20 // rom_data[22:20];
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#define opcode_jump_cond ( rom_data & 0x000F0000 ) >> 16 // rom_data[16:19];
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unsigned char attached_memory[65536]={ };
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unsigned char register_flags=0;
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unsigned char add_carry7=0;
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unsigned char add_carry8=0;
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unsigned char nmi_asserted=0;
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unsigned char irq_gated=0;
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unsigned char add_overflow8=0;
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unsigned char nmi_debounce=0;
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unsigned char system_status=0;
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unsigned char register_a=0;
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unsigned char register_x=0;
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unsigned char register_y=0;
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unsigned short int register_r0=0;
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unsigned short int register_r1=0;
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unsigned short int register_r2=0;
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unsigned short int register_r3=0;
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unsigned short int register_pc=0x400;
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unsigned short int register_sp=0;
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unsigned short int address_out=0;
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unsigned short int data_in=0;
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unsigned short int data_out=0;
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unsigned short int system_output=0;
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unsigned short int alu_last_result=0;
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unsigned short int alu_out=0;
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unsigned short int rom_address=0x07D0; // Address for Microcode Reset procedure
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unsigned short int operand0=0;
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unsigned short int operand1=0;
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unsigned long rom_data;
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unsigned long calling_address;
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// Main loop
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//
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int main()
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{
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while (1)
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{
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// Optional INT and NMI Signals
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// irq_gated = P6502_IRQ_n & ~flag_i;
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// if (nmi_debounce==1) nmi_asserted=0; else if (P6502_NMI_n_old==1 && P6502_NMI_n==0) nmi_asserted=1; P6502_NMI_n_old = P6502_NMI_n;
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data_in = attached_memory[address_out]; // Read data from the Attached Memory RAM
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rom_data = microcode_rom[rom_address]; // Fetch the next microcode instruction
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system_status = ( add_carry8 << 0 | // system_status[0]
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nmi_asserted << 3 | // system_status[3]
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irq_gated << 5 | // system_status[5]
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add_overflow8 << 6 ); // system_status[6]
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switch (opcode_op0_sel)
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{
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case 0x0: operand0 = register_r0; break;
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case 0x1: operand0 = register_r1; break;
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case 0x2: operand0 = register_r2; break;
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case 0x3: operand0 = register_r3; break;
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case 0x4: operand0 = register_a & 0x00FF; break;
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case 0x5: operand0 = register_x & 0x00FF; break;
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case 0x6: operand0 = register_y & 0x00FF; break;
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case 0x7: operand0 = register_pc; break;
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case 0x8: operand0 = ((register_sp & 0x00FF) | 0x0100); break;
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case 0x9: operand0 = register_flags & 0x00FF; break;
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case 0xA: operand0 = address_out; break;
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case 0xB: operand0 = ((data_in&0xFF) << 8) | (data_in&0xFF); break;
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case 0xC: operand0 = system_status; break;
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case 0xD: operand0 = system_output; break;
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case 0xE: operand0 = 0; break;
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case 0xF: operand0 = 0; break;
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}
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switch (opcode_op1_sel)
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{
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case 0x0: operand1 = register_r0; break;
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case 0x1: operand1 = register_r1; break;
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case 0x2: operand1 = register_r2; break;
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case 0x3: operand1 = register_r3; break;
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case 0x4: operand1 = register_a & 0x00FF; break;
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case 0x5: operand1 = register_x & 0x00FF; break;
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case 0x6: operand1 = register_y & 0x00FF; break;
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case 0x7: operand1 = ( (register_pc<<8) | (register_pc>>8) ) ; break;
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case 0x8: operand1 = ((register_sp & 0x00FF) | 0x0100); break;
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case 0x9: operand1 = register_flags & 0x00FF; break;
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case 0xA: operand1 = address_out; break;
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case 0xB: operand1 =( ( data_in << 8) | data_in); break;
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case 0xC: operand1 = system_status; break;
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case 0xD: operand1 = system_output; break;
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case 0xE: operand1 = 0; break;
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case 0xF: operand1 = opcode_immediate; break;
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}
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switch (opcode_type)
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{
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case 0x2: // ADD
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alu_out = operand0 + operand1;
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add_carry7 = (( ((operand0&0x007F) + (operand1&0x007F)) & 0x0080) >> 7);
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add_carry8 = (( ((operand0&0x00FF) + (operand1&0x00FF)) & 0x0100) >> 8);
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add_overflow8 = (add_carry7 ^ add_carry8) & 0x1;
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break;
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case 0x3: alu_out = operand0 & operand1; break; // AND
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case 0x4: alu_out = operand0 | operand1; break; // OR
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case 0x5: alu_out = operand0 ^ operand1; break; // XOR
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case 0x6: alu_out = operand0 >> 1; break; // SHR
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default: alu_out = 0xEEEE; break;
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}
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// Register write-back
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if (opcode_type > 1)
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{
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alu_last_result = alu_out;
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switch (opcode_dst_sel)
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{
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case 0x0: register_r0 = alu_out; break;
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case 0x1: register_r1 = alu_out; break;
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case 0x2: register_r2 = alu_out; break;
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case 0x3: register_r3 = alu_out; break;
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case 0x4: register_a = alu_out & 0x00FF; break;
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case 0x5: register_x = alu_out & 0x00FF; break;
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case 0x6: register_y = alu_out & 0x00FF; break;
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case 0x7: register_pc = alu_out; break;
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case 0x8: register_sp = alu_out & 0x00FF; break;
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case 0x9: register_flags = alu_out | 0x30; break;
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case 0xA: address_out = alu_out; break;
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case 0xB: data_out = alu_out & 0x00FF; break;
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case 0xD: system_output = alu_out & 0x001F; break;
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default: break;
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}
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}
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// JUMP Opcode
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if ( ( opcode_type==0x1 && opcode_jump_cond==0x0 ) || // Unconditional jump
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( opcode_type==0x1 && opcode_jump_cond==0x1 && alu_last_result!=0 ) || // Jump Not Zero
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( opcode_type==0x1 && opcode_jump_cond==0x2 && alu_last_result==0 ) ) // Jump Zero
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{
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// For subroutine CALLs, store next opcode address
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if (opcode_jump_call==1)
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calling_address = (calling_address<<11) | (rom_address&0x07FF) ;
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switch (opcode_jump_src)
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{
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case 0x0: rom_address = opcode_immediate & 0x07FF; break;
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case 0x1: rom_address = data_in & 0x00FF; break; // Opcode Jump Table
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case 0x2: rom_address = (calling_address & 0x07FF) + 1;
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calling_address = calling_address>>11;
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break;
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}
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}
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else
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rom_address = rom_address + 1;
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// Writes to the 6502 Data RAM occur on the simulated rising edge of the clock
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if (opcode_type==0x1 && opcode_jump_cond==0x3 && rdwr_n==0) attached_memory[address_out] = data_out;
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}
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}
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File diff suppressed because one or more lines are too long
13
README.md
13
README.md
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@ -1,6 +1,6 @@
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# Ted Fried's MicroCore Labs Projects
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My blog which has some details on these projects: MicroCoreLabs.Wordpress.com
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My blog which has some details on these projects: www.MicroCoreLabs.Wordpress.com
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My YouTube Channel with some videos of the stuff in action: www.youtube.com/channel/UC9B3TaEUon-araO2j7tp9jg/videos
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@ -9,20 +9,21 @@ My YouTube Channel with some videos of the stuff in action: www.youtube.com/chan
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Microsequencer-based processors:
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MCL65 - MOS 6502
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- C Version as well
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MCL51 - Intel 8051
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MCL86 - Intel 8086/8088
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Other processors:
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MCLR5 - Quad-Issue Superscalar RISCV
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Lockstep Quad Modular Redundant System
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Lockstep Quad Modular Redundant System
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Misc:
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Wheelwriter - FPGA based Printer Option for the IBM Wheelwriter 5
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Wheelwriter2 - Arduino Leonardo based Printer Option for the IBM Wheelwriter 5
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For questions email me at www.MicroCoreLabs.com
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