Uploaded_11_11_2020
This commit is contained in:
MicroCoreLabs
parent
c8667502be
commit
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Release 14.7 ngdbuild P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
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-intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p
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xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
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Reading NGO file "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ngc" ...
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Loading design module "ipcore_dir/EU4Kx32.ngc"...
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Gathering constraint information from source properties...
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Done.
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Annotating constraints to design from ucf file "MCL86jr.ucf" ...
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Resolving constraint associations...
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Checking Constraint Associations...
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INFO:ConstraintSystem:178 - TNM 'CORE_CLK', used in period specification
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'TS_CORE_CLK', was traced into DCM_SP instance SPARTAN6PLL/dcm_sp_inst. The
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following new TNM groups and period specifications were generated at the
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DCM_SP output(s):
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CLKFX: <TIMESPEC TS_SPARTAN6PLL_clkfx = PERIOD "SPARTAN6PLL_clkfx"
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TS_CORE_CLK / 2.2 HIGH 50%>
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Done...
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Checking expanded design ...
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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NGDBUILD Design Results Summary:
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Number of errors: 0
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Number of warnings: 0
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Total memory usage is 170808 kilobytes
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Writing NGD file "MCL86jr.ngd" ...
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Total REAL time to NGDBUILD completion: 4 sec
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Total CPU time to NGDBUILD completion: 4 sec
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Writing NGDBUILD log file "MCL86jr.bld"...
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@ -0,0 +1,676 @@
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xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
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xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
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xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-2 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-2 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
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trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
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xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-2 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
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trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
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xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
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trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
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xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
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trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
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trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
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trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
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xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
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trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
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xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
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trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
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xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
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trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
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trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
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xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
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trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
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xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
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trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
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par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
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trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
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xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
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trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
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xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-2 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
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trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
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xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-2 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
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trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
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xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
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map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
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par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
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trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
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xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
|
||||
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf
|
||||
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf
|
||||
bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd
|
||||
|
|
@ -0,0 +1,217 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="MCL86jr.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="MCL86jr.bld"/>
|
||||
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="MCL86jr.cmd_log"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="MCL86jr.lso"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="MCL86jr.ncd" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="MCL86jr.ngc"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="MCL86jr.ngd"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="MCL86jr.ngr"/>
|
||||
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="MCL86jr.pad"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="MCL86jr.par" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="MCL86jr.pcf" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="MCL86jr.prj"/>
|
||||
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="MCL86jr.ptwx"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="MCL86jr.stx"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="MCL86jr.syr"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="MCL86jr.twr" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="MCL86jr.twx" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="MCL86jr.unroutes" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="MCL86jr.ut" xil_pn:subbranch="FPGAConfiguration"/>
|
||||
<file xil_pn:fileType="FILE_XPI" xil_pn:name="MCL86jr.xpi"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="MCL86jr.xst"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="MCL86jr_envsettings.html"/>
|
||||
<file xil_pn:fileType="FILE_NCD" xil_pn:name="MCL86jr_guide.ncd" xil_pn:origination="imported"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="MCL86jr_map.map" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="MCL86jr_map.mrp" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="MCL86jr_map.ncd" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="MCL86jr_map.ngm" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:fileType="FILE_PSR" xil_pn:name="MCL86jr_map.psr"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="MCL86jr_map.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="MCL86jr_ngdbuild.xrpt"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="MCL86jr_pad.csv" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="MCL86jr_pad.txt" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="MCL86jr_par.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="MCL86jr_summary.html"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="MCL86jr_summary.xml"/>
|
||||
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="MCL86jr_usage.xml"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="MCL86jr_xst.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_CMD" xil_pn:name="_impact.cmd"/>
|
||||
<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impact.log"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="ipcore_dir/EU4Kx32.ngc" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_LOG" xil_pn:name="ipcore_dir/coregen.log"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="mcl86jr.bgn" xil_pn:subbranch="FPGAConfiguration"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="mcl86jr.bit" xil_pn:subbranch="FPGAConfiguration"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="mcl86jr.drc" xil_pn:subbranch="FPGAConfiguration"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_2"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_3"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
|
||||
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
|
||||
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|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1605150595" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1605150595">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1605150595" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3412741792593957925" xil_pn:start_ts="1605150595">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1605150596" xil_pn:in_ck="-7247114840459501862" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="787467277420992043" xil_pn:start_ts="1605150595">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="ipcore_dir/EU4Kx32.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/EU4Kx32.v"/>
|
||||
<outfile xil_pn:name="ipcore_dir/spartan6_pll.v"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1605150596" xil_pn:in_ck="656480033301313304" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1605150596">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
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|
||||
<transform xil_pn:end_ts="1605150596" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1358955015879939485" xil_pn:start_ts="1605150596">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
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|
||||
<transform xil_pn:end_ts="1605150596" xil_pn:in_ck="656480033301313304" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1605150596">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
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|
||||
<transform xil_pn:end_ts="1605150596" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="6091208428188821685" xil_pn:start_ts="1605150596">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
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|
||||
<transform xil_pn:end_ts="1605150615" xil_pn:in_ck="7485807331199273541" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2304791464621354458" xil_pn:start_ts="1605150596">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
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|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="MCL86jr.lso"/>
|
||||
<outfile xil_pn:name="MCL86jr.ngc"/>
|
||||
<outfile xil_pn:name="MCL86jr.ngr"/>
|
||||
<outfile xil_pn:name="MCL86jr.prj"/>
|
||||
<outfile xil_pn:name="MCL86jr.stx"/>
|
||||
<outfile xil_pn:name="MCL86jr.syr"/>
|
||||
<outfile xil_pn:name="MCL86jr.xst"/>
|
||||
<outfile xil_pn:name="MCL86jr_xst.xrpt"/>
|
||||
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
<outfile xil_pn:name="xst"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1605150615" xil_pn:in_ck="5237154405922346467" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1262981232102443208" xil_pn:start_ts="1605150615">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1605150622" xil_pn:in_ck="-1301045618153758935" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-3050930112883171540" xil_pn:start_ts="1605150615">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="MCL86jr.bld"/>
|
||||
<outfile xil_pn:name="MCL86jr.ngd"/>
|
||||
<outfile xil_pn:name="MCL86jr_ngdbuild.xrpt"/>
|
||||
<outfile xil_pn:name="_ngo"/>
|
||||
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1605150658" xil_pn:in_ck="-6237160376423811521" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="5459139723028316866" xil_pn:start_ts="1605150622">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="MCL86jr.pcf"/>
|
||||
<outfile xil_pn:name="MCL86jr_map.map"/>
|
||||
<outfile xil_pn:name="MCL86jr_map.mrp"/>
|
||||
<outfile xil_pn:name="MCL86jr_map.ncd"/>
|
||||
<outfile xil_pn:name="MCL86jr_map.ngm"/>
|
||||
<outfile xil_pn:name="MCL86jr_map.psr"/>
|
||||
<outfile xil_pn:name="MCL86jr_map.xrpt"/>
|
||||
<outfile xil_pn:name="MCL86jr_summary.xml"/>
|
||||
<outfile xil_pn:name="MCL86jr_usage.xml"/>
|
||||
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1605150702" xil_pn:in_ck="5563182848059918264" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1885771668075636388" xil_pn:start_ts="1605150658">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="MCL86jr.ncd"/>
|
||||
<outfile xil_pn:name="MCL86jr.pad"/>
|
||||
<outfile xil_pn:name="MCL86jr.par"/>
|
||||
<outfile xil_pn:name="MCL86jr.ptwx"/>
|
||||
<outfile xil_pn:name="MCL86jr.unroutes"/>
|
||||
<outfile xil_pn:name="MCL86jr.xpi"/>
|
||||
<outfile xil_pn:name="MCL86jr_pad.csv"/>
|
||||
<outfile xil_pn:name="MCL86jr_pad.txt"/>
|
||||
<outfile xil_pn:name="MCL86jr_par.xrpt"/>
|
||||
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1605150730" xil_pn:in_ck="121150499032679689" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3552836582087367069" xil_pn:start_ts="1605150702">
|
||||
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|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
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|
||||
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|
||||
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
|
||||
<outfile xil_pn:name="mcl86jr.bgn"/>
|
||||
<outfile xil_pn:name="mcl86jr.bit"/>
|
||||
<outfile xil_pn:name="mcl86jr.drc"/>
|
||||
<outfile xil_pn:name="usage_statistics_webtalk.html"/>
|
||||
<outfile xil_pn:name="webtalk.log"/>
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1605041197" xil_pn:in_ck="171691199137775411" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1605041194">
|
||||
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|
||||
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|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<outfile xil_pn:name="_impact.cmd"/>
|
||||
<outfile xil_pn:name="_impact.log"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600579929" xil_pn:in_ck="121150499032679689" xil_pn:name="TRAN_XPower_spartan6" xil_pn:prop_ck="1949643303204221642" xil_pn:start_ts="1600579929">
|
||||
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|
||||
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|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1605150702" xil_pn:in_ck="5538025637473800251" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1605150695">
|
||||
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|
||||
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|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="MCL86jr.twr"/>
|
||||
<outfile xil_pn:name="MCL86jr.twx"/>
|
||||
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
</generated_project>
|
||||
|
|
@ -0,0 +1 @@
|
|||
work
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,174 @@
|
|||
Release 14.7 - par P.20131013 (nt64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Wed Nov 11 19:11:33 2020
|
||||
|
||||
|
||||
# NOTE: This file is designed to be imported into a spreadsheet program
|
||||
# such as Microsoft Excel for viewing, printing and sorting. The |
|
||||
# character is used as the data field separator. This file is also designed
|
||||
# to support parsing.
|
||||
#
|
||||
INPUT FILE: MCL86jr_map.ncd
|
||||
OUTPUT FILE: MCL86jr.pad
|
||||
PART TYPE: xc6slx9
|
||||
SPEED GRADE: -3
|
||||
PACKAGE: tqg144
|
||||
|
||||
Pinout by Pin Number:
|
||||
|
||||
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
|
||||
Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
|
||||
P1|A13|IOB|IO_L83N_VREF_3|OUTPUT|PCI33_3|3||||||LOCATED|YES|NONE|
|
||||
P2|A16|IOB|IO_L83P_3|OUTPUT|PCI33_3|3||||||LOCATED|YES|NONE|
|
||||
P3|||GND||||||||||||
|
||||
P4|||VCCO_3|||3|||||3.30||||
|
||||
P5|A12|IOB|IO_L52N_3|OUTPUT|PCI33_3|3||||||LOCATED|YES|NONE|
|
||||
P6|A17|IOB|IO_L52P_3|OUTPUT|PCI33_3|3||||||LOCATED|YES|NONE|
|
||||
P7|A11|IOB|IO_L51N_3|OUTPUT|PCI33_3|3||||||LOCATED|YES|NONE|
|
||||
P8|A18|IOB|IO_L51P_3|OUTPUT|PCI33_3|3||||||LOCATED|YES|NONE|
|
||||
P9|A10|IOB|IO_L50N_3|OUTPUT|PCI33_3|3||||||LOCATED|YES|NONE|
|
||||
P10|A19|IOB|IO_L50P_3|OUTPUT|PCI33_3|3||||||LOCATED|YES|NONE|
|
||||
P11|A9|IOB|IO_L49N_3|OUTPUT|PCI33_3|3||||||LOCATED|YES|NONE|
|
||||
P12|SSO_n|IOB|IO_L49P_3|OUTPUT|PCI33_3|3||||||LOCATED|NO|NONE|
|
||||
P13|||GND||||||||||||
|
||||
P14|A8|IOB|IO_L44N_GCLK20_3|OUTPUT|PCI33_3|3||||||LOCATED|YES|NONE|
|
||||
P15||IOBM|IO_L44P_GCLK21_3|UNUSED||3|||||||||
|
||||
P16|BUF2_DIR|IOB|IO_L43N_GCLK22_IRDY2_3|OUTPUT|PCI33_3|3||||||LOCATED|NO|NONE|
|
||||
P17||IOBM|IO_L43P_GCLK23_3|UNUSED||3|||||||||
|
||||
P18|||VCCO_3|||3|||||3.30||||
|
||||
P19|||VCCINT||||||||1.2||||
|
||||
P20|||VCCAUX||||||||2.5||||
|
||||
P21|BUF2_OE_n|IOB|IO_L42N_GCLK24_3|OUTPUT|PCI33_3|3||||||LOCATED|NO|NONE|
|
||||
P22|AD7|IOB|IO_L42P_GCLK25_TRDY2_3|BIDIR|PCI33_3|3||||NONE||LOCATED|YES|NONE|
|
||||
P23|AD6|IOB|IO_L41N_GCLK26_3|BIDIR|PCI33_3|3||||NONE||LOCATED|YES|NONE|
|
||||
P24||IOBM|IO_L41P_GCLK27_3|UNUSED||3|||||||||
|
||||
P25|||GND||||||||||||
|
||||
P26|AD5|IOB|IO_L37N_3|BIDIR|PCI33_3|3||||NONE||LOCATED|YES|NONE|
|
||||
P27|AD4|IOB|IO_L37P_3|BIDIR|PCI33_3|3||||NONE||LOCATED|YES|NONE|
|
||||
P28|||VCCINT||||||||1.2||||
|
||||
P29||IOBS|IO_L36N_3|UNUSED||3|||||||||
|
||||
P30||IOBM|IO_L36P_3|UNUSED||3|||||||||
|
||||
P31|||VCCO_3|||3|||||3.30||||
|
||||
P32|AD3|IOB|IO_L2N_3|BIDIR|PCI33_3|3||||NONE||LOCATED|YES|NONE|
|
||||
P33|AD2|IOB|IO_L2P_3|BIDIR|PCI33_3|3||||NONE||LOCATED|YES|NONE|
|
||||
P34|AD1|IOB|IO_L1N_VREF_3|BIDIR|PCI33_3|3||||NONE||LOCATED|YES|NONE|
|
||||
P35|AD0|IOB|IO_L1P_3|BIDIR|PCI33_3|3||||NONE||LOCATED|YES|NONE|
|
||||
P36|||VCCAUX||||||||2.5||||
|
||||
P37|||PROGRAM_B_2||||||||||||
|
||||
P38||IOBS|IO_L65N_CSO_B_2|UNUSED||2|||||||||
|
||||
P39||IOBM|IO_L65P_INIT_B_2|UNUSED||2|||||||||
|
||||
P40||IOBS|IO_L64N_D9_2|UNUSED||2|||||||||
|
||||
P41|ALE|IOB|IO_L64P_D8_2|OUTPUT|PCI33_3|2||||||LOCATED|YES|NONE|
|
||||
P42|||VCCO_2|||2|||||3.30||||
|
||||
P43||IOBS|IO_L62N_D6_2|UNUSED||2|||||||||
|
||||
P44|NMI|IOB|IO_L62P_D5_2|INPUT|LVCMOS33|2|||PULLDOWN|NONE||LOCATED|YES|NONE|
|
||||
P45|INTR|IOB|IO_L49N_D4_2|INPUT|PCI33_3|2||||NONE||LOCATED|YES|NONE|
|
||||
P46|CLK|IOB|IO_L49P_D3_2|INPUT|PCI33_3|2||||NONE||LOCATED|YES|NONE|
|
||||
P47|RESET|IOB|IO_L48N_RDWR_B_VREF_2|INPUT|PCI33_3|2||||NONE||LOCATED|NO|NONE|
|
||||
P48|READY|IOB|IO_L48P_D7_2|INPUT|PCI33_3|2||||NONE||LOCATED|YES|NONE|
|
||||
P49|||GND||||||||||||
|
||||
P50|RD_n|IOB|IO_L31N_GCLK30_D15_2|OUTPUT|PCI33_3|2||||||LOCATED|YES|NONE|
|
||||
P51|WR_n|IOB|IO_L31P_GCLK31_D14_2|OUTPUT|PCI33_3|2||||||LOCATED|YES|NONE|
|
||||
P52|||VCCINT||||||||1.2||||
|
||||
P53|||VCCAUX||||||||2.5||||
|
||||
P54|||GND||||||||||||
|
||||
P55|IOM|IOB|IO_L30N_GCLK0_USERCCLK_2|OUTPUT|PCI33_3|2||||||LOCATED|YES|NONE|
|
||||
P56|DTR|IOB|IO_L30P_GCLK1_D13_2|OUTPUT|PCI33_3|2||||||LOCATED|YES|NONE|
|
||||
P57|DEN|IOB|IO_L14N_D12_2|OUTPUT|PCI33_3|2||||||LOCATED|YES|NONE|
|
||||
P58|INTA_n|IOB|IO_L14P_D11_2|OUTPUT|PCI33_3|2||||||LOCATED|YES|NONE|
|
||||
P59|BUF1_OE_n|IOB|IO_L13N_D10_2|OUTPUT|PCI33_3|2||||||LOCATED|NO|NONE|
|
||||
P60||IOBM|IO_L13P_M1_2|UNUSED||2|||||||||
|
||||
P61|SRAM_A<4>|IOB|IO_L12N_D2_MISO3_2|OUTPUT|PCI33_3|2||||||LOCATED|NO|NONE|
|
||||
P62|SRAM_A<5>|IOB|IO_L12P_D1_MISO2_2|OUTPUT|PCI33_3|2||||||LOCATED|NO|NONE|
|
||||
P63|||VCCO_2|||2|||||3.30||||
|
||||
P64||IOBS|IO_L3N_MOSI_CSI_B_MISO0_2|UNUSED||2|||||||||
|
||||
P65||IOBM|IO_L3P_D0_DIN_MISO_MISO1_2|UNUSED||2|||||||||
|
||||
P66|SRAM_A<6>|IOB|IO_L2N_CMPMOSI_2|OUTPUT|PCI33_3|2||||||LOCATED|NO|NONE|
|
||||
P67|SRAM_A<7>|IOB|IO_L2P_CMPCLK_2|OUTPUT|PCI33_3|2||||||LOCATED|NO|NONE|
|
||||
P68|||GND||||||||||||
|
||||
P69||IOBS|IO_L1N_M0_CMPMISO_2|UNUSED||2|||||||||
|
||||
P70||IOBM|IO_L1P_CCLK_2|UNUSED||2|||||||||
|
||||
P71|||DONE_2||||||||||||
|
||||
P72|||CMPCS_B_2||||||||||||
|
||||
P73|||SUSPEND||||||||||||
|
||||
P74|SRAM_A<12>|IOB|IO_L74N_DOUT_BUSY_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
|
||||
P75|SRAM_A<14>|IOB|IO_L74P_AWAKE_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
|
||||
P76|||VCCO_1|||1|||||3.30||||
|
||||
P77|||GND||||||||||||
|
||||
P78|SRAM_A<16>|IOB|IO_L47N_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
|
||||
P79|SRAM_A<17>|IOB|IO_L47P_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
|
||||
P80|SRAM_D<3>|IOB|IO_L46N_1|BIDIR|PCI33_3|1||||NONE||LOCATED|NO|NONE|
|
||||
P81|SRAM_D<4>|IOB|IO_L46P_1|BIDIR|PCI33_3|1||||NONE||LOCATED|NO|NONE|
|
||||
P82|SRAM_D<5>|IOB|IO_L45N_1|BIDIR|PCI33_3|1||||NONE||LOCATED|NO|NONE|
|
||||
P83|SRAM_D<6>|IOB|IO_L45P_1|BIDIR|PCI33_3|1||||NONE||LOCATED|NO|NONE|
|
||||
P84|CORE_CLK|IOB|IO_L43N_GCLK4_1|INPUT|PCI33_3|1||||NONE||LOCATED|NO|NONE|
|
||||
P85|SRAM_D<7>|IOB|IO_L43P_GCLK5_1|BIDIR|PCI33_3|1||||NONE||LOCATED|NO|NONE|
|
||||
P86|||VCCO_1|||1|||||3.30||||
|
||||
P87|SRAM_CE_n|IOB|IO_L42N_GCLK6_TRDY1_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
|
||||
P88|SRAM_A<10>|IOB|IO_L42P_GCLK7_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
|
||||
P89|||VCCINT||||||||1.2||||
|
||||
P90|||VCCAUX||||||||2.5||||
|
||||
P91|||GND||||||||||||
|
||||
P92|SRAM_OE_n|IOB|IO_L41N_GCLK8_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
|
||||
P93|SRAM_A<11>|IOB|IO_L41P_GCLK9_IRDY1_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
|
||||
P94|SRAM_A<9>|IOB|IO_L40N_GCLK10_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
|
||||
P95|SRAM_A<8>|IOB|IO_L40P_GCLK11_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
|
||||
P96|||GND||||||||||||
|
||||
P97|SRAM_A<13>|IOB|IO_L34N_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
|
||||
P98|SRAM_WE_n|IOB|IO_L34P_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
|
||||
P99|SRAM_A<18>|IOB|IO_L33N_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
|
||||
P100|SRAM_A<15>|IOB|IO_L33P_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
|
||||
P101||IOBS|IO_L32N_1|UNUSED||1|||||||||
|
||||
P102||IOBM|IO_L32P_1|UNUSED||1|||||||||
|
||||
P103|||VCCO_1|||1|||||3.30||||
|
||||
P104||IOBS|IO_L1N_VREF_1|UNUSED||1|||||||||
|
||||
P105||IOBM|IO_L1P_1|UNUSED||1|||||||||
|
||||
P106|||TDO||||||||||||
|
||||
P107|||TMS||||||||||||
|
||||
P108|||GND||||||||||||
|
||||
P109|||TCK||||||||||||
|
||||
P110|||TDI||||||||||||
|
||||
P111|LED<0>|IOB|IO_L66N_SCP0_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
|
||||
P112|LED<1>|IOB|IO_L66P_SCP1_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
|
||||
P113|||GND||||||||||||
|
||||
P114|LED<2>|IOB|IO_L65N_SCP2_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
|
||||
P115||IOBM|IO_L65P_SCP3_0|UNUSED||0|||||||||
|
||||
P116|LED<3>|IOB|IO_L64N_SCP4_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
|
||||
P117|SRAM_D<2>|IOB|IO_L64P_SCP5_0|BIDIR|PCI33_3|0||||NONE||LOCATED|NO|NONE|
|
||||
P118|SRAM_D<1>|IOB|IO_L63N_SCP6_0|BIDIR|PCI33_3|0||||NONE||LOCATED|NO|NONE|
|
||||
P119|SRAM_D<0>|IOB|IO_L63P_SCP7_0|BIDIR|PCI33_3|0||||NONE||LOCATED|NO|NONE|
|
||||
P120|LED<4>|IOB|IO_L62N_VREF_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
|
||||
P121|LED<5>|IOB|IO_L62P_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
|
||||
P122|||VCCO_0|||0|||||3.30||||
|
||||
P123|SRAM_A<3>|IOB|IO_L37N_GCLK12_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
|
||||
P124|SRAM_A<2>|IOB|IO_L37P_GCLK13_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
|
||||
P125|||VCCO_0|||0|||||3.30||||
|
||||
P126|SRAM_A<1>|IOB|IO_L36N_GCLK14_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
|
||||
P127|LED<6>|IOB|IO_L36P_GCLK15_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
|
||||
P128|||VCCINT||||||||1.2||||
|
||||
P129|||VCCAUX||||||||2.5||||
|
||||
P130|||GND||||||||||||
|
||||
P131|LED<7>|IOB|IO_L35N_GCLK16_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
|
||||
P132|SRAM_A<0>|IOB|IO_L35P_GCLK17_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
|
||||
P133||IOBS|IO_L34N_GCLK18_0|UNUSED||0|||||||||
|
||||
P134||IOBM|IO_L34P_GCLK19_0|UNUSED||0|||||||||
|
||||
P135|||VCCO_0|||0|||||3.30||||
|
||||
P136|||GND||||||||||||
|
||||
P137||IOBS|IO_L4N_0|UNUSED||0|||||||||
|
||||
P138||IOBM|IO_L4P_0|UNUSED||0|||||||||
|
||||
P139||IOBS|IO_L3N_0|UNUSED||0|||||||||
|
||||
P140||IOBM|IO_L3P_0|UNUSED||0|||||||||
|
||||
P141||IOBS|IO_L2N_0|UNUSED||0|||||||||
|
||||
P142|A14|IOB|IO_L2P_0|OUTPUT|PCI33_3|0||||||LOCATED|YES|NONE|
|
||||
P143|A15|IOB|IO_L1N_VREF_0|OUTPUT|PCI33_3|0||||||LOCATED|YES|NONE|
|
||||
P144||IOBM|IO_L1P_HSWAPEN_0|UNUSED||0|||||||||
|
||||
|
||||
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
|
||||
|
||||
* Default value.
|
||||
** This default Pullup/Pulldown value can be overridden in Bitgen.
|
||||
****** Special VCCO requirements may apply. Please consult the device
|
||||
family datasheet for specific guideline on VCCO requirements.
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,228 @@
|
|||
Release 14.7 par P.20131013 (nt64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
MICROCORELABS:: Wed Nov 11 19:10:59 2020
|
||||
|
||||
par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd
|
||||
MCL86jr.pcf
|
||||
|
||||
|
||||
Constraints file: MCL86jr.pcf.
|
||||
Loading device for application Rf_Device from file '6slx9.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
|
||||
"MCL86jr" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -3
|
||||
|
||||
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
|
||||
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
||||
|
||||
|
||||
Device speed data version: "PRODUCTION 1.23 2013-10-13".
|
||||
|
||||
|
||||
|
||||
Device Utilization Summary:
|
||||
|
||||
Slice Logic Utilization:
|
||||
Number of Slice Registers: 853 out of 11,440 7%
|
||||
Number used as Flip Flops: 853
|
||||
Number used as Latches: 0
|
||||
Number used as Latch-thrus: 0
|
||||
Number used as AND/OR logics: 0
|
||||
Number of Slice LUTs: 959 out of 5,720 16%
|
||||
Number used as logic: 887 out of 5,720 15%
|
||||
Number using O6 output only: 681
|
||||
Number using O5 output only: 54
|
||||
Number using O5 and O6: 152
|
||||
Number used as ROM: 0
|
||||
Number used as Memory: 58 out of 1,440 4%
|
||||
Number used as Dual Port RAM: 0
|
||||
Number used as Single Port RAM: 0
|
||||
Number used as Shift Register: 58
|
||||
Number using O6 output only: 2
|
||||
Number using O5 output only: 0
|
||||
Number using O5 and O6: 56
|
||||
Number used exclusively as route-thrus: 14
|
||||
Number with same-slice register load: 8
|
||||
Number with same-slice carry load: 6
|
||||
Number with other load: 0
|
||||
|
||||
Slice Logic Distribution:
|
||||
Number of occupied Slices: 381 out of 1,430 26%
|
||||
Number of MUXCYs used: 196 out of 2,860 6%
|
||||
Number of LUT Flip Flop pairs used: 1,197
|
||||
Number with an unused Flip Flop: 437 out of 1,197 36%
|
||||
Number with an unused LUT: 238 out of 1,197 19%
|
||||
Number of fully used LUT-FF pairs: 522 out of 1,197 43%
|
||||
Number of slice register sites lost
|
||||
to control set restrictions: 0 out of 11,440 0%
|
||||
|
||||
A LUT Flip Flop pair for this architecture represents one LUT paired with
|
||||
one Flip Flop within a slice. A control set is a unique combination of
|
||||
clock, reset, set, and enable signals for a registered element.
|
||||
The Slice Logic Distribution report is not meaningful if the design is
|
||||
over-mapped for a non-slice resource or if Placement fails.
|
||||
|
||||
IO Utilization:
|
||||
Number of bonded IOBs: 75 out of 102 73%
|
||||
Number of LOCed IOBs: 75 out of 75 100%
|
||||
IOB Flip Flops: 39
|
||||
|
||||
Specific Feature Utilization:
|
||||
Number of RAMB16BWERs: 7 out of 32 21%
|
||||
Number of RAMB8BWERs: 1 out of 64 1%
|
||||
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
|
||||
Number used as BUFIO2s: 1
|
||||
Number used as BUFIO2_2CLKs: 0
|
||||
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
|
||||
Number of BUFG/BUFGMUXs: 1 out of 16 6%
|
||||
Number used as BUFGs: 1
|
||||
Number used as BUFGMUX: 0
|
||||
Number of DCM/DCM_CLKGENs: 1 out of 4 25%
|
||||
Number used as DCMs: 1
|
||||
Number used as DCM_CLKGENs: 0
|
||||
Number of ILOGIC2/ISERDES2s: 12 out of 200 6%
|
||||
Number used as ILOGIC2s: 12
|
||||
Number used as ISERDES2s: 0
|
||||
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
|
||||
Number of OLOGIC2/OSERDES2s: 27 out of 200 13%
|
||||
Number used as OLOGIC2s: 27
|
||||
Number used as OSERDES2s: 0
|
||||
Number of BSCANs: 0 out of 4 0%
|
||||
Number of BUFHs: 0 out of 128 0%
|
||||
Number of BUFPLLs: 0 out of 8 0%
|
||||
Number of BUFPLL_MCBs: 0 out of 4 0%
|
||||
Number of DSP48A1s: 0 out of 16 0%
|
||||
Number of ICAPs: 0 out of 1 0%
|
||||
Number of MCBs: 0 out of 2 0%
|
||||
Number of PCILOGICSEs: 0 out of 2 0%
|
||||
Number of PLL_ADVs: 0 out of 2 0%
|
||||
Number of PMVs: 0 out of 1 0%
|
||||
Number of STARTUPs: 0 out of 1 0%
|
||||
Number of SUSPEND_SYNCs: 0 out of 1 0%
|
||||
|
||||
|
||||
Overall effort level (-ol): High
|
||||
Router effort level (-rl): High
|
||||
|
||||
WARNING:Timing:3402 - The Clock Modifying COMP, SPARTAN6PLL/dcm_sp_inst, has the attribute CLK_FEEDBACK set to NONE. No phase relationship
|
||||
exists between the input and output clocks of this Clock Modifying COMP. Data paths between these clock domains must be constrained using
|
||||
FROM/TO constraints.
|
||||
Starting initial Timing Analysis. REAL time: 4 secs
|
||||
Finished initial Timing Analysis. REAL time: 4 secs
|
||||
|
||||
Starting Router
|
||||
|
||||
|
||||
Phase 1 : 7181 unrouted; REAL time: 4 secs
|
||||
|
||||
Phase 2 : 5599 unrouted; REAL time: 5 secs
|
||||
|
||||
Phase 3 : 2119 unrouted; REAL time: 8 secs
|
||||
|
||||
Phase 4 : 2185 unrouted; (Setup:587, Hold:47, Component Switching Limit:0) REAL time: 9 secs
|
||||
|
||||
Updating file: MCL86jr.ncd with current fully routed design.
|
||||
|
||||
Phase 5 : 0 unrouted; (Setup:6935, Hold:53, Component Switching Limit:0) REAL time: 19 secs
|
||||
|
||||
Phase 6 : 0 unrouted; (Setup:769, Hold:53, Component Switching Limit:0) REAL time: 23 secs
|
||||
|
||||
Updating file: MCL86jr.ncd with current fully routed design.
|
||||
|
||||
Phase 7 : 0 unrouted; (Setup:769, Hold:53, Component Switching Limit:0) REAL time: 32 secs
|
||||
|
||||
Phase 8 : 0 unrouted; (Setup:769, Hold:53, Component Switching Limit:0) REAL time: 32 secs
|
||||
|
||||
Phase 9 : 0 unrouted; (Setup:769, Hold:53, Component Switching Limit:0) REAL time: 32 secs
|
||||
|
||||
Phase 10 : 0 unrouted; (Setup:769, Hold:0, Component Switching Limit:0) REAL time: 32 secs
|
||||
|
||||
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 33 secs
|
||||
Total REAL time to Router completion: 33 secs
|
||||
Total CPU time to Router completion: 33 secs
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
Generating "PAR" statistics.
|
||||
|
||||
**************************
|
||||
Generating Clock Report
|
||||
**************************
|
||||
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| core_clk_int | BUFGMUX_X2Y3| No | 321 | 0.601 | 1.669 |
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
|
||||
* Net Skew is the difference between the minimum and maximum routing
|
||||
only delays for the net. Note this is different from Clock Skew which
|
||||
is reported in TRCE timing report. Clock Skew is the difference between
|
||||
the minimum and maximum path delays which includes logic delays.
|
||||
|
||||
* The fanout is the number of component pins not the individual BEL loads,
|
||||
for example SLICE loads not FF loads.
|
||||
|
||||
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
|
||||
|
||||
Number of Timing Constraints that were not applied: 1
|
||||
|
||||
Asterisk (*) preceding a constraint indicates it was not met.
|
||||
This may be due to a setup or hold violation.
|
||||
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
Constraint | Check | Worst Case | Best Case | Timing | Timing
|
||||
| | Slack | Achievable | Errors | Score
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
TS_SPARTAN6PLL_clkfx = PERIOD TIMEGRP "SP | SETUP | 0.299ns| 8.791ns| 0| 0
|
||||
ARTAN6PLL_clkfx" TS_CORE_CLK / 2.2 | HOLD | 0.367ns| | 0| 0
|
||||
HIGH 50% | | | | |
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
TS_CORE_CLK = PERIOD TIMEGRP "CORE_CLK" 2 | MINLOWPULSE | 12.000ns| 8.000ns| 0| 0
|
||||
0 ns HIGH 50% | | | | |
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Derived Constraint Report
|
||||
Review Timing Report for more details on the following derived constraints.
|
||||
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
|
||||
or "Run Timing Analysis" from Timing Analyzer (timingan).
|
||||
Derived Constraints for TS_CORE_CLK
|
||||
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
||||
| | Period | Actual Period | Timing Errors | Paths Analyzed |
|
||||
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|
||||
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
|
||||
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
||||
|TS_CORE_CLK | 20.000ns| 8.000ns| 19.340ns| 0| 0| 0| 513828|
|
||||
| TS_SPARTAN6PLL_clkfx | 9.091ns| 8.791ns| N/A| 0| 0| 513828| 0|
|
||||
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
||||
|
||||
All constraints were met.
|
||||
|
||||
|
||||
Generating Pad Report.
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
Total REAL time to PAR completion: 34 secs
|
||||
Total CPU time to PAR completion: 34 secs
|
||||
|
||||
Peak Memory Usage: 421 MB
|
||||
|
||||
Placer: Placement generated during map.
|
||||
Routing: Completed - No errors found.
|
||||
Timing: Completed - No errors found.
|
||||
|
||||
Number of error messages: 0
|
||||
Number of warning messages: 1
|
||||
Number of info messages: 0
|
||||
|
||||
Writing design to file MCL86jr.ncd
|
||||
|
||||
|
||||
|
||||
PAR done!
|
||||
|
|
@ -0,0 +1,756 @@
|
|||
//! **************************************************************************
|
||||
// Written by: Map P.20131013 on Wed Nov 11 19:10:56 2020
|
||||
//! **************************************************************************
|
||||
|
||||
SCHEMATIC START;
|
||||
COMP "A8" LOCATE = SITE "P14" LEVEL 1;
|
||||
COMP "A9" LOCATE = SITE "P11" LEVEL 1;
|
||||
COMP "A10" LOCATE = SITE "P9" LEVEL 1;
|
||||
COMP "A11" LOCATE = SITE "P7" LEVEL 1;
|
||||
COMP "A12" LOCATE = SITE "P5" LEVEL 1;
|
||||
COMP "A13" LOCATE = SITE "P1" LEVEL 1;
|
||||
COMP "A14" LOCATE = SITE "P142" LEVEL 1;
|
||||
COMP "A15" LOCATE = SITE "P143" LEVEL 1;
|
||||
COMP "A16" LOCATE = SITE "P2" LEVEL 1;
|
||||
COMP "A17" LOCATE = SITE "P6" LEVEL 1;
|
||||
COMP "A18" LOCATE = SITE "P8" LEVEL 1;
|
||||
COMP "A19" LOCATE = SITE "P10" LEVEL 1;
|
||||
COMP "AD0" LOCATE = SITE "P35" LEVEL 1;
|
||||
COMP "AD1" LOCATE = SITE "P34" LEVEL 1;
|
||||
COMP "AD2" LOCATE = SITE "P33" LEVEL 1;
|
||||
COMP "AD3" LOCATE = SITE "P32" LEVEL 1;
|
||||
COMP "AD4" LOCATE = SITE "P27" LEVEL 1;
|
||||
COMP "AD5" LOCATE = SITE "P26" LEVEL 1;
|
||||
COMP "AD6" LOCATE = SITE "P23" LEVEL 1;
|
||||
COMP "AD7" LOCATE = SITE "P22" LEVEL 1;
|
||||
COMP "ALE" LOCATE = SITE "P41" LEVEL 1;
|
||||
COMP "DEN" LOCATE = SITE "P57" LEVEL 1;
|
||||
COMP "CLK" LOCATE = SITE "P46" LEVEL 1;
|
||||
COMP "DTR" LOCATE = SITE "P56" LEVEL 1;
|
||||
COMP "IOM" LOCATE = SITE "P55" LEVEL 1;
|
||||
COMP "NMI" LOCATE = SITE "P44" LEVEL 1;
|
||||
COMP "SRAM_A<0>" LOCATE = SITE "P132" LEVEL 1;
|
||||
COMP "SRAM_A<1>" LOCATE = SITE "P126" LEVEL 1;
|
||||
COMP "SRAM_A<2>" LOCATE = SITE "P124" LEVEL 1;
|
||||
COMP "SRAM_A<3>" LOCATE = SITE "P123" LEVEL 1;
|
||||
COMP "SRAM_A<4>" LOCATE = SITE "P61" LEVEL 1;
|
||||
COMP "SRAM_A<5>" LOCATE = SITE "P62" LEVEL 1;
|
||||
COMP "SRAM_A<6>" LOCATE = SITE "P66" LEVEL 1;
|
||||
COMP "SRAM_A<7>" LOCATE = SITE "P67" LEVEL 1;
|
||||
COMP "SRAM_A<8>" LOCATE = SITE "P95" LEVEL 1;
|
||||
COMP "SRAM_A<9>" LOCATE = SITE "P94" LEVEL 1;
|
||||
COMP "SRAM_D<0>" LOCATE = SITE "P119" LEVEL 1;
|
||||
COMP "SRAM_D<1>" LOCATE = SITE "P118" LEVEL 1;
|
||||
COMP "SRAM_D<2>" LOCATE = SITE "P117" LEVEL 1;
|
||||
COMP "SRAM_D<3>" LOCATE = SITE "P80" LEVEL 1;
|
||||
COMP "SRAM_D<4>" LOCATE = SITE "P81" LEVEL 1;
|
||||
COMP "SRAM_D<5>" LOCATE = SITE "P82" LEVEL 1;
|
||||
COMP "SRAM_D<6>" LOCATE = SITE "P83" LEVEL 1;
|
||||
COMP "SRAM_D<7>" LOCATE = SITE "P85" LEVEL 1;
|
||||
COMP "SRAM_CE_n" LOCATE = SITE "P87" LEVEL 1;
|
||||
COMP "SRAM_OE_n" LOCATE = SITE "P92" LEVEL 1;
|
||||
COMP "SRAM_WE_n" LOCATE = SITE "P98" LEVEL 1;
|
||||
COMP "INTR" LOCATE = SITE "P45" LEVEL 1;
|
||||
COMP "RD_n" LOCATE = SITE "P50" LEVEL 1;
|
||||
COMP "WR_n" LOCATE = SITE "P51" LEVEL 1;
|
||||
COMP "SRAM_A<10>" LOCATE = SITE "P88" LEVEL 1;
|
||||
COMP "SRAM_A<11>" LOCATE = SITE "P93" LEVEL 1;
|
||||
COMP "SRAM_A<12>" LOCATE = SITE "P74" LEVEL 1;
|
||||
COMP "SRAM_A<13>" LOCATE = SITE "P97" LEVEL 1;
|
||||
COMP "SRAM_A<14>" LOCATE = SITE "P75" LEVEL 1;
|
||||
COMP "SRAM_A<15>" LOCATE = SITE "P100" LEVEL 1;
|
||||
COMP "SRAM_A<16>" LOCATE = SITE "P78" LEVEL 1;
|
||||
COMP "SRAM_A<17>" LOCATE = SITE "P79" LEVEL 1;
|
||||
COMP "SRAM_A<18>" LOCATE = SITE "P99" LEVEL 1;
|
||||
COMP "READY" LOCATE = SITE "P48" LEVEL 1;
|
||||
COMP "RESET" LOCATE = SITE "P47" LEVEL 1;
|
||||
COMP "SSO_n" LOCATE = SITE "P12" LEVEL 1;
|
||||
COMP "LED<0>" LOCATE = SITE "P111" LEVEL 1;
|
||||
COMP "LED<1>" LOCATE = SITE "P112" LEVEL 1;
|
||||
COMP "LED<2>" LOCATE = SITE "P114" LEVEL 1;
|
||||
COMP "LED<3>" LOCATE = SITE "P116" LEVEL 1;
|
||||
COMP "LED<4>" LOCATE = SITE "P120" LEVEL 1;
|
||||
COMP "LED<5>" LOCATE = SITE "P121" LEVEL 1;
|
||||
COMP "LED<6>" LOCATE = SITE "P127" LEVEL 1;
|
||||
COMP "LED<7>" LOCATE = SITE "P131" LEVEL 1;
|
||||
COMP "INTA_n" LOCATE = SITE "P58" LEVEL 1;
|
||||
COMP "BUF1_OE_n" LOCATE = SITE "P59" LEVEL 1;
|
||||
COMP "BUF2_OE_n" LOCATE = SITE "P21" LEVEL 1;
|
||||
COMP "BUF2_DIR" LOCATE = SITE "P16" LEVEL 1;
|
||||
COMP "CORE_CLK" LOCATE = SITE "P84" LEVEL 1;
|
||||
PIN
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>
|
||||
= BEL
|
||||
"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram"
|
||||
PINNAME CLKA;
|
||||
PIN
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>
|
||||
= BEL
|
||||
"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram"
|
||||
PINNAME CLKA;
|
||||
PIN
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>
|
||||
= BEL
|
||||
"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram"
|
||||
PINNAME CLKA;
|
||||
PIN
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>
|
||||
= BEL
|
||||
"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram"
|
||||
PINNAME CLKA;
|
||||
PIN
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>
|
||||
= BEL
|
||||
"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram"
|
||||
PINNAME CLKA;
|
||||
PIN
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM9.ram_pins<26>
|
||||
= BEL
|
||||
"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM9.ram"
|
||||
PINNAME CLKAWRCLK;
|
||||
PIN
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>
|
||||
= BEL
|
||||
"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram"
|
||||
PINNAME CLKA;
|
||||
PIN
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>
|
||||
= BEL
|
||||
"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram"
|
||||
PINNAME CLKA;
|
||||
TIMEGRP SPARTAN6PLL_clkfx = BEL "t_biu_ad_out_d_0" BEL "t_biu_ad_out_d_1" BEL
|
||||
"t_biu_ad_out_d_2" BEL "t_biu_ad_out_d_3" BEL "t_biu_ad_out_d_4" BEL
|
||||
"t_biu_ad_out_d_5" BEL "t_biu_ad_out_d_6" BEL "t_biu_ad_out_d_7" BEL
|
||||
"t_biu_ad_out_d_8" BEL "t_biu_ad_out_d_9" BEL "t_biu_ad_out_d_10" BEL
|
||||
"t_biu_ad_out_d_11" BEL "t_biu_ad_out_d_12" BEL "t_biu_ad_out_d_13"
|
||||
BEL "t_biu_ad_out_d_14" BEL "t_biu_ad_out_d_15" BEL
|
||||
"t_biu_ad_out_d_16" BEL "t_biu_ad_out_d_17" BEL "t_biu_ad_out_d_18"
|
||||
BEL "t_biu_ad_out_d_19" BEL "led_int_0" BEL "led_int_1" BEL
|
||||
"led_int_2" BEL "led_int_3" BEL "led_int_4" BEL "led_int_5" BEL
|
||||
"led_int_6" BEL "led_int_7" BEL "prescaler_d" BEL "t_reset_d3" BEL
|
||||
"prescaler_0" BEL "prescaler_1" BEL "prescaler_2" BEL "prescaler_3"
|
||||
BEL "prescaler_4" BEL "prescaler_5" BEL "prescaler_6" BEL
|
||||
"prescaler_7" BEL "prescaler_8" BEL "prescaler_9" BEL "prescaler_10"
|
||||
BEL "prescaler_11" BEL "prescaler_12" BEL "prescaler_13" BEL
|
||||
"prescaler_14" BEL "prescaler_15" BEL "prescaler_16" BEL
|
||||
"prescaler_17" BEL "prescaler_18" BEL "prescaler_19" BEL
|
||||
"prescaler_20" BEL "prescaler_21" BEL "SPARTAN6PLL/clkout1_buf" BEL
|
||||
"BIU_CORE/nmi_counter_25" BEL "BIU_CORE/nmi_counter_24" BEL
|
||||
"BIU_CORE/nmi_counter_23" BEL "BIU_CORE/nmi_counter_22" BEL
|
||||
"BIU_CORE/nmi_counter_21" BEL "BIU_CORE/nmi_counter_20" BEL
|
||||
"BIU_CORE/nmi_counter_19" BEL "BIU_CORE/nmi_counter_18" BEL
|
||||
"BIU_CORE/nmi_counter_17" BEL "BIU_CORE/nmi_counter_16" BEL
|
||||
"BIU_CORE/nmi_counter_15" BEL "BIU_CORE/nmi_counter_14" BEL
|
||||
"BIU_CORE/nmi_counter_13" BEL "BIU_CORE/nmi_counter_12" BEL
|
||||
"BIU_CORE/nmi_counter_11" BEL "BIU_CORE/nmi_counter_10" BEL
|
||||
"BIU_CORE/nmi_counter_9" BEL "BIU_CORE/nmi_counter_8" BEL
|
||||
"BIU_CORE/nmi_counter_7" BEL "BIU_CORE/nmi_counter_6" BEL
|
||||
"BIU_CORE/nmi_counter_5" BEL "BIU_CORE/nmi_counter_4" BEL
|
||||
"BIU_CORE/nmi_counter_3" BEL "BIU_CORE/nmi_counter_2" BEL
|
||||
"BIU_CORE/nmi_counter_1" BEL "BIU_CORE/nmi_counter_0" BEL
|
||||
"BIU_CORE/pfq_addr_out_15" BEL "BIU_CORE/pfq_addr_out_14" BEL
|
||||
"BIU_CORE/pfq_addr_out_13" BEL "BIU_CORE/pfq_addr_out_12" BEL
|
||||
"BIU_CORE/pfq_addr_out_11" BEL "BIU_CORE/pfq_addr_out_10" BEL
|
||||
"BIU_CORE/pfq_addr_out_9" BEL "BIU_CORE/pfq_addr_out_8" BEL
|
||||
"BIU_CORE/pfq_addr_out_7" BEL "BIU_CORE/pfq_addr_out_6" BEL
|
||||
"BIU_CORE/pfq_addr_out_5" BEL "BIU_CORE/pfq_addr_out_4" BEL
|
||||
"BIU_CORE/pfq_addr_out_3" BEL "BIU_CORE/pfq_addr_out_2" BEL
|
||||
"BIU_CORE/pfq_addr_out_1" BEL "BIU_CORE/pfq_addr_out_0" BEL
|
||||
"BIU_CORE/pfq_addr_in_15" BEL "BIU_CORE/pfq_addr_in_14" BEL
|
||||
"BIU_CORE/pfq_addr_in_13" BEL "BIU_CORE/pfq_addr_in_12" BEL
|
||||
"BIU_CORE/pfq_addr_in_11" BEL "BIU_CORE/pfq_addr_in_10" BEL
|
||||
"BIU_CORE/pfq_addr_in_9" BEL "BIU_CORE/pfq_addr_in_8" BEL
|
||||
"BIU_CORE/pfq_addr_in_7" BEL "BIU_CORE/pfq_addr_in_6" BEL
|
||||
"BIU_CORE/pfq_addr_in_5" BEL "BIU_CORE/pfq_addr_in_4" BEL
|
||||
"BIU_CORE/pfq_addr_in_3" BEL "BIU_CORE/pfq_addr_in_2" BEL
|
||||
"BIU_CORE/pfq_addr_in_1" BEL "BIU_CORE/pfq_addr_in_0" BEL
|
||||
"BIU_CORE/clock_cycle_counter_12" BEL
|
||||
"BIU_CORE/clock_cycle_counter_11" BEL
|
||||
"BIU_CORE/clock_cycle_counter_10" BEL "BIU_CORE/clock_cycle_counter_9"
|
||||
BEL "BIU_CORE/clock_cycle_counter_8" BEL
|
||||
"BIU_CORE/clock_cycle_counter_7" BEL "BIU_CORE/clock_cycle_counter_6"
|
||||
BEL "BIU_CORE/clock_cycle_counter_5" BEL
|
||||
"BIU_CORE/clock_cycle_counter_4" BEL "BIU_CORE/clock_cycle_counter_3"
|
||||
BEL "BIU_CORE/clock_cycle_counter_2" BEL
|
||||
"BIU_CORE/clock_cycle_counter_1" BEL "BIU_CORE/clock_cycle_counter_0"
|
||||
BEL "BIU_CORE/nmi_d5" BEL "BIU_CORE/s_bits_2" BEL "BIU_CORE/s_bits_1"
|
||||
BEL "BIU_CORE/s_bits_0" BEL "BIU_CORE/ALE" BEL
|
||||
"BIU_CORE/pfq_top_byte_int_d1_7" BEL "BIU_CORE/pfq_top_byte_int_d1_6"
|
||||
BEL "BIU_CORE/pfq_top_byte_int_d1_5" BEL
|
||||
"BIU_CORE/pfq_top_byte_int_d1_4" BEL "BIU_CORE/pfq_top_byte_int_d1_3"
|
||||
BEL "BIU_CORE/pfq_top_byte_int_d1_2" BEL
|
||||
"BIU_CORE/pfq_top_byte_int_d1_1" BEL "BIU_CORE/pfq_top_byte_int_d1_0"
|
||||
BEL "BIU_CORE/nmi_d4" BEL "BIU_CORE/clk_d4" BEL
|
||||
"BIU_CORE/pfq_addr_out_d1_15" BEL "BIU_CORE/pfq_addr_out_d1_14" BEL
|
||||
"BIU_CORE/pfq_addr_out_d1_13" BEL "BIU_CORE/pfq_addr_out_d1_12" BEL
|
||||
"BIU_CORE/pfq_addr_out_d1_11" BEL "BIU_CORE/pfq_addr_out_d1_10" BEL
|
||||
"BIU_CORE/pfq_addr_out_d1_9" BEL "BIU_CORE/pfq_addr_out_d1_8" BEL
|
||||
"BIU_CORE/pfq_addr_out_d1_7" BEL "BIU_CORE/pfq_addr_out_d1_6" BEL
|
||||
"BIU_CORE/pfq_addr_out_d1_5" BEL "BIU_CORE/pfq_addr_out_d1_4" BEL
|
||||
"BIU_CORE/pfq_addr_out_d1_3" BEL "BIU_CORE/pfq_addr_out_d1_2" BEL
|
||||
"BIU_CORE/pfq_addr_out_d1_1" BEL "BIU_CORE/pfq_addr_out_d1_0" BEL
|
||||
"BIU_CORE/intr_d3" BEL "BIU_CORE/nmi_d3" BEL "BIU_CORE/clk_d3" BEL
|
||||
"BIU_CORE/pfq_entry2_7" BEL "BIU_CORE/pfq_entry2_6" BEL
|
||||
"BIU_CORE/pfq_entry2_5" BEL "BIU_CORE/pfq_entry2_4" BEL
|
||||
"BIU_CORE/pfq_entry2_3" BEL "BIU_CORE/pfq_entry2_2" BEL
|
||||
"BIU_CORE/pfq_entry2_1" BEL "BIU_CORE/pfq_entry2_0" BEL
|
||||
"BIU_CORE/pfq_entry1_7" BEL "BIU_CORE/pfq_entry1_6" BEL
|
||||
"BIU_CORE/pfq_entry1_5" BEL "BIU_CORE/pfq_entry1_4" BEL
|
||||
"BIU_CORE/pfq_entry1_3" BEL "BIU_CORE/pfq_entry1_2" BEL
|
||||
"BIU_CORE/pfq_entry1_1" BEL "BIU_CORE/pfq_entry1_0" BEL
|
||||
"BIU_CORE/pfq_entry3_7" BEL "BIU_CORE/pfq_entry3_6" BEL
|
||||
"BIU_CORE/pfq_entry3_5" BEL "BIU_CORE/pfq_entry3_4" BEL
|
||||
"BIU_CORE/pfq_entry3_3" BEL "BIU_CORE/pfq_entry3_2" BEL
|
||||
"BIU_CORE/pfq_entry3_1" BEL "BIU_CORE/pfq_entry3_0" BEL
|
||||
"BIU_CORE/pfq_entry0_7" BEL "BIU_CORE/pfq_entry0_6" BEL
|
||||
"BIU_CORE/pfq_entry0_5" BEL "BIU_CORE/pfq_entry0_4" BEL
|
||||
"BIU_CORE/pfq_entry0_3" BEL "BIU_CORE/pfq_entry0_2" BEL
|
||||
"BIU_CORE/pfq_entry0_1" BEL "BIU_CORE/pfq_entry0_0" BEL
|
||||
"BIU_CORE/INTA_n" BEL "BIU_CORE/DEN" BEL "BIU_CORE/RD_n" BEL
|
||||
"BIU_CORE/WR_n" BEL "BIU_CORE/DTR" BEL "BIU_CORE/IOM" BEL
|
||||
"BIU_CORE/intr_d2" BEL "BIU_CORE/clk_d2" BEL "BIU_CORE/SRAM_A_18" BEL
|
||||
"BIU_CORE/SRAM_A_17" BEL "BIU_CORE/SRAM_A_16" BEL "BIU_CORE/SRAM_A_15"
|
||||
BEL "BIU_CORE/SRAM_A_14" BEL "BIU_CORE/SRAM_A_13" BEL
|
||||
"BIU_CORE/SRAM_A_12" BEL "BIU_CORE/SRAM_A_11" BEL "BIU_CORE/SRAM_A_10"
|
||||
BEL "BIU_CORE/SRAM_A_9" BEL "BIU_CORE/SRAM_A_8" BEL
|
||||
"BIU_CORE/SRAM_A_7" BEL "BIU_CORE/SRAM_A_6" BEL "BIU_CORE/SRAM_A_5"
|
||||
BEL "BIU_CORE/SRAM_A_4" BEL "BIU_CORE/SRAM_A_3" BEL
|
||||
"BIU_CORE/SRAM_A_2" BEL "BIU_CORE/SRAM_A_1" BEL "BIU_CORE/SRAM_A_0"
|
||||
BEL "BIU_CORE/latched_data_in_7" BEL "BIU_CORE/latched_data_in_6" BEL
|
||||
"BIU_CORE/latched_data_in_5" BEL "BIU_CORE/latched_data_in_4" BEL
|
||||
"BIU_CORE/latched_data_in_3" BEL "BIU_CORE/latched_data_in_2" BEL
|
||||
"BIU_CORE/latched_data_in_1" BEL "BIU_CORE/latched_data_in_0" BEL
|
||||
"BIU_CORE/biu_return_data_int_7" BEL "BIU_CORE/biu_return_data_int_6"
|
||||
BEL "BIU_CORE/biu_return_data_int_5" BEL
|
||||
"BIU_CORE/biu_return_data_int_4" BEL "BIU_CORE/biu_return_data_int_3"
|
||||
BEL "BIU_CORE/biu_return_data_int_2" BEL
|
||||
"BIU_CORE/biu_return_data_int_1" BEL "BIU_CORE/biu_return_data_int_0"
|
||||
BEL "BIU_CORE/addr_out_temp_19" BEL "BIU_CORE/addr_out_temp_18" BEL
|
||||
"BIU_CORE/addr_out_temp_17" BEL "BIU_CORE/addr_out_temp_16" BEL
|
||||
"BIU_CORE/addr_out_temp_15" BEL "BIU_CORE/addr_out_temp_14" BEL
|
||||
"BIU_CORE/addr_out_temp_13" BEL "BIU_CORE/addr_out_temp_12" BEL
|
||||
"BIU_CORE/addr_out_temp_11" BEL "BIU_CORE/addr_out_temp_10" BEL
|
||||
"BIU_CORE/addr_out_temp_9" BEL "BIU_CORE/addr_out_temp_8" BEL
|
||||
"BIU_CORE/addr_out_temp_7" BEL "BIU_CORE/addr_out_temp_6" BEL
|
||||
"BIU_CORE/addr_out_temp_5" BEL "BIU_CORE/addr_out_temp_4" BEL
|
||||
"BIU_CORE/addr_out_temp_3" BEL "BIU_CORE/addr_out_temp_2" BEL
|
||||
"BIU_CORE/addr_out_temp_1" BEL "BIU_CORE/addr_out_temp_0" BEL
|
||||
"BIU_CORE/AD_OUT_19" BEL "BIU_CORE/AD_OUT_18" BEL "BIU_CORE/AD_OUT_17"
|
||||
BEL "BIU_CORE/AD_OUT_16" BEL "BIU_CORE/AD_OUT_15" BEL
|
||||
"BIU_CORE/AD_OUT_14" BEL "BIU_CORE/AD_OUT_13" BEL "BIU_CORE/AD_OUT_12"
|
||||
BEL "BIU_CORE/AD_OUT_11" BEL "BIU_CORE/AD_OUT_10" BEL
|
||||
"BIU_CORE/AD_OUT_9" BEL "BIU_CORE/AD_OUT_8" BEL "BIU_CORE/AD_OUT_7"
|
||||
BEL "BIU_CORE/AD_OUT_6" BEL "BIU_CORE/AD_OUT_5" BEL
|
||||
"BIU_CORE/AD_OUT_4" BEL "BIU_CORE/AD_OUT_3" BEL "BIU_CORE/AD_OUT_2"
|
||||
BEL "BIU_CORE/AD_OUT_1" BEL "BIU_CORE/AD_OUT_0" BEL
|
||||
"BIU_CORE/SRAM_D_OUT_7" BEL "BIU_CORE/SRAM_D_OUT_6" BEL
|
||||
"BIU_CORE/SRAM_D_OUT_5" BEL "BIU_CORE/SRAM_D_OUT_4" BEL
|
||||
"BIU_CORE/SRAM_D_OUT_3" BEL "BIU_CORE/SRAM_D_OUT_2" BEL
|
||||
"BIU_CORE/SRAM_D_OUT_1" BEL "BIU_CORE/SRAM_D_OUT_0" BEL
|
||||
"BIU_CORE/mcl6_feature_1" BEL "BIU_CORE/mcl6_feature_0" BEL
|
||||
"BIU_CORE/sram_select" BEL "BIU_CORE/SRAM_WE_n" BEL
|
||||
"BIU_CORE/SRAM_OE_n" BEL "BIU_CORE/biu_state_7" BEL
|
||||
"BIU_CORE/biu_state_6" BEL "BIU_CORE/biu_state_5" BEL
|
||||
"BIU_CORE/biu_state_4" BEL "BIU_CORE/biu_state_3" BEL
|
||||
"BIU_CORE/biu_state_2" BEL "BIU_CORE/biu_state_1" BEL
|
||||
"BIU_CORE/biu_state_0" BEL "BIU_CORE/wr_n_int" BEL "BIU_CORE/rd_n_int"
|
||||
BEL "BIU_CORE/den_int" BEL "BIU_CORE/inta_n_int" BEL "BIU_CORE/clk_d1"
|
||||
BEL "BIU_CORE/dtr_int" BEL "BIU_CORE/SRAM_D_OE" BEL "BIU_CORE/AD_OE"
|
||||
BEL "BIU_CORE/intr_d1" BEL "BIU_CORE/byte_num" BEL "BIU_CORE/ready_d1"
|
||||
BEL "BIU_CORE/biu_done_int" BEL "BIU_CORE/eu_biu_req_d1" BEL
|
||||
"BIU_CORE/biu_return_data_int_9" BEL "BIU_CORE/biu_return_data_int_10"
|
||||
BEL "BIU_CORE/biu_return_data_int_8" BEL
|
||||
"BIU_CORE/biu_return_data_int_12" BEL
|
||||
"BIU_CORE/biu_return_data_int_13" BEL
|
||||
"BIU_CORE/biu_return_data_int_11" BEL
|
||||
"BIU_CORE/biu_return_data_int_15" BEL "BIU_CORE/pfq_write" BEL
|
||||
"BIU_CORE/biu_return_data_int_14" BEL "BIU_CORE/nmi_d1" BEL
|
||||
"BIU_CORE/eu_register_r3_d_15" BEL "BIU_CORE/eu_register_r3_d_14" BEL
|
||||
"BIU_CORE/eu_register_r3_d_13" BEL "BIU_CORE/eu_register_r3_d_12" BEL
|
||||
"BIU_CORE/eu_register_r3_d_11" BEL "BIU_CORE/eu_register_r3_d_10" BEL
|
||||
"BIU_CORE/eu_register_r3_d_9" BEL "BIU_CORE/eu_register_r3_d_8" BEL
|
||||
"BIU_CORE/eu_register_r3_d_7" BEL "BIU_CORE/eu_register_r3_d_6" BEL
|
||||
"BIU_CORE/eu_register_r3_d_5" BEL "BIU_CORE/eu_register_r3_d_4" BEL
|
||||
"BIU_CORE/eu_register_r3_d_3" BEL "BIU_CORE/eu_register_r3_d_2" BEL
|
||||
"BIU_CORE/eu_register_r3_d_1" BEL "BIU_CORE/eu_register_r3_d_0" BEL
|
||||
"BIU_CORE/biu_register_reg_15" BEL "BIU_CORE/biu_register_reg_14" BEL
|
||||
"BIU_CORE/biu_register_reg_13" BEL "BIU_CORE/biu_register_reg_12" BEL
|
||||
"BIU_CORE/biu_register_reg_11" BEL "BIU_CORE/biu_register_reg_10" BEL
|
||||
"BIU_CORE/biu_register_reg_9" BEL "BIU_CORE/biu_register_reg_8" BEL
|
||||
"BIU_CORE/biu_register_reg_7" BEL "BIU_CORE/biu_register_reg_6" BEL
|
||||
"BIU_CORE/biu_register_reg_5" BEL "BIU_CORE/biu_register_reg_4" BEL
|
||||
"BIU_CORE/biu_register_reg_3" BEL "BIU_CORE/biu_register_reg_2" BEL
|
||||
"BIU_CORE/biu_register_reg_1" BEL "BIU_CORE/biu_register_reg_0" BEL
|
||||
"BIU_CORE/biu_register_rm_15" BEL "BIU_CORE/biu_register_rm_14" BEL
|
||||
"BIU_CORE/biu_register_rm_13" BEL "BIU_CORE/biu_register_rm_12" BEL
|
||||
"BIU_CORE/biu_register_rm_11" BEL "BIU_CORE/biu_register_rm_10" BEL
|
||||
"BIU_CORE/biu_register_rm_9" BEL "BIU_CORE/biu_register_rm_8" BEL
|
||||
"BIU_CORE/biu_register_rm_7" BEL "BIU_CORE/biu_register_rm_6" BEL
|
||||
"BIU_CORE/biu_register_rm_5" BEL "BIU_CORE/biu_register_rm_4" BEL
|
||||
"BIU_CORE/biu_register_rm_3" BEL "BIU_CORE/biu_register_rm_2" BEL
|
||||
"BIU_CORE/biu_register_rm_1" BEL "BIU_CORE/biu_register_rm_0" BEL
|
||||
"BIU_CORE/biu_register_cs_15" BEL "BIU_CORE/biu_register_cs_14" BEL
|
||||
"BIU_CORE/biu_register_cs_13" BEL "BIU_CORE/biu_register_cs_12" BEL
|
||||
"BIU_CORE/biu_register_cs_11" BEL "BIU_CORE/biu_register_cs_10" BEL
|
||||
"BIU_CORE/biu_register_cs_9" BEL "BIU_CORE/biu_register_cs_8" BEL
|
||||
"BIU_CORE/biu_register_cs_7" BEL "BIU_CORE/biu_register_cs_6" BEL
|
||||
"BIU_CORE/biu_register_cs_5" BEL "BIU_CORE/biu_register_cs_4" BEL
|
||||
"BIU_CORE/biu_register_cs_3" BEL "BIU_CORE/biu_register_cs_2" BEL
|
||||
"BIU_CORE/biu_register_cs_1" BEL "BIU_CORE/biu_register_cs_0" BEL
|
||||
"BIU_CORE/biu_register_ds_15" BEL "BIU_CORE/biu_register_ds_14" BEL
|
||||
"BIU_CORE/biu_register_ds_13" BEL "BIU_CORE/biu_register_ds_12" BEL
|
||||
"BIU_CORE/biu_register_ds_11" BEL "BIU_CORE/biu_register_ds_10" BEL
|
||||
"BIU_CORE/biu_register_ds_9" BEL "BIU_CORE/biu_register_ds_8" BEL
|
||||
"BIU_CORE/biu_register_ds_7" BEL "BIU_CORE/biu_register_ds_6" BEL
|
||||
"BIU_CORE/biu_register_ds_5" BEL "BIU_CORE/biu_register_ds_4" BEL
|
||||
"BIU_CORE/biu_register_ds_3" BEL "BIU_CORE/biu_register_ds_2" BEL
|
||||
"BIU_CORE/biu_register_ds_1" BEL "BIU_CORE/biu_register_ds_0" BEL
|
||||
"BIU_CORE/biu_register_ss_15" BEL "BIU_CORE/biu_register_ss_14" BEL
|
||||
"BIU_CORE/biu_register_ss_13" BEL "BIU_CORE/biu_register_ss_12" BEL
|
||||
"BIU_CORE/biu_register_ss_11" BEL "BIU_CORE/biu_register_ss_10" BEL
|
||||
"BIU_CORE/biu_register_ss_9" BEL "BIU_CORE/biu_register_ss_8" BEL
|
||||
"BIU_CORE/biu_register_ss_7" BEL "BIU_CORE/biu_register_ss_6" BEL
|
||||
"BIU_CORE/biu_register_ss_5" BEL "BIU_CORE/biu_register_ss_4" BEL
|
||||
"BIU_CORE/biu_register_ss_3" BEL "BIU_CORE/biu_register_ss_2" BEL
|
||||
"BIU_CORE/biu_register_ss_1" BEL "BIU_CORE/biu_register_ss_0" BEL
|
||||
"BIU_CORE/biu_register_es_15" BEL "BIU_CORE/biu_register_es_14" BEL
|
||||
"BIU_CORE/biu_register_es_13" BEL "BIU_CORE/biu_register_es_12" BEL
|
||||
"BIU_CORE/biu_register_es_11" BEL "BIU_CORE/biu_register_es_10" BEL
|
||||
"BIU_CORE/biu_register_es_9" BEL "BIU_CORE/biu_register_es_8" BEL
|
||||
"BIU_CORE/biu_register_es_7" BEL "BIU_CORE/biu_register_es_6" BEL
|
||||
"BIU_CORE/biu_register_es_5" BEL "BIU_CORE/biu_register_es_4" BEL
|
||||
"BIU_CORE/biu_register_es_3" BEL "BIU_CORE/biu_register_es_2" BEL
|
||||
"BIU_CORE/biu_register_es_1" BEL "BIU_CORE/biu_register_es_0" BEL
|
||||
"BIU_CORE/ad_in_int_7" BEL "BIU_CORE/ad_in_int_6" BEL
|
||||
"BIU_CORE/ad_in_int_5" BEL "BIU_CORE/ad_in_int_4" BEL
|
||||
"BIU_CORE/ad_in_int_3" BEL "BIU_CORE/ad_in_int_2" BEL
|
||||
"BIU_CORE/ad_in_int_1" BEL "BIU_CORE/ad_in_int_0" BEL
|
||||
"EU_CORE/eu_register_r0_15" BEL "EU_CORE/eu_register_r0_14" BEL
|
||||
"EU_CORE/eu_register_r0_13" BEL "EU_CORE/eu_register_r0_12" BEL
|
||||
"EU_CORE/eu_register_r0_11" BEL "EU_CORE/eu_register_r0_10" BEL
|
||||
"EU_CORE/eu_register_r0_9" BEL "EU_CORE/eu_register_r0_8" BEL
|
||||
"EU_CORE/eu_register_r0_7" BEL "EU_CORE/eu_register_r0_6" BEL
|
||||
"EU_CORE/eu_register_r0_5" BEL "EU_CORE/eu_register_r0_4" BEL
|
||||
"EU_CORE/eu_register_r0_3" BEL "EU_CORE/eu_register_r0_2" BEL
|
||||
"EU_CORE/eu_register_r0_1" BEL "EU_CORE/eu_register_r0_0" BEL
|
||||
"EU_CORE/eu_alu_last_result_15" BEL "EU_CORE/eu_alu_last_result_14"
|
||||
BEL "EU_CORE/eu_alu_last_result_13" BEL
|
||||
"EU_CORE/eu_alu_last_result_12" BEL "EU_CORE/eu_alu_last_result_11"
|
||||
BEL "EU_CORE/eu_alu_last_result_10" BEL "EU_CORE/eu_alu_last_result_9"
|
||||
BEL "EU_CORE/eu_alu_last_result_8" BEL "EU_CORE/eu_alu_last_result_7"
|
||||
BEL "EU_CORE/eu_alu_last_result_6" BEL "EU_CORE/eu_alu_last_result_5"
|
||||
BEL "EU_CORE/eu_alu_last_result_4" BEL "EU_CORE/eu_alu_last_result_3"
|
||||
BEL "EU_CORE/eu_alu_last_result_2" BEL "EU_CORE/eu_alu_last_result_1"
|
||||
BEL "EU_CORE/eu_alu_last_result_0" BEL "EU_CORE/eu_rom_address_12" BEL
|
||||
"EU_CORE/eu_rom_address_11" BEL "EU_CORE/eu_rom_address_10" BEL
|
||||
"EU_CORE/eu_rom_address_9" BEL "EU_CORE/eu_rom_address_8" BEL
|
||||
"EU_CORE/eu_rom_address_7" BEL "EU_CORE/eu_rom_address_6" BEL
|
||||
"EU_CORE/eu_rom_address_5" BEL "EU_CORE/eu_rom_address_4" BEL
|
||||
"EU_CORE/eu_rom_address_3" BEL "EU_CORE/eu_rom_address_2" BEL
|
||||
"EU_CORE/eu_rom_address_1" BEL "EU_CORE/eu_rom_address_0" BEL
|
||||
"EU_CORE/eu_calling_address_51" BEL "EU_CORE/eu_calling_address_50"
|
||||
BEL "EU_CORE/eu_calling_address_49" BEL
|
||||
"EU_CORE/eu_calling_address_48" BEL "EU_CORE/eu_calling_address_47"
|
||||
BEL "EU_CORE/eu_calling_address_46" BEL
|
||||
"EU_CORE/eu_calling_address_45" BEL "EU_CORE/eu_calling_address_44"
|
||||
BEL "EU_CORE/eu_calling_address_43" BEL
|
||||
"EU_CORE/eu_calling_address_42" BEL "EU_CORE/eu_calling_address_41"
|
||||
BEL "EU_CORE/eu_calling_address_40" BEL
|
||||
"EU_CORE/eu_calling_address_39" BEL "EU_CORE/eu_calling_address_38"
|
||||
BEL "EU_CORE/eu_calling_address_37" BEL
|
||||
"EU_CORE/eu_calling_address_36" BEL "EU_CORE/eu_calling_address_35"
|
||||
BEL "EU_CORE/eu_calling_address_34" BEL
|
||||
"EU_CORE/eu_calling_address_33" BEL "EU_CORE/eu_calling_address_32"
|
||||
BEL "EU_CORE/eu_calling_address_31" BEL
|
||||
"EU_CORE/eu_calling_address_30" BEL "EU_CORE/eu_calling_address_29"
|
||||
BEL "EU_CORE/eu_calling_address_28" BEL
|
||||
"EU_CORE/eu_calling_address_27" BEL "EU_CORE/eu_calling_address_26"
|
||||
BEL "EU_CORE/eu_calling_address_25" BEL
|
||||
"EU_CORE/eu_calling_address_24" BEL "EU_CORE/eu_calling_address_23"
|
||||
BEL "EU_CORE/eu_calling_address_22" BEL
|
||||
"EU_CORE/eu_calling_address_21" BEL "EU_CORE/eu_calling_address_20"
|
||||
BEL "EU_CORE/eu_calling_address_19" BEL
|
||||
"EU_CORE/eu_calling_address_18" BEL "EU_CORE/eu_calling_address_17"
|
||||
BEL "EU_CORE/eu_calling_address_16" BEL
|
||||
"EU_CORE/eu_calling_address_15" BEL "EU_CORE/eu_calling_address_14"
|
||||
BEL "EU_CORE/eu_calling_address_13" BEL
|
||||
"EU_CORE/eu_calling_address_12" BEL "EU_CORE/eu_calling_address_11"
|
||||
BEL "EU_CORE/eu_calling_address_10" BEL "EU_CORE/eu_calling_address_9"
|
||||
BEL "EU_CORE/eu_calling_address_8" BEL "EU_CORE/eu_calling_address_7"
|
||||
BEL "EU_CORE/eu_calling_address_6" BEL "EU_CORE/eu_calling_address_5"
|
||||
BEL "EU_CORE/eu_calling_address_4" BEL "EU_CORE/eu_calling_address_3"
|
||||
BEL "EU_CORE/eu_calling_address_2" BEL "EU_CORE/eu_calling_address_1"
|
||||
BEL "EU_CORE/eu_calling_address_0" BEL "EU_CORE/eu_add_overflow8" BEL
|
||||
"EU_CORE/eu_add_overflow16" BEL "EU_CORE/eu_flag_t_d" BEL
|
||||
"EU_CORE/eu_biu_dataout_15" BEL "EU_CORE/eu_biu_dataout_14" BEL
|
||||
"EU_CORE/eu_biu_dataout_13" BEL "EU_CORE/eu_biu_dataout_12" BEL
|
||||
"EU_CORE/eu_biu_dataout_11" BEL "EU_CORE/eu_biu_dataout_10" BEL
|
||||
"EU_CORE/eu_biu_dataout_9" BEL "EU_CORE/eu_biu_dataout_8" BEL
|
||||
"EU_CORE/eu_biu_dataout_7" BEL "EU_CORE/eu_biu_dataout_6" BEL
|
||||
"EU_CORE/eu_biu_dataout_5" BEL "EU_CORE/eu_biu_dataout_4" BEL
|
||||
"EU_CORE/eu_biu_dataout_3" BEL "EU_CORE/eu_biu_dataout_2" BEL
|
||||
"EU_CORE/eu_biu_dataout_1" BEL "EU_CORE/eu_biu_dataout_0" BEL
|
||||
"EU_CORE/eu_register_r3_15" BEL "EU_CORE/eu_register_r3_14" BEL
|
||||
"EU_CORE/eu_register_r3_13" BEL "EU_CORE/eu_register_r3_12" BEL
|
||||
"EU_CORE/eu_register_r3_11" BEL "EU_CORE/eu_register_r3_10" BEL
|
||||
"EU_CORE/eu_register_r3_9" BEL "EU_CORE/eu_register_r3_8" BEL
|
||||
"EU_CORE/eu_register_r3_7" BEL "EU_CORE/eu_register_r3_6" BEL
|
||||
"EU_CORE/eu_register_r3_5" BEL "EU_CORE/eu_register_r3_4" BEL
|
||||
"EU_CORE/eu_register_r3_3" BEL "EU_CORE/eu_register_r3_2" BEL
|
||||
"EU_CORE/eu_register_r3_1" BEL "EU_CORE/eu_register_r3_0" BEL
|
||||
"EU_CORE/eu_register_r2_15" BEL "EU_CORE/eu_register_r2_14" BEL
|
||||
"EU_CORE/eu_register_r2_13" BEL "EU_CORE/eu_register_r2_12" BEL
|
||||
"EU_CORE/eu_register_r2_11" BEL "EU_CORE/eu_register_r2_10" BEL
|
||||
"EU_CORE/eu_register_r2_9" BEL "EU_CORE/eu_register_r2_8" BEL
|
||||
"EU_CORE/eu_register_r2_7" BEL "EU_CORE/eu_register_r2_6" BEL
|
||||
"EU_CORE/eu_register_r2_5" BEL "EU_CORE/eu_register_r2_4" BEL
|
||||
"EU_CORE/eu_register_r2_3" BEL "EU_CORE/eu_register_r2_2" BEL
|
||||
"EU_CORE/eu_register_r2_1" BEL "EU_CORE/eu_register_r2_0" BEL
|
||||
"EU_CORE/eu_biu_command_15" BEL "EU_CORE/eu_biu_command_14" BEL
|
||||
"EU_CORE/eu_biu_command_13" BEL "EU_CORE/eu_biu_command_12" BEL
|
||||
"EU_CORE/eu_biu_command_11" BEL "EU_CORE/eu_biu_command_10" BEL
|
||||
"EU_CORE/eu_biu_command_9" BEL "EU_CORE/eu_biu_command_8" BEL
|
||||
"EU_CORE/eu_biu_command_7" BEL "EU_CORE/eu_biu_command_6" BEL
|
||||
"EU_CORE/eu_biu_command_5" BEL "EU_CORE/eu_biu_command_4" BEL
|
||||
"EU_CORE/eu_biu_command_3" BEL "EU_CORE/eu_biu_command_2" BEL
|
||||
"EU_CORE/eu_biu_command_1" BEL "EU_CORE/eu_biu_command_0" BEL
|
||||
"EU_CORE/eu_flags_15" BEL "EU_CORE/eu_flags_14" BEL
|
||||
"EU_CORE/eu_flags_13" BEL "EU_CORE/eu_flags_12" BEL
|
||||
"EU_CORE/eu_flags_11" BEL "EU_CORE/eu_flags_10" BEL
|
||||
"EU_CORE/eu_flags_9" BEL "EU_CORE/eu_flags_8" BEL "EU_CORE/eu_flags_7"
|
||||
BEL "EU_CORE/eu_flags_6" BEL "EU_CORE/eu_flags_5" BEL
|
||||
"EU_CORE/eu_flags_4" BEL "EU_CORE/eu_flags_3" BEL "EU_CORE/eu_flags_2"
|
||||
BEL "EU_CORE/eu_flags_1" BEL "EU_CORE/eu_flags_0" BEL
|
||||
"EU_CORE/eu_register_r1_15" BEL "EU_CORE/eu_register_r1_14" BEL
|
||||
"EU_CORE/eu_register_r1_13" BEL "EU_CORE/eu_register_r1_12" BEL
|
||||
"EU_CORE/eu_register_r1_11" BEL "EU_CORE/eu_register_r1_10" BEL
|
||||
"EU_CORE/eu_register_r1_9" BEL "EU_CORE/eu_register_r1_8" BEL
|
||||
"EU_CORE/eu_register_r1_7" BEL "EU_CORE/eu_register_r1_6" BEL
|
||||
"EU_CORE/eu_register_r1_5" BEL "EU_CORE/eu_register_r1_4" BEL
|
||||
"EU_CORE/eu_register_r1_3" BEL "EU_CORE/eu_register_r1_2" BEL
|
||||
"EU_CORE/eu_register_r1_1" BEL "EU_CORE/eu_register_r1_0" BEL
|
||||
"EU_CORE/eu_register_si_15" BEL "EU_CORE/eu_register_si_14" BEL
|
||||
"EU_CORE/eu_register_si_13" BEL "EU_CORE/eu_register_si_12" BEL
|
||||
"EU_CORE/eu_register_si_11" BEL "EU_CORE/eu_register_si_10" BEL
|
||||
"EU_CORE/eu_register_si_9" BEL "EU_CORE/eu_register_si_8" BEL
|
||||
"EU_CORE/eu_register_si_7" BEL "EU_CORE/eu_register_si_6" BEL
|
||||
"EU_CORE/eu_register_si_5" BEL "EU_CORE/eu_register_si_4" BEL
|
||||
"EU_CORE/eu_register_si_3" BEL "EU_CORE/eu_register_si_2" BEL
|
||||
"EU_CORE/eu_register_si_1" BEL "EU_CORE/eu_register_si_0" BEL
|
||||
"EU_CORE/eu_register_bp_15" BEL "EU_CORE/eu_register_bp_14" BEL
|
||||
"EU_CORE/eu_register_bp_13" BEL "EU_CORE/eu_register_bp_12" BEL
|
||||
"EU_CORE/eu_register_bp_11" BEL "EU_CORE/eu_register_bp_10" BEL
|
||||
"EU_CORE/eu_register_bp_9" BEL "EU_CORE/eu_register_bp_8" BEL
|
||||
"EU_CORE/eu_register_bp_7" BEL "EU_CORE/eu_register_bp_6" BEL
|
||||
"EU_CORE/eu_register_bp_5" BEL "EU_CORE/eu_register_bp_4" BEL
|
||||
"EU_CORE/eu_register_bp_3" BEL "EU_CORE/eu_register_bp_2" BEL
|
||||
"EU_CORE/eu_register_bp_1" BEL "EU_CORE/eu_register_bp_0" BEL
|
||||
"EU_CORE/eu_register_di_15" BEL "EU_CORE/eu_register_di_14" BEL
|
||||
"EU_CORE/eu_register_di_13" BEL "EU_CORE/eu_register_di_12" BEL
|
||||
"EU_CORE/eu_register_di_11" BEL "EU_CORE/eu_register_di_10" BEL
|
||||
"EU_CORE/eu_register_di_9" BEL "EU_CORE/eu_register_di_8" BEL
|
||||
"EU_CORE/eu_register_di_7" BEL "EU_CORE/eu_register_di_6" BEL
|
||||
"EU_CORE/eu_register_di_5" BEL "EU_CORE/eu_register_di_4" BEL
|
||||
"EU_CORE/eu_register_di_3" BEL "EU_CORE/eu_register_di_2" BEL
|
||||
"EU_CORE/eu_register_di_1" BEL "EU_CORE/eu_register_di_0" BEL
|
||||
"EU_CORE/eu_register_sp_15" BEL "EU_CORE/eu_register_sp_14" BEL
|
||||
"EU_CORE/eu_register_sp_13" BEL "EU_CORE/eu_register_sp_12" BEL
|
||||
"EU_CORE/eu_register_sp_11" BEL "EU_CORE/eu_register_sp_10" BEL
|
||||
"EU_CORE/eu_register_sp_9" BEL "EU_CORE/eu_register_sp_8" BEL
|
||||
"EU_CORE/eu_register_sp_7" BEL "EU_CORE/eu_register_sp_6" BEL
|
||||
"EU_CORE/eu_register_sp_5" BEL "EU_CORE/eu_register_sp_4" BEL
|
||||
"EU_CORE/eu_register_sp_3" BEL "EU_CORE/eu_register_sp_2" BEL
|
||||
"EU_CORE/eu_register_sp_1" BEL "EU_CORE/eu_register_sp_0" BEL
|
||||
"EU_CORE/eu_register_dx_15" BEL "EU_CORE/eu_register_dx_14" BEL
|
||||
"EU_CORE/eu_register_dx_13" BEL "EU_CORE/eu_register_dx_12" BEL
|
||||
"EU_CORE/eu_register_dx_11" BEL "EU_CORE/eu_register_dx_10" BEL
|
||||
"EU_CORE/eu_register_dx_9" BEL "EU_CORE/eu_register_dx_8" BEL
|
||||
"EU_CORE/eu_register_dx_7" BEL "EU_CORE/eu_register_dx_6" BEL
|
||||
"EU_CORE/eu_register_dx_5" BEL "EU_CORE/eu_register_dx_4" BEL
|
||||
"EU_CORE/eu_register_dx_3" BEL "EU_CORE/eu_register_dx_2" BEL
|
||||
"EU_CORE/eu_register_dx_1" BEL "EU_CORE/eu_register_dx_0" BEL
|
||||
"EU_CORE/eu_register_cx_15" BEL "EU_CORE/eu_register_cx_14" BEL
|
||||
"EU_CORE/eu_register_cx_13" BEL "EU_CORE/eu_register_cx_12" BEL
|
||||
"EU_CORE/eu_register_cx_11" BEL "EU_CORE/eu_register_cx_10" BEL
|
||||
"EU_CORE/eu_register_cx_9" BEL "EU_CORE/eu_register_cx_8" BEL
|
||||
"EU_CORE/eu_register_cx_7" BEL "EU_CORE/eu_register_cx_6" BEL
|
||||
"EU_CORE/eu_register_cx_5" BEL "EU_CORE/eu_register_cx_4" BEL
|
||||
"EU_CORE/eu_register_cx_3" BEL "EU_CORE/eu_register_cx_2" BEL
|
||||
"EU_CORE/eu_register_cx_1" BEL "EU_CORE/eu_register_cx_0" BEL
|
||||
"EU_CORE/eu_register_bx_15" BEL "EU_CORE/eu_register_bx_14" BEL
|
||||
"EU_CORE/eu_register_bx_13" BEL "EU_CORE/eu_register_bx_12" BEL
|
||||
"EU_CORE/eu_register_bx_11" BEL "EU_CORE/eu_register_bx_10" BEL
|
||||
"EU_CORE/eu_register_bx_9" BEL "EU_CORE/eu_register_bx_8" BEL
|
||||
"EU_CORE/eu_register_bx_7" BEL "EU_CORE/eu_register_bx_6" BEL
|
||||
"EU_CORE/eu_register_bx_5" BEL "EU_CORE/eu_register_bx_4" BEL
|
||||
"EU_CORE/eu_register_bx_3" BEL "EU_CORE/eu_register_bx_2" BEL
|
||||
"EU_CORE/eu_register_bx_1" BEL "EU_CORE/eu_register_bx_0" BEL
|
||||
"EU_CORE/eu_register_ax_15" BEL "EU_CORE/eu_register_ax_14" BEL
|
||||
"EU_CORE/eu_register_ax_13" BEL "EU_CORE/eu_register_ax_12" BEL
|
||||
"EU_CORE/eu_register_ax_11" BEL "EU_CORE/eu_register_ax_10" BEL
|
||||
"EU_CORE/eu_register_ax_9" BEL "EU_CORE/eu_register_ax_8" BEL
|
||||
"EU_CORE/eu_register_ax_7" BEL "EU_CORE/eu_register_ax_6" BEL
|
||||
"EU_CORE/eu_register_ax_5" BEL "EU_CORE/eu_register_ax_4" BEL
|
||||
"EU_CORE/eu_register_ax_3" BEL "EU_CORE/eu_register_ax_2" BEL
|
||||
"EU_CORE/eu_register_ax_1" BEL "EU_CORE/eu_register_ax_0" BEL
|
||||
"EU_CORE/eu_add_aux_carry" BEL "EU_CORE/eu_add_carry8" BEL
|
||||
"EU_CORE/eu_add_carry" BEL "EU_CORE/biu_done_d1" BEL
|
||||
"EU_CORE/eu_stall_pipeline" BEL "t_reset_d4" BEL
|
||||
"BIU_CORE/eu_biu_req_caught" BEL "BIU_CORE/nmi_caught" BEL
|
||||
"EU_CORE/eu_tr_latched" BEL "EU_CORE/biu_done_caught" BEL
|
||||
"BIU_CORE/BIU_INTR" BEL "BIU_CORE/ale_int" BEL "BIU_CORE/iom_int" BEL
|
||||
"EU_CORE/intr_enable_delayed" BEL "BIU_CORE/nmi_d2" BEL "led_go_left"
|
||||
BEL "BIU_CORE/word_cycle" BEL "Mshreg_t_biu_ad_oe_d2" BEL
|
||||
"t_biu_ad_oe_d2" BEL "Mshreg_t_reset_d2" BEL "t_reset_d2" BEL
|
||||
"BIU_CORE/Mshreg_biu_return_data_int_d2_15" BEL
|
||||
"BIU_CORE/biu_return_data_int_d2_15" BEL
|
||||
"BIU_CORE/Mshreg_biu_return_data_int_d2_14" BEL
|
||||
"BIU_CORE/biu_return_data_int_d2_14" BEL
|
||||
"BIU_CORE/Mshreg_biu_return_data_int_d2_13" BEL
|
||||
"BIU_CORE/biu_return_data_int_d2_13" BEL
|
||||
"BIU_CORE/Mshreg_biu_return_data_int_d2_12" BEL
|
||||
"BIU_CORE/biu_return_data_int_d2_12" BEL
|
||||
"BIU_CORE/Mshreg_biu_return_data_int_d2_11" BEL
|
||||
"BIU_CORE/biu_return_data_int_d2_11" BEL
|
||||
"BIU_CORE/Mshreg_biu_return_data_int_d2_10" BEL
|
||||
"BIU_CORE/biu_return_data_int_d2_10" BEL
|
||||
"BIU_CORE/Mshreg_biu_return_data_int_d2_9" BEL
|
||||
"BIU_CORE/biu_return_data_int_d2_9" BEL
|
||||
"BIU_CORE/Mshreg_biu_return_data_int_d2_8" BEL
|
||||
"BIU_CORE/biu_return_data_int_d2_8" BEL
|
||||
"BIU_CORE/Mshreg_biu_return_data_int_d2_7" BEL
|
||||
"BIU_CORE/biu_return_data_int_d2_7" BEL
|
||||
"BIU_CORE/Mshreg_biu_return_data_int_d2_6" BEL
|
||||
"BIU_CORE/biu_return_data_int_d2_6" BEL
|
||||
"BIU_CORE/Mshreg_biu_return_data_int_d2_3" BEL
|
||||
"BIU_CORE/biu_return_data_int_d2_3" BEL
|
||||
"BIU_CORE/Mshreg_biu_return_data_int_d2_5" BEL
|
||||
"BIU_CORE/biu_return_data_int_d2_5" BEL
|
||||
"BIU_CORE/Mshreg_biu_return_data_int_d2_4" BEL
|
||||
"BIU_CORE/biu_return_data_int_d2_4" BEL
|
||||
"BIU_CORE/Mshreg_biu_return_data_int_d2_2" BEL
|
||||
"BIU_CORE/biu_return_data_int_d2_2" BEL
|
||||
"BIU_CORE/Mshreg_biu_return_data_int_d2_1" BEL
|
||||
"BIU_CORE/biu_return_data_int_d2_1" BEL
|
||||
"BIU_CORE/Mshreg_biu_return_data_int_d2_0" BEL
|
||||
"BIU_CORE/biu_return_data_int_d2_0" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_rm_d2_15" BEL
|
||||
"BIU_CORE/biu_register_rm_d2_15" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_rm_d2_12" BEL
|
||||
"BIU_CORE/biu_register_rm_d2_12" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_rm_d2_14" BEL
|
||||
"BIU_CORE/biu_register_rm_d2_14" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_rm_d2_13" BEL
|
||||
"BIU_CORE/biu_register_rm_d2_13" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_rm_d2_11" BEL
|
||||
"BIU_CORE/biu_register_rm_d2_11" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_rm_d2_10" BEL
|
||||
"BIU_CORE/biu_register_rm_d2_10" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_rm_d2_9" BEL
|
||||
"BIU_CORE/biu_register_rm_d2_9" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_rm_d2_8" BEL
|
||||
"BIU_CORE/biu_register_rm_d2_8" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_rm_d2_5" BEL
|
||||
"BIU_CORE/biu_register_rm_d2_5" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_rm_d2_7" BEL
|
||||
"BIU_CORE/biu_register_rm_d2_7" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_rm_d2_6" BEL
|
||||
"BIU_CORE/biu_register_rm_d2_6" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_rm_d2_4" BEL
|
||||
"BIU_CORE/biu_register_rm_d2_4" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_rm_d2_3" BEL
|
||||
"BIU_CORE/biu_register_rm_d2_3" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_rm_d2_2" BEL
|
||||
"BIU_CORE/biu_register_rm_d2_2" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_rm_d2_1" BEL
|
||||
"BIU_CORE/biu_register_rm_d2_1" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ds_d2_14" BEL
|
||||
"BIU_CORE/biu_register_ds_d2_14" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_rm_d2_0" BEL
|
||||
"BIU_CORE/biu_register_rm_d2_0" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ds_d2_15" BEL
|
||||
"BIU_CORE/biu_register_ds_d2_15" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ds_d2_13" BEL
|
||||
"BIU_CORE/biu_register_ds_d2_13" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ds_d2_12" BEL
|
||||
"BIU_CORE/biu_register_ds_d2_12" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ds_d2_11" BEL
|
||||
"BIU_CORE/biu_register_ds_d2_11" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ds_d2_10" BEL
|
||||
"BIU_CORE/biu_register_ds_d2_10" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ds_d2_7" BEL
|
||||
"BIU_CORE/biu_register_ds_d2_7" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ds_d2_9" BEL
|
||||
"BIU_CORE/biu_register_ds_d2_9" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ds_d2_8" BEL
|
||||
"BIU_CORE/biu_register_ds_d2_8" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ds_d2_6" BEL
|
||||
"BIU_CORE/biu_register_ds_d2_6" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ds_d2_5" BEL
|
||||
"BIU_CORE/biu_register_ds_d2_5" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ds_d2_4" BEL
|
||||
"BIU_CORE/biu_register_ds_d2_4" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ds_d2_3" BEL
|
||||
"BIU_CORE/biu_register_ds_d2_3" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ds_d2_0" BEL
|
||||
"BIU_CORE/biu_register_ds_d2_0" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ds_d2_2" BEL
|
||||
"BIU_CORE/biu_register_ds_d2_2" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ds_d2_1" BEL
|
||||
"BIU_CORE/biu_register_ds_d2_1" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_reg_d2_15" BEL
|
||||
"BIU_CORE/biu_register_reg_d2_15" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_reg_d2_14" BEL
|
||||
"BIU_CORE/biu_register_reg_d2_14" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_reg_d2_13" BEL
|
||||
"BIU_CORE/biu_register_reg_d2_13" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_reg_d2_12" BEL
|
||||
"BIU_CORE/biu_register_reg_d2_12" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_reg_d2_9" BEL
|
||||
"BIU_CORE/biu_register_reg_d2_9" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_reg_d2_11" BEL
|
||||
"BIU_CORE/biu_register_reg_d2_11" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_reg_d2_10" BEL
|
||||
"BIU_CORE/biu_register_reg_d2_10" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_reg_d2_8" BEL
|
||||
"BIU_CORE/biu_register_reg_d2_8" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_reg_d2_7" BEL
|
||||
"BIU_CORE/biu_register_reg_d2_7" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_reg_d2_6" BEL
|
||||
"BIU_CORE/biu_register_reg_d2_6" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_reg_d2_5" BEL
|
||||
"BIU_CORE/biu_register_reg_d2_5" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_reg_d2_4" BEL
|
||||
"BIU_CORE/biu_register_reg_d2_4" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_reg_d2_3" BEL
|
||||
"BIU_CORE/biu_register_reg_d2_3" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_reg_d2_2" BEL
|
||||
"BIU_CORE/biu_register_reg_d2_2" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_reg_d2_1" BEL
|
||||
"BIU_CORE/biu_register_reg_d2_1" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_reg_d2_0" BEL
|
||||
"BIU_CORE/biu_register_reg_d2_0" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ss_d2_15" BEL
|
||||
"BIU_CORE/biu_register_ss_d2_15" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ss_d2_14" BEL
|
||||
"BIU_CORE/biu_register_ss_d2_14" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ss_d2_13" BEL
|
||||
"BIU_CORE/biu_register_ss_d2_13" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ss_d2_10" BEL
|
||||
"BIU_CORE/biu_register_ss_d2_10" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ss_d2_12" BEL
|
||||
"BIU_CORE/biu_register_ss_d2_12" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ss_d2_11" BEL
|
||||
"BIU_CORE/biu_register_ss_d2_11" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ss_d2_9" BEL
|
||||
"BIU_CORE/biu_register_ss_d2_9" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ss_d2_8" BEL
|
||||
"BIU_CORE/biu_register_ss_d2_8" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ss_d2_7" BEL
|
||||
"BIU_CORE/biu_register_ss_d2_7" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ss_d2_6" BEL
|
||||
"BIU_CORE/biu_register_ss_d2_6" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ss_d2_3" BEL
|
||||
"BIU_CORE/biu_register_ss_d2_3" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ss_d2_5" BEL
|
||||
"BIU_CORE/biu_register_ss_d2_5" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ss_d2_4" BEL
|
||||
"BIU_CORE/biu_register_ss_d2_4" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ss_d2_2" BEL
|
||||
"BIU_CORE/biu_register_ss_d2_2" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ss_d2_1" BEL
|
||||
"BIU_CORE/biu_register_ss_d2_1" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_ss_d2_0" BEL
|
||||
"BIU_CORE/biu_register_ss_d2_0" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_es_d2_15" BEL
|
||||
"BIU_CORE/biu_register_es_d2_15" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_es_d2_12" BEL
|
||||
"BIU_CORE/biu_register_es_d2_12" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_es_d2_14" BEL
|
||||
"BIU_CORE/biu_register_es_d2_14" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_es_d2_13" BEL
|
||||
"BIU_CORE/biu_register_es_d2_13" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_es_d2_11" BEL
|
||||
"BIU_CORE/biu_register_es_d2_11" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_es_d2_10" BEL
|
||||
"BIU_CORE/biu_register_es_d2_10" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_es_d2_9" BEL
|
||||
"BIU_CORE/biu_register_es_d2_9" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_es_d2_8" BEL
|
||||
"BIU_CORE/biu_register_es_d2_8" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_es_d2_5" BEL
|
||||
"BIU_CORE/biu_register_es_d2_5" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_es_d2_7" BEL
|
||||
"BIU_CORE/biu_register_es_d2_7" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_es_d2_6" BEL
|
||||
"BIU_CORE/biu_register_es_d2_6" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_es_d2_4" BEL
|
||||
"BIU_CORE/biu_register_es_d2_4" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_es_d2_3" BEL
|
||||
"BIU_CORE/biu_register_es_d2_3" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_es_d2_2" BEL
|
||||
"BIU_CORE/biu_register_es_d2_2" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_es_d2_1" BEL
|
||||
"BIU_CORE/biu_register_es_d2_1" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_cs_d2_14" BEL
|
||||
"BIU_CORE/biu_register_cs_d2_14" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_es_d2_0" BEL
|
||||
"BIU_CORE/biu_register_es_d2_0" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_cs_d2_15" BEL
|
||||
"BIU_CORE/biu_register_cs_d2_15" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_cs_d2_13" BEL
|
||||
"BIU_CORE/biu_register_cs_d2_13" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_cs_d2_12" BEL
|
||||
"BIU_CORE/biu_register_cs_d2_12" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_cs_d2_11" BEL
|
||||
"BIU_CORE/biu_register_cs_d2_11" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_cs_d2_10" BEL
|
||||
"BIU_CORE/biu_register_cs_d2_10" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_cs_d2_7" BEL
|
||||
"BIU_CORE/biu_register_cs_d2_7" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_cs_d2_9" BEL
|
||||
"BIU_CORE/biu_register_cs_d2_9" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_cs_d2_8" BEL
|
||||
"BIU_CORE/biu_register_cs_d2_8" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_cs_d2_6" BEL
|
||||
"BIU_CORE/biu_register_cs_d2_6" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_cs_d2_5" BEL
|
||||
"BIU_CORE/biu_register_cs_d2_5" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_cs_d2_4" BEL
|
||||
"BIU_CORE/biu_register_cs_d2_4" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_cs_d2_3" BEL
|
||||
"BIU_CORE/biu_register_cs_d2_3" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_cs_d2_0" BEL
|
||||
"BIU_CORE/biu_register_cs_d2_0" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_cs_d2_2" BEL
|
||||
"BIU_CORE/biu_register_cs_d2_2" BEL
|
||||
"BIU_CORE/Mshreg_biu_register_cs_d2_1" BEL
|
||||
"BIU_CORE/biu_register_cs_d2_1" PIN
|
||||
"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>"
|
||||
PIN
|
||||
"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>"
|
||||
PIN
|
||||
"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>"
|
||||
PIN
|
||||
"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>"
|
||||
PIN
|
||||
"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>"
|
||||
PIN
|
||||
"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM9.ram_pins<26>"
|
||||
BEL
|
||||
"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/sel_pipe_0"
|
||||
PIN
|
||||
"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>"
|
||||
PIN
|
||||
"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>";
|
||||
PIN SP6_BUFIO_INSERT_ML_BUFIO2_0_pins<0> = BEL "SP6_BUFIO_INSERT_ML_BUFIO2_0"
|
||||
PINNAME DIVCLK;
|
||||
PIN SPARTAN6PLL/dcm_sp_inst_pins<2> = BEL "SPARTAN6PLL/dcm_sp_inst" PINNAME
|
||||
CLKIN;
|
||||
TIMEGRP CORE_CLK = PIN "SP6_BUFIO_INSERT_ML_BUFIO2_0_pins<0>" PIN
|
||||
"SPARTAN6PLL/dcm_sp_inst_pins<2>";
|
||||
TS_CORE_CLK = PERIOD TIMEGRP "CORE_CLK" 20 ns HIGH 50%;
|
||||
TS_SPARTAN6PLL_clkfx = PERIOD TIMEGRP "SPARTAN6PLL_clkfx" TS_CORE_CLK / 2.2
|
||||
HIGH 50%;
|
||||
SCHEMATIC END;
|
||||
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
verilog work "ipcore_dir/EU4Kx32.v"
|
||||
verilog work "ipcore_dir/spartan6_pll.v"
|
||||
verilog work "../src4synth/eu.v"
|
||||
verilog work "../src4synth/biu_min.v"
|
||||
verilog work "../src4synth/MCL86jr.v"
|
||||
|
|
@ -0,0 +1,332 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE twReport [
|
||||
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
|
||||
twDebug*, twFoot?, twClientInfo?)>
|
||||
<!ATTLIST twReport version CDATA "10,4">
|
||||
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
|
||||
<!ELEMENT twExecVer (#PCDATA)>
|
||||
<!ELEMENT twCopyright (#PCDATA)>
|
||||
<!ELEMENT twCmdLine (#PCDATA)>
|
||||
<!ELEMENT twDesign (#PCDATA)>
|
||||
<!ELEMENT twPCF (#PCDATA)>
|
||||
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
|
||||
<!ELEMENT twDevName (#PCDATA)>
|
||||
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
|
||||
<!ELEMENT twSpeedGrade (#PCDATA)>
|
||||
<!ELEMENT twSpeedVer (#PCDATA)>
|
||||
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
|
||||
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
|
||||
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
|
||||
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
|
||||
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
|
||||
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twItemLimit (#PCDATA)>
|
||||
<!ELEMENT twUnconst EMPTY>
|
||||
<!ELEMENT twUnconstLimit (#PCDATA)>
|
||||
<!ELEMENT twEnvVar EMPTY>
|
||||
<!ATTLIST twEnvVar name CDATA #REQUIRED>
|
||||
<!ATTLIST twEnvVar description CDATA #REQUIRED>
|
||||
<!ELEMENT twWarn (#PCDATA)>
|
||||
<!ELEMENT twInfo (#PCDATA)>
|
||||
<!ELEMENT twDebug (#PCDATA)>
|
||||
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
|
||||
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
|
||||
<!ELEMENT twProc (#PCDATA)>
|
||||
<!ELEMENT twTemp (#PCDATA)>
|
||||
<!ELEMENT twVolt (#PCDATA)>
|
||||
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
|
||||
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
|
||||
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
|
||||
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
|
||||
<!ELEMENT twCycles (twSigConn+)>
|
||||
<!ATTLIST twCycles twNum CDATA #REQUIRED>
|
||||
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
|
||||
<!ELEMENT twSig (#PCDATA)>
|
||||
<!ELEMENT twDriver (#PCDATA)>
|
||||
<!ELEMENT twLoad (#PCDATA)>
|
||||
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
|
||||
<!ATTLIST twConst twConstType (NET |
|
||||
NETDELAY |
|
||||
NETSKEW |
|
||||
PATH |
|
||||
DEFPERIOD |
|
||||
UNCONSTPATH |
|
||||
DEFPATH |
|
||||
PATH2SETUP |
|
||||
UNCONSTPATH2SETUP |
|
||||
PATHCLASS |
|
||||
PATHDELAY |
|
||||
PERIOD |
|
||||
FREQUENCY |
|
||||
PATHBLOCK |
|
||||
OFFSET |
|
||||
OFFSETIN |
|
||||
OFFSETINCLOCK |
|
||||
UNCONSTOFFSETINCLOCK |
|
||||
OFFSETINDELAY |
|
||||
OFFSETINMOD |
|
||||
OFFSETOUT |
|
||||
OFFSETOUTCLOCK |
|
||||
UNCONSTOFFSETOUTCLOCK |
|
||||
OFFSETOUTDELAY |
|
||||
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
|
||||
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
|
||||
twEndPtCnt?,
|
||||
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
|
||||
<!ELEMENT twConstName (#PCDATA)>
|
||||
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
|
||||
<!ATTLIST twConstHead uID CDATA #IMPLIED>
|
||||
<!ELEMENT twItemCnt (#PCDATA)>
|
||||
<!ELEMENT twErrCnt (#PCDATA)>
|
||||
<!ELEMENT twErrCntEndPt (#PCDATA)>
|
||||
<!ELEMENT twErrCntSetup (#PCDATA)>
|
||||
<!ELEMENT twErrCntHold (#PCDATA)>
|
||||
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
|
||||
<!ELEMENT twEndPtCnt (#PCDATA)>
|
||||
<!ELEMENT twPathErrCnt (#PCDATA)>
|
||||
<!ELEMENT twMinPer (#PCDATA) >
|
||||
<!ELEMENT twFootnote EMPTY>
|
||||
<!ATTLIST twFootnote number CDATA #REQUIRED>
|
||||
<!ELEMENT twMaxDel (#PCDATA)>
|
||||
<!ELEMENT twMaxFreq (#PCDATA)>
|
||||
<!ELEMENT twMinOff (#PCDATA)>
|
||||
<!ELEMENT twMaxOff (#PCDATA)>
|
||||
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
|
||||
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
|
||||
<!ELEMENT twTIGName (#PCDATA)>
|
||||
<!ELEMENT twInstantiated (#PCDATA)>
|
||||
<!ELEMENT twBlocked (#PCDATA)>
|
||||
<!ELEMENT twRacePathRpt (twRacePath+)>
|
||||
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
|
||||
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
|
||||
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
|
||||
twSimpleMinPath CDATA #IMPLIED>
|
||||
<!ELEMENT twTotDel (#PCDATA)>
|
||||
<!ELEMENT twSrc (#PCDATA)>
|
||||
<!ATTLIST twSrc BELType CDATA #IMPLIED>
|
||||
<!ELEMENT twDest (#PCDATA)>
|
||||
<!ATTLIST twDest BELType CDATA #IMPLIED>
|
||||
<!ELEMENT twDel (#PCDATA)>
|
||||
<!ELEMENT twSUTime (#PCDATA)>
|
||||
<!ELEMENT twTotPathDel (#PCDATA)>
|
||||
<!ELEMENT twClkSkew (#PCDATA)>
|
||||
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
|
||||
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
|
||||
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
|
||||
<!ELEMENT twSlack (#PCDATA)>
|
||||
<!ELEMENT twDelConst (#PCDATA)>
|
||||
<!ELEMENT tw2Phase EMPTY>
|
||||
<!ELEMENT twClkUncert (#PCDATA)>
|
||||
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
|
||||
fDCMJit CDATA #IMPLIED
|
||||
fPhaseErr CDATA #IMPLIED
|
||||
sEqu CDATA #IMPLIED>
|
||||
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
|
||||
<!ELEMENT twPathRptBanner (#PCDATA)>
|
||||
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
|
||||
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
|
||||
<!ELEMENT twOff (#PCDATA)>
|
||||
<!ELEMENT twGuaranteed EMPTY>
|
||||
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
|
||||
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
|
||||
<!ELEMENT twClkDel (#PCDATA)>
|
||||
<!ELEMENT twClkSrc (#PCDATA)>
|
||||
<!ELEMENT twClkDest (#PCDATA)>
|
||||
<!ELEMENT twGuarInSetup (#PCDATA)>
|
||||
<!ELEMENT twOffSrc (#PCDATA)>
|
||||
<!ELEMENT twOffDest (#PCDATA)>
|
||||
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
|
||||
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
|
||||
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
|
||||
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ELEMENT twDataDel (#PCDATA)>
|
||||
<!ELEMENT twDataSrc (#PCDATA)>
|
||||
<!ELEMENT twDataDest (#PCDATA)>
|
||||
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
|
||||
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twLogLvls (#PCDATA)>
|
||||
<!ELEMENT twSrcSite (#PCDATA)>
|
||||
<!ELEMENT twSrcClk (#PCDATA)>
|
||||
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
|
||||
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
|
||||
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
|
||||
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
|
||||
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
|
||||
<!ELEMENT twDelInfo (#PCDATA)>
|
||||
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
|
||||
<!ELEMENT twSite (#PCDATA)>
|
||||
<!ELEMENT twDelType (#PCDATA)>
|
||||
<!ELEMENT twFanCnt (#PCDATA)>
|
||||
<!ELEMENT twComp (#PCDATA)>
|
||||
<!ELEMENT twNet (#PCDATA)>
|
||||
<!ELEMENT twBEL (#PCDATA)>
|
||||
<!ELEMENT twLogDel (#PCDATA)>
|
||||
<!ELEMENT twRouteDel (#PCDATA)>
|
||||
<!ELEMENT twDestClk (#PCDATA)>
|
||||
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
|
||||
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
|
||||
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
|
||||
<!ELEMENT twPctLog (#PCDATA)>
|
||||
<!ELEMENT twPctRoute (#PCDATA)>
|
||||
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
|
||||
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
|
||||
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
|
||||
<!ELEMENT twTimeConst (#PCDATA)>
|
||||
<!ELEMENT twAbsSlack (#PCDATA)>
|
||||
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
|
||||
<!ELEMENT twSkew (#PCDATA)>
|
||||
<!ELEMENT twDetNet (twNetDel*)>
|
||||
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
|
||||
<!ELEMENT twNetDelInfo (#PCDATA)>
|
||||
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
|
||||
<!ELEMENT twDetSkewNet (twNetSkew*)>
|
||||
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
|
||||
<!ELEMENT twClkSkewLimit EMPTY>
|
||||
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
|
||||
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
|
||||
<!ELEMENT twConstRollupTable (twConstRollup*)>
|
||||
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
|
||||
<!ELEMENT twConstRollup EMPTY>
|
||||
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
|
||||
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
|
||||
<!ELEMENT twConstList (twConstListItem)*>
|
||||
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
|
||||
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
|
||||
<!ELEMENT twNotMet EMPTY>
|
||||
<!ELEMENT twReqVal (#PCDATA)>
|
||||
<!ELEMENT twActVal (#PCDATA)>
|
||||
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
|
||||
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
|
||||
<!ELEMENT twConstStats (twConstName)>
|
||||
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
|
||||
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
|
||||
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
|
||||
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
|
||||
<!ELEMENT twConstData EMPTY>
|
||||
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
|
||||
best CDATA #IMPLIED requested CDATA #IMPLIED
|
||||
errors CDATA #IMPLIED
|
||||
score CDATA #IMPLIED>
|
||||
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
|
||||
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
|
||||
<!ELEMENT twTimeGrpName (#PCDATA)>
|
||||
<!ELEMENT twCompList (twCompName+)>
|
||||
<!ELEMENT twCompName (#PCDATA)>
|
||||
<!ELEMENT twSigList (twSigName+)>
|
||||
<!ELEMENT twSigName (#PCDATA)>
|
||||
<!ELEMENT twBELList (twBELName+)>
|
||||
<!ELEMENT twBELName (#PCDATA)>
|
||||
<!ELEMENT twBlockList (twBlockName+)>
|
||||
<!ELEMENT twBlockName (#PCDATA)>
|
||||
<!ELEMENT twMacList (twMacName+)>
|
||||
<!ELEMENT twMacName (#PCDATA)>
|
||||
<!ELEMENT twPinList (twPinName+)>
|
||||
<!ELEMENT twPinName (#PCDATA)>
|
||||
<!ELEMENT twUnmetConstCnt (#PCDATA)>
|
||||
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
|
||||
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
|
||||
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
|
||||
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
|
||||
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
|
||||
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
|
||||
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
|
||||
<!ELEMENT twSU2ClkTime (#PCDATA)>
|
||||
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twH2ClkTime (#PCDATA)>
|
||||
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
|
||||
<!ELEMENT twClk2Pad (twDest, twTime)>
|
||||
<!ELEMENT twTime (#PCDATA)>
|
||||
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
|
||||
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
|
||||
<!ELEMENT twClk2Out EMPTY>
|
||||
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
|
||||
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
|
||||
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
|
||||
<!ELEMENT twRiseRise (#PCDATA)>
|
||||
<!ELEMENT twFallRise (#PCDATA)>
|
||||
<!ELEMENT twRiseFall (#PCDATA)>
|
||||
<!ELEMENT twFallFall (#PCDATA)>
|
||||
<!ELEMENT twPad2PadList (twPad2Pad+)>
|
||||
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
|
||||
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
|
||||
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
|
||||
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
|
||||
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
|
||||
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
|
||||
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
|
||||
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
|
||||
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
|
||||
<!ELEMENT twOffOutTblRow EMPTY>
|
||||
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
|
||||
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
|
||||
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
|
||||
<!ELEMENT twNonDedClk (#PCDATA)>
|
||||
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
|
||||
<!ELEMENT twScore (#PCDATA)>
|
||||
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
|
||||
<!ELEMENT twPathCnt (#PCDATA)>
|
||||
<!ELEMENT twNetCnt (#PCDATA)>
|
||||
<!ELEMENT twConnCnt (#PCDATA)>
|
||||
<!ELEMENT twPct (#PCDATA)>
|
||||
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
|
||||
<!ELEMENT twMaxCombDel (#PCDATA)>
|
||||
<!ELEMENT twMaxFromToDel (#PCDATA)>
|
||||
<!ELEMENT twMaxNetDel (#PCDATA)>
|
||||
<!ELEMENT twMaxNetSkew (#PCDATA)>
|
||||
<!ELEMENT twMaxInAfterClk (#PCDATA)>
|
||||
<!ELEMENT twMinInBeforeClk (#PCDATA)>
|
||||
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
|
||||
<!ELEMENT twMinOutAfterClk (#PCDATA)>
|
||||
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
|
||||
<!ELEMENT twTimestamp (#PCDATA)>
|
||||
<!ELEMENT twFootnoteExplanation EMPTY>
|
||||
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
|
||||
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
|
||||
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
|
||||
<!ELEMENT twClientName (#PCDATA)>
|
||||
<!ELEMENT twAttrList (twAttrListItem)*>
|
||||
<!ELEMENT twAttrListItem (twName, twValue*)>
|
||||
<!ELEMENT twName (#PCDATA)>
|
||||
<!ELEMENT twValue (#PCDATA)>
|
||||
]>
|
||||
<twReport><twBody><twSumRpt><twConstRollupTable uID="1" anchorID="55"><twConstRollup name="TS_CORE_CLK" fullName="TS_CORE_CLK = PERIOD TIMEGRP "CORE_CLK" 20 ns HIGH 50%;" type="origin" depth="0" requirement="20.000" prefType="period" actual="8.000" actualRollup="19.340" errors="0" errorRollup="0" items="0" itemsRollup="513828"/><twConstRollup name="TS_SPARTAN6PLL_clkfx" fullName="TS_SPARTAN6PLL_clkfx = PERIOD TIMEGRP "SPARTAN6PLL_clkfx" TS_CORE_CLK / 2.2 HIGH 50%;" type="child" depth="1" requirement="9.091" prefType="period" actual="8.791" actualRollup="N/A" errors="0" errorRollup="0" items="513828" itemsRollup="0"/></twConstRollupTable><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SPARTAN6PLL_clkfx = PERIOD TIMEGRP "SPARTAN6PLL_clkfx" TS_CORE_CLK / 2.2 HIGH 50%</twConstName><twConstData type="SETUP" slack="0.299" best="8.791" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.367" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_CORE_CLK = PERIOD TIMEGRP "CORE_CLK" 20 ns HIGH 50%</twConstName><twConstData type="MINLOWPULSE" slack="12.000" best="8.000" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="56">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
|
||||
|
|
@ -0,0 +1,944 @@
|
|||
Release 14.7 - xst P.20131013 (nt64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
--> Parameter TMPDIR set to xst/projnav.tmp
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.09 secs
|
||||
|
||||
--> Parameter xsthdpdir set to xst
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.09 secs
|
||||
|
||||
--> Reading design: MCL86jr.prj
|
||||
|
||||
TABLE OF CONTENTS
|
||||
1) Synthesis Options Summary
|
||||
2) HDL Parsing
|
||||
3) HDL Elaboration
|
||||
4) HDL Synthesis
|
||||
4.1) HDL Synthesis Report
|
||||
5) Advanced HDL Synthesis
|
||||
5.1) Advanced HDL Synthesis Report
|
||||
6) Low Level Synthesis
|
||||
7) Partition Report
|
||||
8) Design Summary
|
||||
8.1) Primitive and Black Box Usage
|
||||
8.2) Device utilization summary
|
||||
8.3) Partition Resource Summary
|
||||
8.4) Timing Report
|
||||
8.4.1) Clock Information
|
||||
8.4.2) Asynchronous Control Signals Information
|
||||
8.4.3) Timing Summary
|
||||
8.4.4) Timing Details
|
||||
8.4.5) Cross Clock Domains Report
|
||||
|
||||
|
||||
=========================================================================
|
||||
* Synthesis Options Summary *
|
||||
=========================================================================
|
||||
---- Source Parameters
|
||||
Input File Name : "MCL86jr.prj"
|
||||
Ignore Synthesis Constraint File : NO
|
||||
|
||||
---- Target Parameters
|
||||
Output File Name : "MCL86jr"
|
||||
Output Format : NGC
|
||||
Target Device : xc6slx9-3-tqg144
|
||||
|
||||
---- Source Options
|
||||
Top Module Name : MCL86jr
|
||||
Automatic FSM Extraction : YES
|
||||
FSM Encoding Algorithm : Auto
|
||||
Safe Implementation : No
|
||||
FSM Style : LUT
|
||||
RAM Extraction : Yes
|
||||
RAM Style : Auto
|
||||
ROM Extraction : Yes
|
||||
Shift Register Extraction : YES
|
||||
ROM Style : Auto
|
||||
Resource Sharing : YES
|
||||
Asynchronous To Synchronous : NO
|
||||
Shift Register Minimum Size : 2
|
||||
Use DSP Block : Auto
|
||||
Automatic Register Balancing : No
|
||||
|
||||
---- Target Options
|
||||
LUT Combining : Auto
|
||||
Reduce Control Sets : Auto
|
||||
Add IO Buffers : YES
|
||||
Global Maximum Fanout : 100000
|
||||
Add Generic Clock Buffer(BUFG) : 16
|
||||
Register Duplication : YES
|
||||
Optimize Instantiated Primitives : NO
|
||||
Use Clock Enable : Auto
|
||||
Use Synchronous Set : Auto
|
||||
Use Synchronous Reset : Auto
|
||||
Pack IO Registers into IOBs : Auto
|
||||
Equivalent register Removal : YES
|
||||
|
||||
---- General Options
|
||||
Optimization Goal : Speed
|
||||
Optimization Effort : 1
|
||||
Power Reduction : NO
|
||||
Keep Hierarchy : No
|
||||
Netlist Hierarchy : As_Optimized
|
||||
RTL Output : Yes
|
||||
Global Optimization : AllClockNets
|
||||
Read Cores : YES
|
||||
Write Timing Constraints : NO
|
||||
Cross Clock Analysis : NO
|
||||
Hierarchy Separator : /
|
||||
Bus Delimiter : <>
|
||||
Case Specifier : Maintain
|
||||
Slice Utilization Ratio : 100
|
||||
BRAM Utilization Ratio : 100
|
||||
DSP48 Utilization Ratio : 100
|
||||
Auto BRAM Packing : NO
|
||||
Slice Utilization Ratio Delta : 5
|
||||
|
||||
---- Other Options
|
||||
Cores Search Directories : {"ipcore_dir" }
|
||||
|
||||
=========================================================================
|
||||
|
||||
|
||||
=========================================================================
|
||||
* HDL Parsing *
|
||||
=========================================================================
|
||||
Analyzing Verilog file "C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\EU4Kx32.v" into library work
|
||||
Parsing module <EU4Kx32>.
|
||||
Analyzing Verilog file "C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\spartan6_pll.v" into library work
|
||||
Parsing module <spartan6_pll>.
|
||||
Analyzing Verilog file "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" into library work
|
||||
Parsing module <mcl86_eu_core>.
|
||||
Analyzing Verilog file "C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" into library work
|
||||
Parsing module <biu_min>.
|
||||
Analyzing Verilog file "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" into library work
|
||||
Parsing module <MCL86jr>.
|
||||
|
||||
=========================================================================
|
||||
* HDL Elaboration *
|
||||
=========================================================================
|
||||
|
||||
Elaborating module <MCL86jr>.
|
||||
|
||||
Elaborating module <spartan6_pll>.
|
||||
|
||||
Elaborating module <IBUFG>.
|
||||
|
||||
Elaborating module <DCM_SP(CLKDV_DIVIDE=2.0,CLKFX_DIVIDE=5,CLKFX_MULTIPLY=11,CLKIN_DIVIDE_BY_2="FALSE",CLKIN_PERIOD=20.0,CLKOUT_PHASE_SHIFT="NONE",CLK_FEEDBACK="NONE",DESKEW_ADJUST="SYSTEM_SYNCHRONOUS",PHASE_SHIFT=0,STARTUP_WAIT="FALSE")>.
|
||||
WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\spartan6_pll.v" Line 111: Assignment to clk0 ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\spartan6_pll.v" Line 126: Assignment to locked_int ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\spartan6_pll.v" Line 127: Assignment to status_int ignored, since the identifier is never used
|
||||
|
||||
Elaborating module <BUFG>.
|
||||
WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 182: Result of 32-bit expression is truncated to fit in 1-bit target.
|
||||
WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 183: Result of 32-bit expression is truncated to fit in 1-bit target.
|
||||
WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 184: Result of 32-bit expression is truncated to fit in 1-bit target.
|
||||
WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 185: Result of 32-bit expression is truncated to fit in 1-bit target.
|
||||
WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 186: Result of 32-bit expression is truncated to fit in 1-bit target.
|
||||
WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 187: Result of 32-bit expression is truncated to fit in 1-bit target.
|
||||
WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 188: Result of 32-bit expression is truncated to fit in 1-bit target.
|
||||
WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 189: Result of 32-bit expression is truncated to fit in 1-bit target.
|
||||
WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 213: Assignment to t_eu_flag_i_d ignored, since the identifier is never used
|
||||
|
||||
Elaborating module <biu_min>.
|
||||
WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 231: Assignment to eu_qs_out ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 477: Result of 32-bit expression is truncated to fit in 13-bit target.
|
||||
WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 493: Result of 17-bit expression is truncated to fit in 16-bit target.
|
||||
WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 503: Result of 17-bit expression is truncated to fit in 16-bit target.
|
||||
WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 835: Result of 17-bit expression is truncated to fit in 16-bit target.
|
||||
WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 276: Assignment to ready_d3 ignored, since the identifier is never used
|
||||
|
||||
Elaborating module <mcl86_eu_core>.
|
||||
|
||||
Elaborating module <EU4Kx32>.
|
||||
WARNING:HDLCompiler:1499 - "C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\EU4Kx32.v" Line 39: Empty module <EU4Kx32> remains a black box.
|
||||
WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 264: Assignment to eu_prefix_repnz ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 265: Assignment to eu_prefix_rep ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 268: Assignment to eu_flag_o ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 269: Assignment to eu_flag_d ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 272: Assignment to eu_flag_s ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 273: Assignment to eu_flag_z ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 275: Assignment to eu_flag_a ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 276: Assignment to eu_nmi_pending ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 277: Assignment to eu_flag_p ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 278: Assignment to eu_flag_temp ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 279: Assignment to eu_flag_c ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 298: Result of 20-bit expression is truncated to fit in 16-bit target.
|
||||
WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 338: Assignment to biu_done_d2 ignored, since the identifier is never used
|
||||
WARNING:HDLCompiler:634 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 147: Net <system_signals[15]> does not have a driver.
|
||||
|
||||
=========================================================================
|
||||
* HDL Synthesis *
|
||||
=========================================================================
|
||||
|
||||
Synthesizing Unit <MCL86jr>.
|
||||
Related source file is "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v".
|
||||
INFO:Xst:3210 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" line 269: Output port <BIU_SEGMENT> of the instance <BIU_CORE> is unconnected or connected to loadless signal.
|
||||
INFO:Xst:3210 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" line 322: Output port <EU_FLAG_I> of the instance <EU_CORE> is unconnected or connected to loadless signal.
|
||||
Found 1-bit register for signal <t_biu_ad_oe_d2>.
|
||||
Found 20-bit register for signal <t_biu_ad_out_d>.
|
||||
Found 1-bit register for signal <t_reset_d1>.
|
||||
Found 1-bit register for signal <t_reset_d2>.
|
||||
Found 1-bit register for signal <t_reset_d3>.
|
||||
Found 1-bit register for signal <t_reset_d4>.
|
||||
Found 8-bit register for signal <led_int>.
|
||||
Found 27-bit register for signal <prescaler>.
|
||||
Found 1-bit register for signal <prescaler_d>.
|
||||
Found 1-bit register for signal <led_go_left>.
|
||||
Found 1-bit register for signal <t_biu_ad_oe_d1>.
|
||||
Found 27-bit adder for signal <prescaler[26]_GND_1_o_add_24_OUT> created at line 241.
|
||||
Found 1-bit tristate buffer for signal <AD7> created at line 182
|
||||
Found 1-bit tristate buffer for signal <AD6> created at line 183
|
||||
Found 1-bit tristate buffer for signal <AD5> created at line 184
|
||||
Found 1-bit tristate buffer for signal <AD4> created at line 185
|
||||
Found 1-bit tristate buffer for signal <AD3> created at line 186
|
||||
Found 1-bit tristate buffer for signal <AD2> created at line 187
|
||||
Found 1-bit tristate buffer for signal <AD1> created at line 188
|
||||
Found 1-bit tristate buffer for signal <AD0> created at line 189
|
||||
Found 1-bit tristate buffer for signal <SRAM_D<7>> created at line 199
|
||||
Found 1-bit tristate buffer for signal <SRAM_D<6>> created at line 199
|
||||
Found 1-bit tristate buffer for signal <SRAM_D<5>> created at line 199
|
||||
Found 1-bit tristate buffer for signal <SRAM_D<4>> created at line 199
|
||||
Found 1-bit tristate buffer for signal <SRAM_D<3>> created at line 199
|
||||
Found 1-bit tristate buffer for signal <SRAM_D<2>> created at line 199
|
||||
Found 1-bit tristate buffer for signal <SRAM_D<1>> created at line 199
|
||||
Found 1-bit tristate buffer for signal <SRAM_D<0>> created at line 199
|
||||
Summary:
|
||||
inferred 1 Adder/Subtractor(s).
|
||||
inferred 63 D-type flip-flop(s).
|
||||
inferred 1 Multiplexer(s).
|
||||
inferred 16 Tristate(s).
|
||||
Unit <MCL86jr> synthesized.
|
||||
|
||||
Synthesizing Unit <spartan6_pll>.
|
||||
Related source file is "C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\spartan6_pll.v".
|
||||
Summary:
|
||||
no macro.
|
||||
Unit <spartan6_pll> synthesized.
|
||||
|
||||
Synthesizing Unit <biu_min>.
|
||||
Related source file is "C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v".
|
||||
WARNING:Xst:647 - Input <EU_BIU_COMMAND<3:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <EU_BIU_COMMAND<15:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <EU_PREFIX_LOCK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
Found 1-bit register for signal <clk_d2>.
|
||||
Found 1-bit register for signal <clk_d3>.
|
||||
Found 1-bit register for signal <clk_d4>.
|
||||
Found 1-bit register for signal <nmi_d1>.
|
||||
Found 1-bit register for signal <nmi_d2>.
|
||||
Found 1-bit register for signal <nmi_d3>.
|
||||
Found 1-bit register for signal <nmi_d4>.
|
||||
Found 1-bit register for signal <nmi_d5>.
|
||||
Found 1-bit register for signal <nmi_caught>.
|
||||
Found 16-bit register for signal <eu_register_r3_d>.
|
||||
Found 1-bit register for signal <eu_biu_req_caught>.
|
||||
Found 16-bit register for signal <biu_register_cs>.
|
||||
Found 16-bit register for signal <biu_register_es>.
|
||||
Found 16-bit register for signal <biu_register_ss>.
|
||||
Found 16-bit register for signal <biu_register_ds>.
|
||||
Found 16-bit register for signal <biu_register_rm>.
|
||||
Found 16-bit register for signal <biu_register_reg>.
|
||||
Found 13-bit register for signal <clock_cycle_counter>.
|
||||
Found 16-bit register for signal <pfq_addr_out>.
|
||||
Found 8-bit register for signal <pfq_entry0>.
|
||||
Found 8-bit register for signal <pfq_entry1>.
|
||||
Found 8-bit register for signal <pfq_entry2>.
|
||||
Found 8-bit register for signal <pfq_entry3>.
|
||||
Found 8-bit register for signal <biu_state>.
|
||||
Found 1-bit register for signal <pfq_write>.
|
||||
Found 16-bit register for signal <pfq_addr_in>.
|
||||
Found 1-bit register for signal <biu_return_data_int<15>>.
|
||||
Found 1-bit register for signal <biu_return_data_int<14>>.
|
||||
Found 1-bit register for signal <biu_return_data_int<13>>.
|
||||
Found 1-bit register for signal <biu_return_data_int<12>>.
|
||||
Found 1-bit register for signal <biu_return_data_int<11>>.
|
||||
Found 1-bit register for signal <biu_return_data_int<10>>.
|
||||
Found 1-bit register for signal <biu_return_data_int<9>>.
|
||||
Found 1-bit register for signal <biu_return_data_int<8>>.
|
||||
Found 1-bit register for signal <biu_return_data_int<7>>.
|
||||
Found 1-bit register for signal <biu_return_data_int<6>>.
|
||||
Found 1-bit register for signal <biu_return_data_int<5>>.
|
||||
Found 1-bit register for signal <biu_return_data_int<4>>.
|
||||
Found 1-bit register for signal <biu_return_data_int<3>>.
|
||||
Found 1-bit register for signal <biu_return_data_int<2>>.
|
||||
Found 1-bit register for signal <biu_return_data_int<1>>.
|
||||
Found 1-bit register for signal <biu_return_data_int<0>>.
|
||||
Found 1-bit register for signal <biu_done_int>.
|
||||
Found 1-bit register for signal <ready_d1>.
|
||||
Found 1-bit register for signal <eu_biu_req_d1>.
|
||||
Found 8-bit register for signal <latched_data_in>.
|
||||
Found 1-bit register for signal <addr_out_temp<19>>.
|
||||
Found 1-bit register for signal <addr_out_temp<18>>.
|
||||
Found 1-bit register for signal <addr_out_temp<17>>.
|
||||
Found 1-bit register for signal <addr_out_temp<16>>.
|
||||
Found 1-bit register for signal <addr_out_temp<15>>.
|
||||
Found 1-bit register for signal <addr_out_temp<14>>.
|
||||
Found 1-bit register for signal <addr_out_temp<13>>.
|
||||
Found 1-bit register for signal <addr_out_temp<12>>.
|
||||
Found 1-bit register for signal <addr_out_temp<11>>.
|
||||
Found 1-bit register for signal <addr_out_temp<10>>.
|
||||
Found 1-bit register for signal <addr_out_temp<9>>.
|
||||
Found 1-bit register for signal <addr_out_temp<8>>.
|
||||
Found 1-bit register for signal <addr_out_temp<7>>.
|
||||
Found 1-bit register for signal <addr_out_temp<6>>.
|
||||
Found 1-bit register for signal <addr_out_temp<5>>.
|
||||
Found 1-bit register for signal <addr_out_temp<4>>.
|
||||
Found 1-bit register for signal <addr_out_temp<3>>.
|
||||
Found 1-bit register for signal <addr_out_temp<2>>.
|
||||
Found 1-bit register for signal <addr_out_temp<1>>.
|
||||
Found 1-bit register for signal <addr_out_temp<0>>.
|
||||
Found 3-bit register for signal <s_bits>.
|
||||
Found 1-bit register for signal <AD_OUT<19>>.
|
||||
Found 1-bit register for signal <AD_OUT<18>>.
|
||||
Found 1-bit register for signal <AD_OUT<17>>.
|
||||
Found 1-bit register for signal <AD_OUT<16>>.
|
||||
Found 1-bit register for signal <AD_OUT<15>>.
|
||||
Found 1-bit register for signal <AD_OUT<14>>.
|
||||
Found 1-bit register for signal <AD_OUT<13>>.
|
||||
Found 1-bit register for signal <AD_OUT<12>>.
|
||||
Found 1-bit register for signal <AD_OUT<11>>.
|
||||
Found 1-bit register for signal <AD_OUT<10>>.
|
||||
Found 1-bit register for signal <AD_OUT<9>>.
|
||||
Found 1-bit register for signal <AD_OUT<8>>.
|
||||
Found 1-bit register for signal <AD_OUT<7>>.
|
||||
Found 1-bit register for signal <AD_OUT<6>>.
|
||||
Found 1-bit register for signal <AD_OUT<5>>.
|
||||
Found 1-bit register for signal <AD_OUT<4>>.
|
||||
Found 1-bit register for signal <AD_OUT<3>>.
|
||||
Found 1-bit register for signal <AD_OUT<2>>.
|
||||
Found 1-bit register for signal <AD_OUT<1>>.
|
||||
Found 1-bit register for signal <AD_OUT<0>>.
|
||||
Found 1-bit register for signal <word_cycle>.
|
||||
Found 1-bit register for signal <byte_num>.
|
||||
Found 8-bit register for signal <ad_in_int>.
|
||||
Found 1-bit register for signal <BIU_INTR>.
|
||||
Found 1-bit register for signal <intr_d1>.
|
||||
Found 1-bit register for signal <intr_d2>.
|
||||
Found 1-bit register for signal <intr_d3>.
|
||||
Found 1-bit register for signal <AD_OE>.
|
||||
Found 1-bit register for signal <RD_n>.
|
||||
Found 1-bit register for signal <WR_n>.
|
||||
Found 1-bit register for signal <IOM>.
|
||||
Found 1-bit register for signal <DTR>.
|
||||
Found 1-bit register for signal <DEN>.
|
||||
Found 1-bit register for signal <INTA_n>.
|
||||
Found 1-bit register for signal <inta_n_int>.
|
||||
Found 1-bit register for signal <ale_int>.
|
||||
Found 1-bit register for signal <rd_n_int>.
|
||||
Found 1-bit register for signal <wr_n_int>.
|
||||
Found 1-bit register for signal <iom_int>.
|
||||
Found 1-bit register for signal <dtr_int>.
|
||||
Found 1-bit register for signal <den_int>.
|
||||
Found 1-bit register for signal <SRAM_OE_n>.
|
||||
Found 1-bit register for signal <SRAM_WE_n>.
|
||||
Found 1-bit register for signal <SRAM_D_OE>.
|
||||
Found 16-bit register for signal <biu_register_es_d1>.
|
||||
Found 16-bit register for signal <biu_register_ss_d1>.
|
||||
Found 16-bit register for signal <biu_register_cs_d1>.
|
||||
Found 16-bit register for signal <biu_register_ds_d1>.
|
||||
Found 16-bit register for signal <biu_register_rm_d1>.
|
||||
Found 16-bit register for signal <biu_register_reg_d1>.
|
||||
Found 16-bit register for signal <biu_register_es_d2>.
|
||||
Found 16-bit register for signal <biu_register_ss_d2>.
|
||||
Found 16-bit register for signal <biu_register_cs_d2>.
|
||||
Found 16-bit register for signal <biu_register_ds_d2>.
|
||||
Found 16-bit register for signal <biu_register_rm_d2>.
|
||||
Found 16-bit register for signal <biu_register_reg_d2>.
|
||||
Found 8-bit register for signal <pfq_top_byte_int_d1>.
|
||||
Found 16-bit register for signal <pfq_addr_out_d1>.
|
||||
Found 16-bit register for signal <biu_return_data_int_d1>.
|
||||
Found 16-bit register for signal <biu_return_data_int_d2>.
|
||||
Found 26-bit register for signal <nmi_counter>.
|
||||
Found 1-bit register for signal <ALE>.
|
||||
Found 1-bit register for signal <sram_select>.
|
||||
Found 8-bit register for signal <mcl6_feature>.
|
||||
Found 1-bit register for signal <SRAM_A<18>>.
|
||||
Found 1-bit register for signal <SRAM_A<17>>.
|
||||
Found 1-bit register for signal <SRAM_A<16>>.
|
||||
Found 1-bit register for signal <SRAM_A<15>>.
|
||||
Found 1-bit register for signal <SRAM_A<14>>.
|
||||
Found 1-bit register for signal <SRAM_A<13>>.
|
||||
Found 1-bit register for signal <SRAM_A<12>>.
|
||||
Found 1-bit register for signal <SRAM_A<11>>.
|
||||
Found 1-bit register for signal <SRAM_A<10>>.
|
||||
Found 1-bit register for signal <SRAM_A<9>>.
|
||||
Found 1-bit register for signal <SRAM_A<8>>.
|
||||
Found 1-bit register for signal <SRAM_A<7>>.
|
||||
Found 1-bit register for signal <SRAM_A<6>>.
|
||||
Found 1-bit register for signal <SRAM_A<5>>.
|
||||
Found 1-bit register for signal <SRAM_A<4>>.
|
||||
Found 1-bit register for signal <SRAM_A<3>>.
|
||||
Found 1-bit register for signal <SRAM_A<2>>.
|
||||
Found 1-bit register for signal <SRAM_A<1>>.
|
||||
Found 1-bit register for signal <SRAM_A<0>>.
|
||||
Found 8-bit register for signal <SRAM_D_OUT>.
|
||||
Found 1-bit register for signal <clk_d1>.
|
||||
Found 26-bit adder for signal <nmi_counter[25]_GND_22_o_add_44_OUT> created at line 402.
|
||||
Found 16-bit adder for signal <pfq_addr_out[15]_GND_22_o_add_79_OUT> created at line 493.
|
||||
Found 16-bit adder for signal <pfq_addr_in[15]_GND_22_o_add_85_OUT> created at line 503.
|
||||
Found 8-bit adder for signal <biu_state[7]_GND_22_o_add_97_OUT> created at line 523.
|
||||
Found 20-bit adder for signal <biu_register_cs[15]_GND_22_o_add_99_OUT> created at line 579.
|
||||
Found 20-bit adder for signal <biu_muxed_segment[15]_GND_22_o_add_100_OUT> created at line 586.
|
||||
Found 20-bit adder for signal <biu_register_ss[15]_GND_22_o_add_102_OUT> created at line 601.
|
||||
Found 20-bit adder for signal <biu_register_cs[15]_GND_22_o_add_128_OUT> created at line 651.
|
||||
Found 16-bit adder for signal <addr_out_temp[15]_GND_22_o_add_186_OUT> created at line 875.
|
||||
Found 13-bit subtractor for signal <GND_22_o_GND_22_o_sub_73_OUT<12:0>> created at line 477.
|
||||
Found 16-bit 4-to-1 multiplexer for signal <biu_muxed_segment> created at line 189.
|
||||
Found 8-bit 4-to-1 multiplexer for signal <pfq_top_byte_int> created at line 196.
|
||||
Found 1-bit comparator equal for signal <n0033> created at line 255
|
||||
Found 2-bit comparator equal for signal <pfq_addr_in[1]_pfq_addr_out[1]_equal_33_o> created at line 256
|
||||
Found 4-bit comparator greater for signal <GND_22_o_addr_out_temp[19]_LessThan_140_o> created at line 671
|
||||
Found 4-bit comparator greater for signal <addr_out_temp[19]_PWR_6_o_LessThan_141_o> created at line 671
|
||||
Summary:
|
||||
inferred 10 Adder/Subtractor(s).
|
||||
inferred 621 D-type flip-flop(s).
|
||||
inferred 4 Comparator(s).
|
||||
inferred 101 Multiplexer(s).
|
||||
Unit <biu_min> synthesized.
|
||||
|
||||
Synthesizing Unit <mcl86_eu_core>.
|
||||
Related source file is "C:\MCL\MCL86\MCL86jr\src4synth\eu.v".
|
||||
WARNING:Xst:653 - Signal <system_signals<15:14>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
||||
WARNING:Xst:653 - Signal <system_signals<10>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
||||
Found 1-bit register for signal <eu_biu_req_d1>.
|
||||
Found 1-bit register for signal <biu_done_caught>.
|
||||
Found 1-bit register for signal <eu_flag_t_d>.
|
||||
Found 1-bit register for signal <eu_tr_latched>.
|
||||
Found 1-bit register for signal <eu_add_carry>.
|
||||
Found 1-bit register for signal <eu_add_carry8>.
|
||||
Found 1-bit register for signal <eu_add_aux_carry>.
|
||||
Found 1-bit register for signal <eu_add_overflow16>.
|
||||
Found 1-bit register for signal <eu_add_overflow8>.
|
||||
Found 16-bit register for signal <eu_alu_last_result>.
|
||||
Found 16-bit register for signal <eu_register_ax>.
|
||||
Found 16-bit register for signal <eu_register_bx>.
|
||||
Found 16-bit register for signal <eu_register_cx>.
|
||||
Found 16-bit register for signal <eu_register_dx>.
|
||||
Found 16-bit register for signal <eu_register_sp>.
|
||||
Found 16-bit register for signal <eu_register_bp>.
|
||||
Found 16-bit register for signal <eu_register_si>.
|
||||
Found 16-bit register for signal <eu_register_di>.
|
||||
Found 16-bit register for signal <eu_flags>.
|
||||
Found 16-bit register for signal <eu_register_r0>.
|
||||
Found 16-bit register for signal <eu_register_r1>.
|
||||
Found 16-bit register for signal <eu_register_r2>.
|
||||
Found 16-bit register for signal <eu_register_r3>.
|
||||
Found 16-bit register for signal <eu_biu_command>.
|
||||
Found 16-bit register for signal <eu_biu_dataout>.
|
||||
Found 1-bit register for signal <eu_stall_pipeline>.
|
||||
Found 13-bit register for signal <eu_rom_address>.
|
||||
Found 52-bit register for signal <eu_calling_address>.
|
||||
Found 1-bit register for signal <intr_enable_delayed>.
|
||||
Found 1-bit register for signal <biu_done_d1>.
|
||||
Found 13-bit adder for signal <eu_rom_address[12]_GND_23_o_add_186_OUT> created at line 483.
|
||||
Found 16-bit 16-to-1 multiplexer for signal <eu_operand0> created at line 155.
|
||||
Found 16-bit 16-to-1 multiplexer for signal <eu_operand1> created at line 156.
|
||||
Found 20-bit 7-to-1 multiplexer for signal <n0455> created at line 298.
|
||||
Summary:
|
||||
inferred 1 Adder/Subtractor(s).
|
||||
inferred 333 D-type flip-flop(s).
|
||||
inferred 54 Multiplexer(s).
|
||||
Unit <mcl86_eu_core> synthesized.
|
||||
|
||||
=========================================================================
|
||||
HDL Synthesis Report
|
||||
|
||||
Macro Statistics
|
||||
# Adders/Subtractors : 12
|
||||
13-bit adder : 1
|
||||
13-bit subtractor : 1
|
||||
16-bit adder : 3
|
||||
20-bit adder : 4
|
||||
26-bit adder : 1
|
||||
27-bit adder : 1
|
||||
8-bit adder : 1
|
||||
# Registers : 129
|
||||
1-bit register : 68
|
||||
13-bit register : 2
|
||||
16-bit register : 41
|
||||
19-bit register : 1
|
||||
20-bit register : 3
|
||||
26-bit register : 1
|
||||
27-bit register : 1
|
||||
3-bit register : 1
|
||||
52-bit register : 1
|
||||
8-bit register : 10
|
||||
# Comparators : 4
|
||||
1-bit comparator equal : 1
|
||||
2-bit comparator equal : 1
|
||||
4-bit comparator greater : 2
|
||||
# Multiplexers : 156
|
||||
1-bit 2-to-1 multiplexer : 118
|
||||
13-bit 2-to-1 multiplexer : 9
|
||||
16-bit 16-to-1 multiplexer : 2
|
||||
16-bit 2-to-1 multiplexer : 3
|
||||
16-bit 4-to-1 multiplexer : 1
|
||||
2-bit 2-to-1 multiplexer : 1
|
||||
20-bit 2-to-1 multiplexer : 3
|
||||
20-bit 7-to-1 multiplexer : 1
|
||||
26-bit 2-to-1 multiplexer : 1
|
||||
3-bit 2-to-1 multiplexer : 1
|
||||
52-bit 2-to-1 multiplexer : 1
|
||||
8-bit 2-to-1 multiplexer : 14
|
||||
8-bit 4-to-1 multiplexer : 1
|
||||
# Tristates : 16
|
||||
1-bit tristate buffer : 16
|
||||
# Xors : 20
|
||||
1-bit xor2 : 2
|
||||
1-bit xor3 : 16
|
||||
1-bit xor8 : 1
|
||||
16-bit xor2 : 1
|
||||
|
||||
=========================================================================
|
||||
|
||||
=========================================================================
|
||||
* Advanced HDL Synthesis *
|
||||
=========================================================================
|
||||
|
||||
Reading core <ipcore_dir/EU4Kx32.ngc>.
|
||||
Loading core <EU4Kx32> for timing and area information for instance <EU4Kx32_i>.
|
||||
WARNING:Xst:2677 - Node <mcl6_feature_2> of sequential type is unconnected in block <BIU_CORE>.
|
||||
WARNING:Xst:2677 - Node <mcl6_feature_3> of sequential type is unconnected in block <BIU_CORE>.
|
||||
WARNING:Xst:2677 - Node <mcl6_feature_4> of sequential type is unconnected in block <BIU_CORE>.
|
||||
WARNING:Xst:2677 - Node <mcl6_feature_5> of sequential type is unconnected in block <BIU_CORE>.
|
||||
WARNING:Xst:2677 - Node <mcl6_feature_6> of sequential type is unconnected in block <BIU_CORE>.
|
||||
WARNING:Xst:2677 - Node <mcl6_feature_7> of sequential type is unconnected in block <BIU_CORE>.
|
||||
|
||||
Synthesizing (advanced) Unit <MCL86jr>.
|
||||
The following registers are absorbed into counter <prescaler>: 1 register on signal <prescaler>.
|
||||
Unit <MCL86jr> synthesized (advanced).
|
||||
|
||||
Synthesizing (advanced) Unit <biu_min>.
|
||||
The following registers are absorbed into counter <clock_cycle_counter>: 1 register on signal <clock_cycle_counter>.
|
||||
The following registers are absorbed into counter <pfq_addr_out>: 1 register on signal <pfq_addr_out>.
|
||||
The following registers are absorbed into counter <nmi_counter>: 1 register on signal <nmi_counter>.
|
||||
The following registers are absorbed into counter <pfq_addr_in>: 1 register on signal <pfq_addr_in>.
|
||||
Unit <biu_min> synthesized (advanced).
|
||||
WARNING:Xst:2677 - Node <mcl6_feature_2> of sequential type is unconnected in block <biu_min>.
|
||||
WARNING:Xst:2677 - Node <mcl6_feature_3> of sequential type is unconnected in block <biu_min>.
|
||||
WARNING:Xst:2677 - Node <mcl6_feature_4> of sequential type is unconnected in block <biu_min>.
|
||||
WARNING:Xst:2677 - Node <mcl6_feature_5> of sequential type is unconnected in block <biu_min>.
|
||||
WARNING:Xst:2677 - Node <mcl6_feature_6> of sequential type is unconnected in block <biu_min>.
|
||||
WARNING:Xst:2677 - Node <mcl6_feature_7> of sequential type is unconnected in block <biu_min>.
|
||||
|
||||
=========================================================================
|
||||
Advanced HDL Synthesis Report
|
||||
|
||||
Macro Statistics
|
||||
# Adders/Subtractors : 7
|
||||
13-bit adder : 1
|
||||
16-bit adder : 1
|
||||
20-bit adder : 4
|
||||
8-bit adder : 1
|
||||
# Counters : 5
|
||||
13-bit down counter : 1
|
||||
16-bit up counter : 2
|
||||
26-bit up counter : 1
|
||||
27-bit up counter : 1
|
||||
# Registers : 913
|
||||
Flip-Flops : 913
|
||||
# Comparators : 4
|
||||
1-bit comparator equal : 1
|
||||
2-bit comparator equal : 1
|
||||
4-bit comparator greater : 2
|
||||
# Multiplexers : 209
|
||||
1-bit 16-to-1 multiplexer : 32
|
||||
1-bit 2-to-1 multiplexer : 131
|
||||
1-bit 4-to-1 multiplexer : 16
|
||||
13-bit 2-to-1 multiplexer : 7
|
||||
16-bit 2-to-1 multiplexer : 1
|
||||
2-bit 2-to-1 multiplexer : 1
|
||||
20-bit 2-to-1 multiplexer : 3
|
||||
20-bit 7-to-1 multiplexer : 1
|
||||
3-bit 2-to-1 multiplexer : 1
|
||||
52-bit 2-to-1 multiplexer : 1
|
||||
8-bit 2-to-1 multiplexer : 14
|
||||
8-bit 4-to-1 multiplexer : 1
|
||||
# Xors : 20
|
||||
1-bit xor2 : 2
|
||||
1-bit xor3 : 16
|
||||
1-bit xor8 : 1
|
||||
16-bit xor2 : 1
|
||||
|
||||
=========================================================================
|
||||
|
||||
=========================================================================
|
||||
* Low Level Synthesis *
|
||||
=========================================================================
|
||||
WARNING:Xst:2677 - Node <prescaler_22> of sequential type is unconnected in block <MCL86jr>.
|
||||
WARNING:Xst:2677 - Node <prescaler_23> of sequential type is unconnected in block <MCL86jr>.
|
||||
WARNING:Xst:2677 - Node <prescaler_24> of sequential type is unconnected in block <MCL86jr>.
|
||||
WARNING:Xst:2677 - Node <prescaler_25> of sequential type is unconnected in block <MCL86jr>.
|
||||
WARNING:Xst:2677 - Node <prescaler_26> of sequential type is unconnected in block <MCL86jr>.
|
||||
|
||||
Optimizing unit <MCL86jr> ...
|
||||
|
||||
Optimizing unit <biu_min> ...
|
||||
|
||||
Optimizing unit <mcl86_eu_core> ...
|
||||
INFO:Xst:2261 - The FF/Latch <BIU_CORE/eu_biu_req_d1> in Unit <MCL86jr> is equivalent to the following FF/Latch, which will be removed : <EU_CORE/eu_biu_req_d1>
|
||||
|
||||
Mapping all equations...
|
||||
Building and optimizing final netlist ...
|
||||
Found area constraint ratio of 100 (+ 5) on block MCL86jr, actual ratio is 32.
|
||||
|
||||
Final Macro Processing ...
|
||||
|
||||
Processing Unit <MCL86jr> :
|
||||
Found 2-bit shift register for signal <t_biu_ad_oe_d2>.
|
||||
Found 2-bit shift register for signal <t_reset_d2>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_15>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_14>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_13>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_12>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_11>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_10>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_9>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_8>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_7>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_6>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_5>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_4>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_3>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_2>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_1>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_0>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_15>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_14>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_13>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_12>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_11>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_10>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_9>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_8>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_7>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_6>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_5>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_4>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_3>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_2>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_1>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_0>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_15>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_14>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_13>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_12>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_11>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_10>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_9>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_8>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_7>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_6>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_5>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_4>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_3>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_2>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_1>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_0>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_15>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_14>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_13>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_12>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_11>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_10>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_9>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_8>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_7>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_6>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_5>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_4>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_3>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_2>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_1>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_0>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_15>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_14>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_13>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_12>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_11>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_10>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_9>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_8>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_7>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_6>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_5>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_4>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_3>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_2>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_1>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_0>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_15>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_14>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_13>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_12>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_11>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_10>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_9>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_8>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_7>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_6>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_5>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_4>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_3>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_2>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_1>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_0>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_15>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_14>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_13>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_12>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_11>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_10>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_9>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_8>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_7>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_6>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_5>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_4>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_3>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_2>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_1>.
|
||||
Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_0>.
|
||||
Unit <MCL86jr> processed.
|
||||
|
||||
=========================================================================
|
||||
Final Register Report
|
||||
|
||||
Macro Statistics
|
||||
# Registers : 777
|
||||
Flip-Flops : 777
|
||||
# Shift Registers : 114
|
||||
2-bit shift register : 114
|
||||
|
||||
=========================================================================
|
||||
|
||||
=========================================================================
|
||||
* Partition Report *
|
||||
=========================================================================
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
=========================================================================
|
||||
* Design Summary *
|
||||
=========================================================================
|
||||
|
||||
Top Level Output File Name : MCL86jr.ngc
|
||||
|
||||
Primitive and Black Box Usage:
|
||||
------------------------------
|
||||
# BELS : 1407
|
||||
# GND : 2
|
||||
# INV : 15
|
||||
# LUT1 : 60
|
||||
# LUT2 : 87
|
||||
# LUT3 : 116
|
||||
# LUT4 : 73
|
||||
# LUT5 : 223
|
||||
# LUT6 : 384
|
||||
# MUXCY : 175
|
||||
# MUXF7 : 59
|
||||
# MUXF8 : 25
|
||||
# VCC : 2
|
||||
# XORCY : 186
|
||||
# FlipFlops/Latches : 892
|
||||
# FD : 48
|
||||
# FDE : 183
|
||||
# FDR : 125
|
||||
# FDRE : 503
|
||||
# FDS : 13
|
||||
# FDSE : 20
|
||||
# RAMS : 8
|
||||
# RAMB16BWER : 7
|
||||
# RAMB8BWER : 1
|
||||
# Shift Registers : 114
|
||||
# SRLC16E : 114
|
||||
# Clock Buffers : 1
|
||||
# BUFG : 1
|
||||
# IO Buffers : 75
|
||||
# IBUF : 5
|
||||
# IBUFG : 1
|
||||
# IOBUF : 16
|
||||
# OBUF : 53
|
||||
# DCMs : 1
|
||||
# DCM_SP : 1
|
||||
|
||||
Device utilization summary:
|
||||
---------------------------
|
||||
|
||||
Selected Device : 6slx9tqg144-3
|
||||
|
||||
|
||||
Slice Logic Utilization:
|
||||
Number of Slice Registers: 892 out of 11440 7%
|
||||
Number of Slice LUTs: 1072 out of 5720 18%
|
||||
Number used as Logic: 958 out of 5720 16%
|
||||
Number used as Memory: 114 out of 1440 7%
|
||||
Number used as SRL: 114
|
||||
|
||||
Slice Logic Distribution:
|
||||
Number of LUT Flip Flop pairs used: 1452
|
||||
Number with an unused Flip Flop: 560 out of 1452 38%
|
||||
Number with an unused LUT: 380 out of 1452 26%
|
||||
Number of fully used LUT-FF pairs: 512 out of 1452 35%
|
||||
Number of unique control sets: 41
|
||||
|
||||
IO Utilization:
|
||||
Number of IOs: 75
|
||||
Number of bonded IOBs: 75 out of 102 73%
|
||||
|
||||
Specific Feature Utilization:
|
||||
Number of Block RAM/FIFO: 8 out of 32 25%
|
||||
Number using Block RAM only: 8
|
||||
Number of BUFG/BUFGCTRLs: 1 out of 16 6%
|
||||
|
||||
---------------------------
|
||||
Partition Resource Summary:
|
||||
---------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
---------------------------
|
||||
|
||||
|
||||
=========================================================================
|
||||
Timing Report
|
||||
|
||||
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
||||
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
||||
GENERATED AFTER PLACE-and-ROUTE.
|
||||
|
||||
Clock Information:
|
||||
------------------
|
||||
-----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------+-------+
|
||||
Clock Signal | Clock buffer(FF name) | Load |
|
||||
-----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------+-------+
|
||||
CORE_CLK | DCM_SP:CLKFX | 1014 |
|
||||
EU_CORE/EU4Kx32_i/N1 | NONE(EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram)| 8 |
|
||||
-----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------+-------+
|
||||
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
||||
|
||||
Asynchronous Control Signals Information:
|
||||
----------------------------------------
|
||||
No asynchronous control signals found in this design
|
||||
|
||||
Timing Summary:
|
||||
---------------
|
||||
Speed Grade: -3
|
||||
|
||||
Minimum period: 20.419ns (Maximum Frequency: 48.973MHz)
|
||||
Minimum input arrival time before clock: 3.307ns
|
||||
Maximum output required time after clock: 4.642ns
|
||||
Maximum combinational path delay: No path found
|
||||
|
||||
Timing Details:
|
||||
---------------
|
||||
All values displayed in nanoseconds (ns)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default period analysis for Clock 'CORE_CLK'
|
||||
Clock period: 20.419ns (frequency: 48.973MHz)
|
||||
Total number of paths / destination ports: 513942 / 2565
|
||||
-------------------------------------------------------------------------
|
||||
Delay: 9.282ns (Levels of Logic = 9)
|
||||
Source: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (RAM)
|
||||
Destination: EU_CORE/eu_register_r0_15 (FF)
|
||||
Source Clock: CORE_CLK rising 2.2X
|
||||
Destination Clock: CORE_CLK rising 2.2X
|
||||
|
||||
Data Path: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram to EU_CORE/eu_register_r0_15
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
RAMB16BWER:CLKA->DOA7 1 1.850 0.684 U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<7>)
|
||||
LUT3:I1->O 88 0.203 1.903 U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux141 (douta<21>)
|
||||
end scope: 'EU_CORE/EU4Kx32_i:douta<21>'
|
||||
LUT5:I3->O 1 0.203 0.000 EU_CORE/mux30_4 (EU_CORE/mux30_4)
|
||||
MUXF7:I1->O 1 0.140 0.000 EU_CORE/mux30_3_f7 (EU_CORE/mux30_3_f7)
|
||||
MUXF8:I1->O 10 0.152 1.085 EU_CORE/mux30_2_f8 (EU_CORE/eu_operand0<8>1)
|
||||
LUT6:I3->O 2 0.205 0.617 EU_CORE/carry<7>1_SW0 (N146)
|
||||
LUT5:I4->O 1 0.205 0.808 EU_CORE/carry<9>1_SW0 (N152)
|
||||
LUT5:I2->O 5 0.205 0.715 EU_CORE/carry<11>1 (EU_CORE/carry<11>)
|
||||
LUT6:I5->O 16 0.205 0.000 EU_CORE/Mmux_n045534 (EU_CORE/n0455<11>)
|
||||
FDRE:D 0.102 EU_CORE/eu_register_ax_11
|
||||
----------------------------------------
|
||||
Total 9.282ns (3.470ns logic, 5.812ns route)
|
||||
(37.4% logic, 62.6% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default OFFSET IN BEFORE for Clock 'CORE_CLK'
|
||||
Total number of paths / destination ports: 37 / 37
|
||||
-------------------------------------------------------------------------
|
||||
Offset: 3.307ns (Levels of Logic = 3)
|
||||
Source: SRAM_D<1> (PAD)
|
||||
Destination: BIU_CORE/biu_return_data_int_9 (FF)
|
||||
Destination Clock: CORE_CLK rising 2.2X
|
||||
|
||||
Data Path: SRAM_D<1> to BIU_CORE/biu_return_data_int_9
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
IOBUF:IO->O 3 1.222 0.995 SRAM_D_1_IOBUF (N103)
|
||||
LUT5:I0->O 1 0.203 0.580 BIU_CORE/biu_state[7]_biu_return_data_int[15]_select_249_OUT<6>_SW1 (N215)
|
||||
LUT5:I4->O 1 0.205 0.000 BIU_CORE/biu_state[7]_biu_return_data_int[15]_select_249_OUT<6> (BIU_CORE/biu_state[7]_biu_return_data_int[15]_select_249_OUT<9>)
|
||||
FDR:D 0.102 BIU_CORE/biu_return_data_int_9
|
||||
----------------------------------------
|
||||
Total 3.307ns (1.732ns logic, 1.575ns route)
|
||||
(52.4% logic, 47.6% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default OFFSET OUT AFTER for Clock 'CORE_CLK'
|
||||
Total number of paths / destination ports: 82 / 66
|
||||
-------------------------------------------------------------------------
|
||||
Offset: 4.642ns (Levels of Logic = 2)
|
||||
Source: BIU_CORE/SRAM_D_OE (FF)
|
||||
Destination: SRAM_D<7> (PAD)
|
||||
Source Clock: CORE_CLK rising 2.2X
|
||||
|
||||
Data Path: BIU_CORE/SRAM_D_OE to SRAM_D<7>
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
FDR:C->Q 2 0.447 0.616 BIU_CORE/SRAM_D_OE (BIU_CORE/SRAM_D_OE)
|
||||
INV:I->O 8 0.206 0.802 t_sram_d_oe_inv1_INV_0 (t_sram_d_oe_inv)
|
||||
IOBUF:T->IO 2.571 SRAM_D_7_IOBUF (SRAM_D<7>)
|
||||
----------------------------------------
|
||||
Total 4.642ns (3.224ns logic, 1.418ns route)
|
||||
(69.5% logic, 30.5% route)
|
||||
|
||||
=========================================================================
|
||||
|
||||
Cross Clock Domains Report:
|
||||
--------------------------
|
||||
|
||||
Clock to Setup on destination clock CORE_CLK
|
||||
---------------+---------+---------+---------+---------+
|
||||
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
||||
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
||||
---------------+---------+---------+---------+---------+
|
||||
CORE_CLK | 9.282| | | |
|
||||
---------------+---------+---------+---------+---------+
|
||||
|
||||
=========================================================================
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 17.00 secs
|
||||
Total CPU time to Xst completion: 16.43 secs
|
||||
|
||||
-->
|
||||
|
||||
Total memory usage is 268688 kilobytes
|
||||
|
||||
Number of errors : 0 ( 0 filtered)
|
||||
Number of warnings : 55 ( 0 filtered)
|
||||
Number of infos : 4 ( 0 filtered)
|
||||
|
||||
|
|
@ -0,0 +1,694 @@
|
|||
--------------------------------------------------------------------------------
|
||||
Release 14.7 Trace (nt64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3
|
||||
-n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf
|
||||
MCL86jr.ucf
|
||||
|
||||
Design file: MCL86jr.ncd
|
||||
Physical constraint file: MCL86jr.pcf
|
||||
Device,package,speed: xc6slx9,tqg144,C,-3 (PRODUCTION 1.23 2013-10-13)
|
||||
Report level: verbose report
|
||||
|
||||
Environment Variable Effect
|
||||
-------------------- ------
|
||||
NONE No environment variables were set
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
|
||||
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
|
||||
option. All paths that are not constrained will be reported in the
|
||||
unconstrained paths section(s) of the report.
|
||||
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
|
||||
a 50 Ohm transmission line loading model. For the details of this model,
|
||||
and for more information on accounting for different loading conditions,
|
||||
please see the device datasheet.
|
||||
|
||||
================================================================================
|
||||
Timing constraint: TS_CORE_CLK = PERIOD TIMEGRP "CORE_CLK" 20 ns HIGH 50%;
|
||||
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
|
||||
|
||||
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
||||
0 timing errors detected. (0 component switching limit errors)
|
||||
Minimum period is 8.000ns.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Component Switching Limit Checks: TS_CORE_CLK = PERIOD TIMEGRP "CORE_CLK" 20 ns HIGH 50%;
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 6.421ns (period - min period limit)
|
||||
Period: 9.091ns
|
||||
Min period limit: 2.670ns (374.532MHz) (Tdcmper_CLKFX)
|
||||
Physical resource: SPARTAN6PLL/dcm_sp_inst/CLKFX
|
||||
Logical resource: SPARTAN6PLL/dcm_sp_inst/CLKFX
|
||||
Location pin: DCM_X0Y1.CLKFX
|
||||
Clock network: SPARTAN6PLL/clkfx
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 12.000ns (period - (min low pulse limit / (low pulse / period)))
|
||||
Period: 20.000ns
|
||||
Low pulse: 10.000ns
|
||||
Low pulse limit: 4.000ns (Tdcmpw_CLKIN_50_100)
|
||||
Physical resource: SPARTAN6PLL/dcm_sp_inst/CLKIN
|
||||
Logical resource: SPARTAN6PLL/dcm_sp_inst/CLKIN
|
||||
Location pin: DCM_X0Y1.CLKIN
|
||||
Clock network: SPARTAN6PLL/dcm_sp_inst_ML_NEW_DIVCLK
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 12.000ns (period - (min high pulse limit / (high pulse / period)))
|
||||
Period: 20.000ns
|
||||
High pulse: 10.000ns
|
||||
High pulse limit: 4.000ns (Tdcmpw_CLKIN_50_100)
|
||||
Physical resource: SPARTAN6PLL/dcm_sp_inst/CLKIN
|
||||
Logical resource: SPARTAN6PLL/dcm_sp_inst/CLKIN
|
||||
Location pin: DCM_X0Y1.CLKIN
|
||||
Clock network: SPARTAN6PLL/dcm_sp_inst_ML_NEW_DIVCLK
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
================================================================================
|
||||
Timing constraint: TS_SPARTAN6PLL_clkfx = PERIOD TIMEGRP "SPARTAN6PLL_clkfx"
|
||||
TS_CORE_CLK / 2.2 HIGH 50%;
|
||||
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
|
||||
|
||||
513828 paths analyzed, 3870 endpoints analyzed, 0 failing endpoints
|
||||
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
|
||||
Minimum period is 8.791ns.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point EU_CORE/eu_flags_12 (SLICE_X15Y29.BX), 2245 paths
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (setup path): 0.299ns (requirement - (data path - clock path skew + uncertainty))
|
||||
Source: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (RAM)
|
||||
Destination: EU_CORE/eu_flags_12 (FF)
|
||||
Requirement: 9.090ns
|
||||
Data Path Delay: 8.558ns (Levels of Logic = 6)
|
||||
Clock Path Skew: -0.007ns (0.243 - 0.250)
|
||||
Source Clock: core_clk_int rising at 0.000ns
|
||||
Destination Clock: core_clk_int rising at 9.090ns
|
||||
Clock Uncertainty: 0.226ns
|
||||
|
||||
Clock Uncertainty: 0.226ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Total Input Jitter (TIJ): 0.000ns
|
||||
Discrete Jitter (DJ): 0.381ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Maximum Data Path at Slow Process Corner: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram to EU_CORE/eu_flags_12
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
RAMB16_X1Y10.DOA5 Trcko_DOA 1.850 EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
|
||||
SLICE_X17Y23.B3 net (fanout=1) 1.070 EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<5>
|
||||
SLICE_X17Y23.B Tilo 0.259 EU_CORE/eu_register_r0<3>
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux111
|
||||
SLICE_X12Y22.BX net (fanout=18) 0.850 EU_CORE/eu_rom_data<19>
|
||||
SLICE_X12Y22.BMUX Tbxb 0.157 EU_CORE/eu_biu_dataout<3>
|
||||
EU_CORE/mux14_2_f8
|
||||
SLICE_X13Y25.D1 net (fanout=5) 0.878 EU_CORE/eu_operand1<8>
|
||||
SLICE_X13Y25.D Tilo 0.259 EU_CORE/eu_register_r2<11>
|
||||
EU_CORE/carry<7>1_SW1
|
||||
SLICE_X13Y25.C6 net (fanout=3) 0.132 N147
|
||||
SLICE_X13Y25.C Tilo 0.259 EU_CORE/eu_register_r2<11>
|
||||
EU_CORE/carry<9>1_SW1
|
||||
SLICE_X15Y24.C2 net (fanout=1) 0.804 N153
|
||||
SLICE_X15Y24.C Tilo 0.259 EU_CORE/eu_alu_last_result<11>
|
||||
EU_CORE/carry<11>1
|
||||
SLICE_X17Y30.A5 net (fanout=7) 0.811 EU_CORE/carry<11>
|
||||
SLICE_X17Y30.A Tilo 0.259 EU_CORE/eu_register_r1<15>
|
||||
EU_CORE/Mmux_n045543
|
||||
SLICE_X15Y29.BX net (fanout=13) 0.648 EU_CORE/n0455<12>
|
||||
SLICE_X15Y29.CLK Tdick 0.063 EU_CORE/eu_flags<14>
|
||||
EU_CORE/eu_flags_12
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 8.558ns (3.365ns logic, 5.193ns route)
|
||||
(39.3% logic, 60.7% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (setup path): 0.368ns (requirement - (data path - clock path skew + uncertainty))
|
||||
Source: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (RAM)
|
||||
Destination: EU_CORE/eu_flags_12 (FF)
|
||||
Requirement: 9.090ns
|
||||
Data Path Delay: 8.492ns (Levels of Logic = 6)
|
||||
Clock Path Skew: -0.004ns (0.243 - 0.247)
|
||||
Source Clock: core_clk_int rising at 0.000ns
|
||||
Destination Clock: core_clk_int rising at 9.090ns
|
||||
Clock Uncertainty: 0.226ns
|
||||
|
||||
Clock Uncertainty: 0.226ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Total Input Jitter (TIJ): 0.000ns
|
||||
Discrete Jitter (DJ): 0.381ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Maximum Data Path at Slow Process Corner: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram to EU_CORE/eu_flags_12
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
RAMB16_X1Y12.DOA2 Trcko_DOA 1.850 EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
|
||||
SLICE_X13Y21.B3 net (fanout=2) 1.098 EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<2>
|
||||
SLICE_X13Y21.B Tilo 0.259 BIU_CORE/pfq_addr_out_d1<15>
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux81
|
||||
SLICE_X12Y22.D4 net (fanout=49) 0.520 EU_CORE/eu_rom_data<16>
|
||||
SLICE_X12Y22.BMUX Topdb 0.393 EU_CORE/eu_biu_dataout<3>
|
||||
EU_CORE/mux14_6
|
||||
EU_CORE/mux14_4_f7
|
||||
EU_CORE/mux14_2_f8
|
||||
SLICE_X13Y25.D1 net (fanout=5) 0.878 EU_CORE/eu_operand1<8>
|
||||
SLICE_X13Y25.D Tilo 0.259 EU_CORE/eu_register_r2<11>
|
||||
EU_CORE/carry<7>1_SW1
|
||||
SLICE_X13Y25.C6 net (fanout=3) 0.132 N147
|
||||
SLICE_X13Y25.C Tilo 0.259 EU_CORE/eu_register_r2<11>
|
||||
EU_CORE/carry<9>1_SW1
|
||||
SLICE_X15Y24.C2 net (fanout=1) 0.804 N153
|
||||
SLICE_X15Y24.C Tilo 0.259 EU_CORE/eu_alu_last_result<11>
|
||||
EU_CORE/carry<11>1
|
||||
SLICE_X17Y30.A5 net (fanout=7) 0.811 EU_CORE/carry<11>
|
||||
SLICE_X17Y30.A Tilo 0.259 EU_CORE/eu_register_r1<15>
|
||||
EU_CORE/Mmux_n045543
|
||||
SLICE_X15Y29.BX net (fanout=13) 0.648 EU_CORE/n0455<12>
|
||||
SLICE_X15Y29.CLK Tdick 0.063 EU_CORE/eu_flags<14>
|
||||
EU_CORE/eu_flags_12
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 8.492ns (3.601ns logic, 4.891ns route)
|
||||
(42.4% logic, 57.6% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (setup path): 0.375ns (requirement - (data path - clock path skew + uncertainty))
|
||||
Source: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (RAM)
|
||||
Destination: EU_CORE/eu_flags_12 (FF)
|
||||
Requirement: 9.090ns
|
||||
Data Path Delay: 8.485ns (Levels of Logic = 6)
|
||||
Clock Path Skew: -0.004ns (0.243 - 0.247)
|
||||
Source Clock: core_clk_int rising at 0.000ns
|
||||
Destination Clock: core_clk_int rising at 9.090ns
|
||||
Clock Uncertainty: 0.226ns
|
||||
|
||||
Clock Uncertainty: 0.226ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Total Input Jitter (TIJ): 0.000ns
|
||||
Discrete Jitter (DJ): 0.381ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Maximum Data Path at Slow Process Corner: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram to EU_CORE/eu_flags_12
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
RAMB16_X1Y12.DOA2 Trcko_DOA 1.850 EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
|
||||
SLICE_X13Y21.B3 net (fanout=2) 1.098 EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<2>
|
||||
SLICE_X13Y21.B Tilo 0.259 BIU_CORE/pfq_addr_out_d1<15>
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux81
|
||||
SLICE_X12Y22.C4 net (fanout=49) 0.520 EU_CORE/eu_rom_data<16>
|
||||
SLICE_X12Y22.BMUX Topcb 0.386 EU_CORE/eu_biu_dataout<3>
|
||||
EU_CORE/mux14_51
|
||||
EU_CORE/mux14_4_f7
|
||||
EU_CORE/mux14_2_f8
|
||||
SLICE_X13Y25.D1 net (fanout=5) 0.878 EU_CORE/eu_operand1<8>
|
||||
SLICE_X13Y25.D Tilo 0.259 EU_CORE/eu_register_r2<11>
|
||||
EU_CORE/carry<7>1_SW1
|
||||
SLICE_X13Y25.C6 net (fanout=3) 0.132 N147
|
||||
SLICE_X13Y25.C Tilo 0.259 EU_CORE/eu_register_r2<11>
|
||||
EU_CORE/carry<9>1_SW1
|
||||
SLICE_X15Y24.C2 net (fanout=1) 0.804 N153
|
||||
SLICE_X15Y24.C Tilo 0.259 EU_CORE/eu_alu_last_result<11>
|
||||
EU_CORE/carry<11>1
|
||||
SLICE_X17Y30.A5 net (fanout=7) 0.811 EU_CORE/carry<11>
|
||||
SLICE_X17Y30.A Tilo 0.259 EU_CORE/eu_register_r1<15>
|
||||
EU_CORE/Mmux_n045543
|
||||
SLICE_X15Y29.BX net (fanout=13) 0.648 EU_CORE/n0455<12>
|
||||
SLICE_X15Y29.CLK Tdick 0.063 EU_CORE/eu_flags<14>
|
||||
EU_CORE/eu_flags_12
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 8.485ns (3.594ns logic, 4.891ns route)
|
||||
(42.4% logic, 57.6% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point EU_CORE/eu_alu_last_result_12 (SLICE_X18Y30.AX), 2245 paths
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (setup path): 0.306ns (requirement - (data path - clock path skew + uncertainty))
|
||||
Source: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (RAM)
|
||||
Destination: EU_CORE/eu_alu_last_result_12 (FF)
|
||||
Requirement: 9.090ns
|
||||
Data Path Delay: 8.553ns (Levels of Logic = 6)
|
||||
Clock Path Skew: -0.005ns (0.245 - 0.250)
|
||||
Source Clock: core_clk_int rising at 0.000ns
|
||||
Destination Clock: core_clk_int rising at 9.090ns
|
||||
Clock Uncertainty: 0.226ns
|
||||
|
||||
Clock Uncertainty: 0.226ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Total Input Jitter (TIJ): 0.000ns
|
||||
Discrete Jitter (DJ): 0.381ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Maximum Data Path at Slow Process Corner: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram to EU_CORE/eu_alu_last_result_12
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
RAMB16_X1Y10.DOA5 Trcko_DOA 1.850 EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
|
||||
SLICE_X17Y23.B3 net (fanout=1) 1.070 EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<5>
|
||||
SLICE_X17Y23.B Tilo 0.259 EU_CORE/eu_register_r0<3>
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux111
|
||||
SLICE_X12Y22.BX net (fanout=18) 0.850 EU_CORE/eu_rom_data<19>
|
||||
SLICE_X12Y22.BMUX Tbxb 0.157 EU_CORE/eu_biu_dataout<3>
|
||||
EU_CORE/mux14_2_f8
|
||||
SLICE_X13Y25.D1 net (fanout=5) 0.878 EU_CORE/eu_operand1<8>
|
||||
SLICE_X13Y25.D Tilo 0.259 EU_CORE/eu_register_r2<11>
|
||||
EU_CORE/carry<7>1_SW1
|
||||
SLICE_X13Y25.C6 net (fanout=3) 0.132 N147
|
||||
SLICE_X13Y25.C Tilo 0.259 EU_CORE/eu_register_r2<11>
|
||||
EU_CORE/carry<9>1_SW1
|
||||
SLICE_X15Y24.C2 net (fanout=1) 0.804 N153
|
||||
SLICE_X15Y24.C Tilo 0.259 EU_CORE/eu_alu_last_result<11>
|
||||
EU_CORE/carry<11>1
|
||||
SLICE_X17Y30.A5 net (fanout=7) 0.811 EU_CORE/carry<11>
|
||||
SLICE_X17Y30.A Tilo 0.259 EU_CORE/eu_register_r1<15>
|
||||
EU_CORE/Mmux_n045543
|
||||
SLICE_X18Y30.AX net (fanout=13) 0.570 EU_CORE/n0455<12>
|
||||
SLICE_X18Y30.CLK Tdick 0.136 EU_CORE/eu_alu_last_result<15>
|
||||
EU_CORE/eu_alu_last_result_12
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 8.553ns (3.438ns logic, 5.115ns route)
|
||||
(40.2% logic, 59.8% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (setup path): 0.375ns (requirement - (data path - clock path skew + uncertainty))
|
||||
Source: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (RAM)
|
||||
Destination: EU_CORE/eu_alu_last_result_12 (FF)
|
||||
Requirement: 9.090ns
|
||||
Data Path Delay: 8.487ns (Levels of Logic = 6)
|
||||
Clock Path Skew: -0.002ns (0.245 - 0.247)
|
||||
Source Clock: core_clk_int rising at 0.000ns
|
||||
Destination Clock: core_clk_int rising at 9.090ns
|
||||
Clock Uncertainty: 0.226ns
|
||||
|
||||
Clock Uncertainty: 0.226ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Total Input Jitter (TIJ): 0.000ns
|
||||
Discrete Jitter (DJ): 0.381ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Maximum Data Path at Slow Process Corner: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram to EU_CORE/eu_alu_last_result_12
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
RAMB16_X1Y12.DOA2 Trcko_DOA 1.850 EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
|
||||
SLICE_X13Y21.B3 net (fanout=2) 1.098 EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<2>
|
||||
SLICE_X13Y21.B Tilo 0.259 BIU_CORE/pfq_addr_out_d1<15>
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux81
|
||||
SLICE_X12Y22.D4 net (fanout=49) 0.520 EU_CORE/eu_rom_data<16>
|
||||
SLICE_X12Y22.BMUX Topdb 0.393 EU_CORE/eu_biu_dataout<3>
|
||||
EU_CORE/mux14_6
|
||||
EU_CORE/mux14_4_f7
|
||||
EU_CORE/mux14_2_f8
|
||||
SLICE_X13Y25.D1 net (fanout=5) 0.878 EU_CORE/eu_operand1<8>
|
||||
SLICE_X13Y25.D Tilo 0.259 EU_CORE/eu_register_r2<11>
|
||||
EU_CORE/carry<7>1_SW1
|
||||
SLICE_X13Y25.C6 net (fanout=3) 0.132 N147
|
||||
SLICE_X13Y25.C Tilo 0.259 EU_CORE/eu_register_r2<11>
|
||||
EU_CORE/carry<9>1_SW1
|
||||
SLICE_X15Y24.C2 net (fanout=1) 0.804 N153
|
||||
SLICE_X15Y24.C Tilo 0.259 EU_CORE/eu_alu_last_result<11>
|
||||
EU_CORE/carry<11>1
|
||||
SLICE_X17Y30.A5 net (fanout=7) 0.811 EU_CORE/carry<11>
|
||||
SLICE_X17Y30.A Tilo 0.259 EU_CORE/eu_register_r1<15>
|
||||
EU_CORE/Mmux_n045543
|
||||
SLICE_X18Y30.AX net (fanout=13) 0.570 EU_CORE/n0455<12>
|
||||
SLICE_X18Y30.CLK Tdick 0.136 EU_CORE/eu_alu_last_result<15>
|
||||
EU_CORE/eu_alu_last_result_12
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 8.487ns (3.674ns logic, 4.813ns route)
|
||||
(43.3% logic, 56.7% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (setup path): 0.382ns (requirement - (data path - clock path skew + uncertainty))
|
||||
Source: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (RAM)
|
||||
Destination: EU_CORE/eu_alu_last_result_12 (FF)
|
||||
Requirement: 9.090ns
|
||||
Data Path Delay: 8.480ns (Levels of Logic = 6)
|
||||
Clock Path Skew: -0.002ns (0.245 - 0.247)
|
||||
Source Clock: core_clk_int rising at 0.000ns
|
||||
Destination Clock: core_clk_int rising at 9.090ns
|
||||
Clock Uncertainty: 0.226ns
|
||||
|
||||
Clock Uncertainty: 0.226ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Total Input Jitter (TIJ): 0.000ns
|
||||
Discrete Jitter (DJ): 0.381ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Maximum Data Path at Slow Process Corner: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram to EU_CORE/eu_alu_last_result_12
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
RAMB16_X1Y12.DOA2 Trcko_DOA 1.850 EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
|
||||
SLICE_X13Y21.B3 net (fanout=2) 1.098 EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<2>
|
||||
SLICE_X13Y21.B Tilo 0.259 BIU_CORE/pfq_addr_out_d1<15>
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux81
|
||||
SLICE_X12Y22.C4 net (fanout=49) 0.520 EU_CORE/eu_rom_data<16>
|
||||
SLICE_X12Y22.BMUX Topcb 0.386 EU_CORE/eu_biu_dataout<3>
|
||||
EU_CORE/mux14_51
|
||||
EU_CORE/mux14_4_f7
|
||||
EU_CORE/mux14_2_f8
|
||||
SLICE_X13Y25.D1 net (fanout=5) 0.878 EU_CORE/eu_operand1<8>
|
||||
SLICE_X13Y25.D Tilo 0.259 EU_CORE/eu_register_r2<11>
|
||||
EU_CORE/carry<7>1_SW1
|
||||
SLICE_X13Y25.C6 net (fanout=3) 0.132 N147
|
||||
SLICE_X13Y25.C Tilo 0.259 EU_CORE/eu_register_r2<11>
|
||||
EU_CORE/carry<9>1_SW1
|
||||
SLICE_X15Y24.C2 net (fanout=1) 0.804 N153
|
||||
SLICE_X15Y24.C Tilo 0.259 EU_CORE/eu_alu_last_result<11>
|
||||
EU_CORE/carry<11>1
|
||||
SLICE_X17Y30.A5 net (fanout=7) 0.811 EU_CORE/carry<11>
|
||||
SLICE_X17Y30.A Tilo 0.259 EU_CORE/eu_register_r1<15>
|
||||
EU_CORE/Mmux_n045543
|
||||
SLICE_X18Y30.AX net (fanout=13) 0.570 EU_CORE/n0455<12>
|
||||
SLICE_X18Y30.CLK Tdick 0.136 EU_CORE/eu_alu_last_result<15>
|
||||
EU_CORE/eu_alu_last_result_12
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 8.480ns (3.667ns logic, 4.813ns route)
|
||||
(43.2% logic, 56.8% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point EU_CORE/eu_register_di_12 (SLICE_X17Y27.CX), 2245 paths
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (setup path): 0.316ns (requirement - (data path - clock path skew + uncertainty))
|
||||
Source: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (RAM)
|
||||
Destination: EU_CORE/eu_register_di_12 (FF)
|
||||
Requirement: 9.090ns
|
||||
Data Path Delay: 8.538ns (Levels of Logic = 6)
|
||||
Clock Path Skew: -0.010ns (0.240 - 0.250)
|
||||
Source Clock: core_clk_int rising at 0.000ns
|
||||
Destination Clock: core_clk_int rising at 9.090ns
|
||||
Clock Uncertainty: 0.226ns
|
||||
|
||||
Clock Uncertainty: 0.226ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Total Input Jitter (TIJ): 0.000ns
|
||||
Discrete Jitter (DJ): 0.381ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Maximum Data Path at Slow Process Corner: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram to EU_CORE/eu_register_di_12
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
RAMB16_X1Y10.DOA5 Trcko_DOA 1.850 EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
|
||||
SLICE_X17Y23.B3 net (fanout=1) 1.070 EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<5>
|
||||
SLICE_X17Y23.B Tilo 0.259 EU_CORE/eu_register_r0<3>
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux111
|
||||
SLICE_X12Y22.BX net (fanout=18) 0.850 EU_CORE/eu_rom_data<19>
|
||||
SLICE_X12Y22.BMUX Tbxb 0.157 EU_CORE/eu_biu_dataout<3>
|
||||
EU_CORE/mux14_2_f8
|
||||
SLICE_X13Y25.D1 net (fanout=5) 0.878 EU_CORE/eu_operand1<8>
|
||||
SLICE_X13Y25.D Tilo 0.259 EU_CORE/eu_register_r2<11>
|
||||
EU_CORE/carry<7>1_SW1
|
||||
SLICE_X13Y25.C6 net (fanout=3) 0.132 N147
|
||||
SLICE_X13Y25.C Tilo 0.259 EU_CORE/eu_register_r2<11>
|
||||
EU_CORE/carry<9>1_SW1
|
||||
SLICE_X15Y24.C2 net (fanout=1) 0.804 N153
|
||||
SLICE_X15Y24.C Tilo 0.259 EU_CORE/eu_alu_last_result<11>
|
||||
EU_CORE/carry<11>1
|
||||
SLICE_X17Y30.A5 net (fanout=7) 0.811 EU_CORE/carry<11>
|
||||
SLICE_X17Y30.A Tilo 0.259 EU_CORE/eu_register_r1<15>
|
||||
EU_CORE/Mmux_n045543
|
||||
SLICE_X17Y27.CX net (fanout=13) 0.628 EU_CORE/n0455<12>
|
||||
SLICE_X17Y27.CLK Tdick 0.063 EU_CORE/eu_register_di<12>
|
||||
EU_CORE/eu_register_di_12
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 8.538ns (3.365ns logic, 5.173ns route)
|
||||
(39.4% logic, 60.6% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (setup path): 0.385ns (requirement - (data path - clock path skew + uncertainty))
|
||||
Source: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (RAM)
|
||||
Destination: EU_CORE/eu_register_di_12 (FF)
|
||||
Requirement: 9.090ns
|
||||
Data Path Delay: 8.472ns (Levels of Logic = 6)
|
||||
Clock Path Skew: -0.007ns (0.240 - 0.247)
|
||||
Source Clock: core_clk_int rising at 0.000ns
|
||||
Destination Clock: core_clk_int rising at 9.090ns
|
||||
Clock Uncertainty: 0.226ns
|
||||
|
||||
Clock Uncertainty: 0.226ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Total Input Jitter (TIJ): 0.000ns
|
||||
Discrete Jitter (DJ): 0.381ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Maximum Data Path at Slow Process Corner: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram to EU_CORE/eu_register_di_12
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
RAMB16_X1Y12.DOA2 Trcko_DOA 1.850 EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
|
||||
SLICE_X13Y21.B3 net (fanout=2) 1.098 EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<2>
|
||||
SLICE_X13Y21.B Tilo 0.259 BIU_CORE/pfq_addr_out_d1<15>
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux81
|
||||
SLICE_X12Y22.D4 net (fanout=49) 0.520 EU_CORE/eu_rom_data<16>
|
||||
SLICE_X12Y22.BMUX Topdb 0.393 EU_CORE/eu_biu_dataout<3>
|
||||
EU_CORE/mux14_6
|
||||
EU_CORE/mux14_4_f7
|
||||
EU_CORE/mux14_2_f8
|
||||
SLICE_X13Y25.D1 net (fanout=5) 0.878 EU_CORE/eu_operand1<8>
|
||||
SLICE_X13Y25.D Tilo 0.259 EU_CORE/eu_register_r2<11>
|
||||
EU_CORE/carry<7>1_SW1
|
||||
SLICE_X13Y25.C6 net (fanout=3) 0.132 N147
|
||||
SLICE_X13Y25.C Tilo 0.259 EU_CORE/eu_register_r2<11>
|
||||
EU_CORE/carry<9>1_SW1
|
||||
SLICE_X15Y24.C2 net (fanout=1) 0.804 N153
|
||||
SLICE_X15Y24.C Tilo 0.259 EU_CORE/eu_alu_last_result<11>
|
||||
EU_CORE/carry<11>1
|
||||
SLICE_X17Y30.A5 net (fanout=7) 0.811 EU_CORE/carry<11>
|
||||
SLICE_X17Y30.A Tilo 0.259 EU_CORE/eu_register_r1<15>
|
||||
EU_CORE/Mmux_n045543
|
||||
SLICE_X17Y27.CX net (fanout=13) 0.628 EU_CORE/n0455<12>
|
||||
SLICE_X17Y27.CLK Tdick 0.063 EU_CORE/eu_register_di<12>
|
||||
EU_CORE/eu_register_di_12
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 8.472ns (3.601ns logic, 4.871ns route)
|
||||
(42.5% logic, 57.5% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (setup path): 0.392ns (requirement - (data path - clock path skew + uncertainty))
|
||||
Source: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (RAM)
|
||||
Destination: EU_CORE/eu_register_di_12 (FF)
|
||||
Requirement: 9.090ns
|
||||
Data Path Delay: 8.465ns (Levels of Logic = 6)
|
||||
Clock Path Skew: -0.007ns (0.240 - 0.247)
|
||||
Source Clock: core_clk_int rising at 0.000ns
|
||||
Destination Clock: core_clk_int rising at 9.090ns
|
||||
Clock Uncertainty: 0.226ns
|
||||
|
||||
Clock Uncertainty: 0.226ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
||||
Total System Jitter (TSJ): 0.070ns
|
||||
Total Input Jitter (TIJ): 0.000ns
|
||||
Discrete Jitter (DJ): 0.381ns
|
||||
Phase Error (PE): 0.000ns
|
||||
|
||||
Maximum Data Path at Slow Process Corner: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram to EU_CORE/eu_register_di_12
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
RAMB16_X1Y12.DOA2 Trcko_DOA 1.850 EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
|
||||
SLICE_X13Y21.B3 net (fanout=2) 1.098 EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<2>
|
||||
SLICE_X13Y21.B Tilo 0.259 BIU_CORE/pfq_addr_out_d1<15>
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux81
|
||||
SLICE_X12Y22.C4 net (fanout=49) 0.520 EU_CORE/eu_rom_data<16>
|
||||
SLICE_X12Y22.BMUX Topcb 0.386 EU_CORE/eu_biu_dataout<3>
|
||||
EU_CORE/mux14_51
|
||||
EU_CORE/mux14_4_f7
|
||||
EU_CORE/mux14_2_f8
|
||||
SLICE_X13Y25.D1 net (fanout=5) 0.878 EU_CORE/eu_operand1<8>
|
||||
SLICE_X13Y25.D Tilo 0.259 EU_CORE/eu_register_r2<11>
|
||||
EU_CORE/carry<7>1_SW1
|
||||
SLICE_X13Y25.C6 net (fanout=3) 0.132 N147
|
||||
SLICE_X13Y25.C Tilo 0.259 EU_CORE/eu_register_r2<11>
|
||||
EU_CORE/carry<9>1_SW1
|
||||
SLICE_X15Y24.C2 net (fanout=1) 0.804 N153
|
||||
SLICE_X15Y24.C Tilo 0.259 EU_CORE/eu_alu_last_result<11>
|
||||
EU_CORE/carry<11>1
|
||||
SLICE_X17Y30.A5 net (fanout=7) 0.811 EU_CORE/carry<11>
|
||||
SLICE_X17Y30.A Tilo 0.259 EU_CORE/eu_register_r1<15>
|
||||
EU_CORE/Mmux_n045543
|
||||
SLICE_X17Y27.CX net (fanout=13) 0.628 EU_CORE/n0455<12>
|
||||
SLICE_X17Y27.CLK Tdick 0.063 EU_CORE/eu_register_di<12>
|
||||
EU_CORE/eu_register_di_12
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 8.465ns (3.594ns logic, 4.871ns route)
|
||||
(42.5% logic, 57.5% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Hold Paths: TS_SPARTAN6PLL_clkfx = PERIOD TIMEGRP "SPARTAN6PLL_clkfx" TS_CORE_CLK / 2.2
|
||||
HIGH 50%;
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point BIU_CORE/Mshreg_biu_return_data_int_d2_2 (SLICE_X12Y35.BX), 1 path
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (hold path): 0.367ns (requirement - (clock path skew + uncertainty - data path))
|
||||
Source: BIU_CORE/biu_return_data_int_2 (FF)
|
||||
Destination: BIU_CORE/Mshreg_biu_return_data_int_d2_2 (FF)
|
||||
Requirement: 0.000ns
|
||||
Data Path Delay: 0.369ns (Levels of Logic = 0)
|
||||
Clock Path Skew: 0.002ns (0.041 - 0.039)
|
||||
Source Clock: core_clk_int rising at 0.000ns
|
||||
Destination Clock: core_clk_int rising at 0.000ns
|
||||
Clock Uncertainty: 0.000ns
|
||||
|
||||
Minimum Data Path at Fast Process Corner: BIU_CORE/biu_return_data_int_2 to BIU_CORE/Mshreg_biu_return_data_int_d2_2
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
SLICE_X13Y35.AQ Tcko 0.198 BIU_CORE/biu_return_data_int_5
|
||||
BIU_CORE/biu_return_data_int_2
|
||||
SLICE_X12Y35.BX net (fanout=2) 0.251 BIU_CORE/biu_return_data_int_2
|
||||
SLICE_X12Y35.CLK Tdh (-Th) 0.080 BIU_CORE/biu_return_data_int_d2<5>
|
||||
BIU_CORE/Mshreg_biu_return_data_int_d2_2
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 0.369ns (0.118ns logic, 0.251ns route)
|
||||
(32.0% logic, 68.0% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point BIU_CORE/Mshreg_biu_register_reg_d2_11 (SLICE_X20Y29.BX), 1 path
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (hold path): 0.371ns (requirement - (clock path skew + uncertainty - data path))
|
||||
Source: BIU_CORE/biu_register_reg_11 (FF)
|
||||
Destination: BIU_CORE/Mshreg_biu_register_reg_d2_11 (FF)
|
||||
Requirement: 0.000ns
|
||||
Data Path Delay: 0.372ns (Levels of Logic = 0)
|
||||
Clock Path Skew: 0.001ns (0.042 - 0.041)
|
||||
Source Clock: core_clk_int rising at 0.000ns
|
||||
Destination Clock: core_clk_int rising at 0.000ns
|
||||
Clock Uncertainty: 0.000ns
|
||||
|
||||
Minimum Data Path at Fast Process Corner: BIU_CORE/biu_register_reg_11 to BIU_CORE/Mshreg_biu_register_reg_d2_11
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
SLICE_X20Y30.DQ Tcko 0.234 BIU_CORE/biu_register_reg<11>
|
||||
BIU_CORE/biu_register_reg_11
|
||||
SLICE_X20Y29.BX net (fanout=1) 0.218 BIU_CORE/biu_register_reg<11>
|
||||
SLICE_X20Y29.CLK Tdh (-Th) 0.080 BIU_CORE/biu_register_reg_d2<12>
|
||||
BIU_CORE/Mshreg_biu_register_reg_d2_11
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 0.372ns (0.154ns logic, 0.218ns route)
|
||||
(41.4% logic, 58.6% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Paths for end point BIU_CORE/Mshreg_biu_register_rm_d2_7 (SLICE_X0Y20.BI), 1 path
|
||||
--------------------------------------------------------------------------------
|
||||
Slack (hold path): 0.372ns (requirement - (clock path skew + uncertainty - data path))
|
||||
Source: BIU_CORE/biu_register_rm_7 (FF)
|
||||
Destination: BIU_CORE/Mshreg_biu_register_rm_d2_7 (FF)
|
||||
Requirement: 0.000ns
|
||||
Data Path Delay: 0.376ns (Levels of Logic = 0)
|
||||
Clock Path Skew: 0.004ns (0.038 - 0.034)
|
||||
Source Clock: core_clk_int rising at 0.000ns
|
||||
Destination Clock: core_clk_int rising at 0.000ns
|
||||
Clock Uncertainty: 0.000ns
|
||||
|
||||
Minimum Data Path at Fast Process Corner: BIU_CORE/biu_register_rm_7 to BIU_CORE/Mshreg_biu_register_rm_d2_7
|
||||
Location Delay type Delay(ns) Physical Resource
|
||||
Logical Resource(s)
|
||||
------------------------------------------------- -------------------
|
||||
SLICE_X0Y21.DQ Tcko 0.234 BIU_CORE/biu_register_rm<7>
|
||||
BIU_CORE/biu_register_rm_7
|
||||
SLICE_X0Y20.BI net (fanout=1) 0.113 BIU_CORE/biu_register_rm<7>
|
||||
SLICE_X0Y20.CLK Tdh (-Th) -0.029 BIU_CORE/biu_register_rm_d2<4>
|
||||
BIU_CORE/Mshreg_biu_register_rm_d2_7
|
||||
------------------------------------------------- ---------------------------
|
||||
Total 0.376ns (0.263ns logic, 0.113ns route)
|
||||
(69.9% logic, 30.1% route)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Component Switching Limit Checks: TS_SPARTAN6PLL_clkfx = PERIOD TIMEGRP "SPARTAN6PLL_clkfx" TS_CORE_CLK / 2.2
|
||||
HIGH 50%;
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 5.966ns (period - min period limit)
|
||||
Period: 9.090ns
|
||||
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
|
||||
Physical resource: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA
|
||||
Logical resource: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA
|
||||
Location pin: RAMB16_X1Y14.CLKA
|
||||
Clock network: core_clk_int
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 5.966ns (period - min period limit)
|
||||
Period: 9.090ns
|
||||
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
|
||||
Physical resource: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA
|
||||
Logical resource: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA
|
||||
Location pin: RAMB16_X1Y10.CLKA
|
||||
Clock network: core_clk_int
|
||||
--------------------------------------------------------------------------------
|
||||
Slack: 5.966ns (period - min period limit)
|
||||
Period: 9.090ns
|
||||
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
|
||||
Physical resource: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA
|
||||
Logical resource: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA
|
||||
Location pin: RAMB16_X0Y12.CLKA
|
||||
Clock network: core_clk_int
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Derived Constraint Report
|
||||
Derived Constraints for TS_CORE_CLK
|
||||
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
||||
| | Period | Actual Period | Timing Errors | Paths Analyzed |
|
||||
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|
||||
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
|
||||
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
||||
|TS_CORE_CLK | 20.000ns| 8.000ns| 19.340ns| 0| 0| 0| 513828|
|
||||
| TS_SPARTAN6PLL_clkfx | 9.091ns| 8.791ns| N/A| 0| 0| 513828| 0|
|
||||
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
||||
|
||||
All constraints were met.
|
||||
|
||||
|
||||
Data Sheet report:
|
||||
-----------------
|
||||
All values displayed in nanoseconds (ns)
|
||||
|
||||
Clock to Setup on destination clock CORE_CLK
|
||||
---------------+---------+---------+---------+---------+
|
||||
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
||||
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
||||
---------------+---------+---------+---------+---------+
|
||||
CORE_CLK | 8.791| | | |
|
||||
---------------+---------+---------+---------+---------+
|
||||
|
||||
|
||||
Timing summary:
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
|
||||
|
||||
Constraints cover 513828 paths, 0 nets, and 5708 connections
|
||||
|
||||
Design statistics:
|
||||
Minimum period: 8.791ns{1} (Maximum frequency: 113.753MHz)
|
||||
|
||||
|
||||
------------------------------------Footnotes-----------------------------------
|
||||
1) The minimum period statistic assumes all single cycle delays.
|
||||
|
||||
Analysis completed Wed Nov 11 19:11:41 2020
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Trace Settings:
|
||||
-------------------------
|
||||
Trace Settings
|
||||
|
||||
Peak Memory Usage: 236 MB
|
||||
|
||||
|
||||
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,178 @@
|
|||
|
||||
#Created by Constraints Editor (xc6slx9-tqg144-2) - 2016/06/18
|
||||
NET "CORE_CLK" TNM_NET = "CORE_CLK";
|
||||
TIMESPEC TS_CORE_CLK = PERIOD "CORE_CLK" 20 ns HIGH 50 %;
|
||||
|
||||
|
||||
NET "CORE_CLK" IOSTANDARD = PCI33_3;
|
||||
NET "A8" IOSTANDARD = PCI33_3;
|
||||
NET "A9" IOSTANDARD = PCI33_3;
|
||||
NET "A10" IOSTANDARD = PCI33_3;
|
||||
NET "A11" IOSTANDARD = PCI33_3;
|
||||
NET "A12" IOSTANDARD = PCI33_3;
|
||||
NET "A13" IOSTANDARD = PCI33_3;
|
||||
NET "A14" IOSTANDARD = PCI33_3;
|
||||
NET "A15" IOSTANDARD = PCI33_3;
|
||||
NET "A16" IOSTANDARD = PCI33_3;
|
||||
NET "A17" IOSTANDARD = PCI33_3;
|
||||
NET "A18" IOSTANDARD = PCI33_3;
|
||||
NET "A19" IOSTANDARD = PCI33_3;
|
||||
NET "AD0" IOSTANDARD = PCI33_3;
|
||||
NET "AD1" IOSTANDARD = PCI33_3;
|
||||
NET "AD2" IOSTANDARD = PCI33_3;
|
||||
NET "AD3" IOSTANDARD = PCI33_3;
|
||||
NET "AD4" IOSTANDARD = PCI33_3;
|
||||
NET "AD5" IOSTANDARD = PCI33_3;
|
||||
NET "AD6" IOSTANDARD = PCI33_3;
|
||||
NET "AD7" IOSTANDARD = PCI33_3;
|
||||
NET "CLK" IOSTANDARD = PCI33_3;
|
||||
NET "INTR" IOSTANDARD = PCI33_3;
|
||||
NET "NMI" IOSTANDARD = LVCMOS33;
|
||||
NET "READY" IOSTANDARD = PCI33_3;
|
||||
NET "RESET" IOSTANDARD = PCI33_3;
|
||||
NET "ALE" IOSTANDARD = PCI33_3;
|
||||
NET "INTA_n" IOSTANDARD = PCI33_3;
|
||||
NET "RD_n" IOSTANDARD = PCI33_3;
|
||||
NET "DEN" IOSTANDARD = PCI33_3;
|
||||
NET "WR_n" IOSTANDARD = PCI33_3;
|
||||
NET "DTR" IOSTANDARD = PCI33_3;
|
||||
NET "IOM" IOSTANDARD = PCI33_3;
|
||||
|
||||
NET "SRAM_A[18]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_A[17]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_A[16]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_A[15]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_A[14]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_A[13]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_A[12]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_A[11]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_A[10]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_A[9]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_A[8]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_A[7]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_A[6]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_A[5]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_A[4]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_A[3]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_A[2]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_A[1]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_A[0]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_CE_n" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_OE_n" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_WE_n" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_D[7]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_D[6]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_D[5]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_D[4]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_D[3]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_D[2]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_D[1]" IOSTANDARD = PCI33_3;
|
||||
NET "SRAM_D[0]" IOSTANDARD = PCI33_3;
|
||||
|
||||
NET "LED[7]" IOSTANDARD = PCI33_3;
|
||||
NET "LED[6]" IOSTANDARD = PCI33_3;
|
||||
NET "LED[5]" IOSTANDARD = PCI33_3;
|
||||
NET "LED[4]" IOSTANDARD = PCI33_3;
|
||||
NET "LED[3]" IOSTANDARD = PCI33_3;
|
||||
NET "LED[2]" IOSTANDARD = PCI33_3;
|
||||
NET "LED[1]" IOSTANDARD = PCI33_3;
|
||||
NET "LED[0]" IOSTANDARD = PCI33_3;
|
||||
|
||||
NET "BUF1_OE_n" IOSTANDARD = PCI33_3;
|
||||
NET "BUF2_OE_n" IOSTANDARD = PCI33_3;
|
||||
NET "BUF2_DIR" IOSTANDARD = PCI33_3;
|
||||
NET "SSO_n" IOSTANDARD = PCI33_3;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
NET "A8" LOC = P14;
|
||||
NET "A9" LOC = P11;
|
||||
NET "A10" LOC = P9;
|
||||
NET "A11" LOC = P7;
|
||||
NET "A12" LOC = P5;
|
||||
NET "A13" LOC = P1;
|
||||
NET "A14" LOC = P142;
|
||||
NET "A15" LOC = P143;
|
||||
NET "A16" LOC = P2;
|
||||
NET "A17" LOC = P6;
|
||||
NET "A18" LOC = P8;
|
||||
NET "A19" LOC = P10;
|
||||
NET "AD0" LOC = P35;
|
||||
NET "AD1" LOC = P34;
|
||||
NET "AD2" LOC = P33;
|
||||
NET "AD3" LOC = P32;
|
||||
NET "AD4" LOC = P27;
|
||||
NET "AD5" LOC = P26;
|
||||
NET "AD6" LOC = P23;
|
||||
NET "AD7" LOC = P22;
|
||||
NET "CLK" LOC = P46;
|
||||
NET "INTR" LOC = P45;
|
||||
NET "NMI" LOC = P44;
|
||||
NET "READY" LOC = P48;
|
||||
NET "RESET" LOC = P47;
|
||||
NET "ALE" LOC = P41;
|
||||
NET "INTA_n" LOC = P58;
|
||||
NET "RD_n" LOC = P50;
|
||||
NET "WR_n" LOC = P51;
|
||||
NET "IOM" LOC = P55;
|
||||
NET "DTR" LOC = P56;
|
||||
NET "DEN" LOC = P57;
|
||||
|
||||
NET "SRAM_A[18]" LOC = P99;
|
||||
NET "SRAM_A[17]" LOC = P79;
|
||||
NET "SRAM_A[16]" LOC = P78;
|
||||
NET "SRAM_A[15]" LOC = P100;
|
||||
NET "SRAM_A[14]" LOC = P75;
|
||||
NET "SRAM_A[13]" LOC = P97;
|
||||
NET "SRAM_A[12]" LOC = P74;
|
||||
NET "SRAM_A[11]" LOC = P93;
|
||||
NET "SRAM_A[10]" LOC = P88;
|
||||
NET "SRAM_A[9]" LOC = P94;
|
||||
NET "SRAM_A[8]" LOC = P95;
|
||||
NET "SRAM_A[7]" LOC = P67;
|
||||
NET "SRAM_A[6]" LOC = P66;
|
||||
NET "SRAM_A[5]" LOC = P62;
|
||||
NET "SRAM_A[4]" LOC = P61;
|
||||
NET "SRAM_A[3]" LOC = P123;
|
||||
NET "SRAM_A[2]" LOC = P124;
|
||||
NET "SRAM_A[1]" LOC = P126;
|
||||
NET "SRAM_A[0]" LOC = P132;
|
||||
|
||||
NET "SRAM_CE_n" LOC = P87;
|
||||
NET "SRAM_OE_n" LOC = P92;
|
||||
NET "SRAM_WE_n" LOC = P98;
|
||||
|
||||
NET "SRAM_D[7]" LOC = P85;
|
||||
NET "SRAM_D[6]" LOC = P83;
|
||||
NET "SRAM_D[5]" LOC = P82;
|
||||
NET "SRAM_D[4]" LOC = P81;
|
||||
NET "SRAM_D[3]" LOC = P80;
|
||||
NET "SRAM_D[2]" LOC = P117;
|
||||
NET "SRAM_D[1]" LOC = P118;
|
||||
NET "SRAM_D[0]" LOC = P119;
|
||||
|
||||
NET "LED[7]" LOC = P131;
|
||||
NET "LED[6]" LOC = P127;
|
||||
NET "LED[5]" LOC = P121;
|
||||
NET "LED[4]" LOC = P120;
|
||||
NET "LED[3]" LOC = P116;
|
||||
NET "LED[2]" LOC = P114;
|
||||
NET "LED[1]" LOC = P112;
|
||||
NET "LED[0]" LOC = P111;
|
||||
|
||||
|
||||
NET "CORE_CLK" LOC = P84;
|
||||
|
||||
|
||||
NET "BUF1_OE_n" LOC = P59;
|
||||
NET "BUF2_OE_n" LOC = P21;
|
||||
NET "BUF2_DIR" LOC = P16;
|
||||
NET "SSO_n" LOC = P12;
|
||||
|
||||
|
||||
# PlanAhead Generated IO constraints
|
||||
|
||||
NET "NMI" PULLDOWN;
|
||||
|
|
@ -0,0 +1,175 @@
|
|||
|
||||
#Created by Constraints Editor (xc6slx9-tqg144-2) - 2016/06/18
|
||||
NET "CORE_CLK" TNM_NET = "CORE_CLK";
|
||||
TIMESPEC TS_CORE_CLK = PERIOD "CORE_CLK" 20 ns HIGH 50 %;
|
||||
|
||||
# PlanAhead Generated IO constraints
|
||||
|
||||
NET "CORE_CLK" IOSTANDARD = PCI33_3;
|
||||
NET "A8" IOSTANDARD = PCI33_3;
|
||||
NET "A9" IOSTANDARD = PCI33_3;
|
||||
NET "A10" IOSTANDARD = PCI33_3;
|
||||
NET "A11" IOSTANDARD = PCI33_3 ;
|
||||
NET "A12" IOSTANDARD = PCI33_3 ;
|
||||
NET "A13" IOSTANDARD = PCI33_3 ;
|
||||
NET "A14" IOSTANDARD = PCI33_3 ;
|
||||
NET "A15" IOSTANDARD = PCI33_3 ;
|
||||
NET "A16" IOSTANDARD = PCI33_3 ;
|
||||
NET "A17" IOSTANDARD = PCI33_3 ;
|
||||
NET "A18" IOSTANDARD = PCI33_3 ;
|
||||
NET "A19" IOSTANDARD = PCI33_3 ;
|
||||
NET "AD0" IOSTANDARD = PCI33_3 ;
|
||||
NET "AD1" IOSTANDARD = PCI33_3 ;
|
||||
NET "AD2" IOSTANDARD = PCI33_3 ;
|
||||
NET "AD3" IOSTANDARD = PCI33_3 ;
|
||||
NET "AD4" IOSTANDARD = PCI33_3 ;
|
||||
NET "AD5" IOSTANDARD = PCI33_3 ;
|
||||
NET "AD6" IOSTANDARD = PCI33_3 ;
|
||||
NET "AD7" IOSTANDARD = PCI33_3 ;
|
||||
NET "CLK" IOSTANDARD = PCI33_3 ;
|
||||
NET "INTR" IOSTANDARD = PCI33_3 ;
|
||||
NET "NMI" IOSTANDARD = PCI33_3 ;
|
||||
NET "READY" IOSTANDARD = PCI33_3 ;
|
||||
NET "RESET" IOSTANDARD = PCI33_3 ;
|
||||
NET "ALE" IOSTANDARD = PCI33_3 ;
|
||||
NET "INTA_n" IOSTANDARD = PCI33_3 ;
|
||||
NET "RD_n" IOSTANDARD = PCI33_3 ;
|
||||
NET "DEN" IOSTANDARD = PCI33_3 ;
|
||||
NET "WR_n" IOSTANDARD = PCI33_3 ;
|
||||
NET "DTR" IOSTANDARD = PCI33_3 ;
|
||||
NET "IOM" IOSTANDARD = PCI33_3 ;
|
||||
|
||||
NET "SRAM_A[18]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_A[17]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_A[16]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_A[15]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_A[14]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_A[13]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_A[12]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_A[11]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_A[10]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_A[9]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_A[8]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_A[7]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_A[6]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_A[5]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_A[4]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_A[3]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_A[2]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_A[1]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_A[0]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_CE_n" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_OE_n" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_WE_n" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_D[7]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_D[6]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_D[5]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_D[4]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_D[3]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_D[2]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_D[1]" IOSTANDARD = PCI33_3 ;
|
||||
NET "SRAM_D[0]" IOSTANDARD = PCI33_3 ;
|
||||
|
||||
NET "LED[7]" IOSTANDARD = PCI33_3 ;
|
||||
NET "LED[6]" IOSTANDARD = PCI33_3 ;
|
||||
NET "LED[5]" IOSTANDARD = PCI33_3 ;
|
||||
NET "LED[4]" IOSTANDARD = PCI33_3 ;
|
||||
NET "LED[3]" IOSTANDARD = PCI33_3 ;
|
||||
NET "LED[2]" IOSTANDARD = PCI33_3 ;
|
||||
NET "LED[1]" IOSTANDARD = PCI33_3 ;
|
||||
NET "LED[0]" IOSTANDARD = PCI33_3 ;
|
||||
|
||||
NET "BUF1_OE_n" IOSTANDARD = PCI33_3 ;
|
||||
NET "BUF2_OE_n" IOSTANDARD = PCI33_3 ;
|
||||
NET "BUF2_DIR" IOSTANDARD = PCI33_3 ;
|
||||
NET "SSO_n" IOSTANDARD = PCI33_3 ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
NET "A8" LOC = P14 ;
|
||||
NET "A9" LOC = P11 ;
|
||||
NET "A10" LOC = P9 ;
|
||||
NET "A11" LOC = P7 ;
|
||||
NET "A12" LOC = P5 ;
|
||||
NET "A13" LOC = P1 ;
|
||||
NET "A14" LOC = P143 ;
|
||||
NET "A15" LOC = P144 ;
|
||||
NET "A16" LOC = P2 ;
|
||||
NET "A17" LOC = P6 ;
|
||||
NET "A18" LOC = P8 ;
|
||||
NET "A19" LOC = P10 ;
|
||||
NET "AD0" LOC = P35 ;
|
||||
NET "AD1" LOC = P34 ;
|
||||
NET "AD2" LOC = P33 ;
|
||||
NET "AD3" LOC = P32 ;
|
||||
NET "AD4" LOC = P27 ;
|
||||
NET "AD5" LOC = P26 ;
|
||||
NET "AD6" LOC = P23 ;
|
||||
NET "AD7" LOC = P22 ;
|
||||
NET "CLK" LOC = P46;
|
||||
NET "INTR" LOC = P45 ;
|
||||
NET "NMI" LOC = P44 ;
|
||||
NET "READY" LOC = P48 ;
|
||||
NET "RESET" LOC = P47 ;
|
||||
NET "ALE" LOC = P41 ;
|
||||
NET "INTA_n" LOC = P58 ;
|
||||
NET "RD_n" LOC = P50 ;
|
||||
NET "WR_n" LOC = P51 ;
|
||||
NET "IOM" LOC = P55 ;
|
||||
NET "DTR" LOC = P56 ;
|
||||
NET "DEN" LOC = P57 ;
|
||||
|
||||
NET "SRAM_A[18]" LOC = P99 ;
|
||||
NET "SRAM_A[17]" LOC = P79 ;
|
||||
NET "SRAM_A[16]" LOC = P78 ;
|
||||
NET "SRAM_A[15]" LOC = P100 ;
|
||||
NET "SRAM_A[14]" LOC = P75 ;
|
||||
NET "SRAM_A[13]" LOC = P97 ;
|
||||
NET "SRAM_A[12]" LOC = P74 ;
|
||||
NET "SRAM_A[11]" LOC = P93 ;
|
||||
NET "SRAM_A[10]" LOC = P88 ;
|
||||
NET "SRAM_A[9]" LOC = P94 ;
|
||||
NET "SRAM_A[8]" LOC = P95 ;
|
||||
NET "SRAM_A[7]" LOC = P67 ;
|
||||
NET "SRAM_A[6]" LOC = P66 ;
|
||||
NET "SRAM_A[5]" LOC = P62 ;
|
||||
NET "SRAM_A[4]" LOC = P61 ;
|
||||
NET "SRAM_A[3]" LOC = P123 ;
|
||||
NET "SRAM_A[2]" LOC = P124 ;
|
||||
NET "SRAM_A[1]" LOC = P126 ;
|
||||
NET "SRAM_A[0]" LOC = P132 ;
|
||||
|
||||
NET "SRAM_CE_n" LOC = P87 ;
|
||||
NET "SRAM_OE_n" LOC = P92 ;
|
||||
NET "SRAM_WE_n" LOC = P98 ;
|
||||
|
||||
NET "SRAM_D[7]" LOC = P85 ;
|
||||
NET "SRAM_D[6]" LOC = P83 ;
|
||||
NET "SRAM_D[5]" LOC = P82 ;
|
||||
NET "SRAM_D[4]" LOC = P81 ;
|
||||
NET "SRAM_D[3]" LOC = P80 ;
|
||||
NET "SRAM_D[2]" LOC = P117 ;
|
||||
NET "SRAM_D[1]" LOC = P118 ;
|
||||
NET "SRAM_D[0]" LOC = P119 ;
|
||||
|
||||
NET "LED[7]" LOC = P131 ;
|
||||
NET "LED[6]" LOC = P127 ;
|
||||
NET "LED[5]" LOC = P121 ;
|
||||
NET "LED[4]" LOC = P120 ;
|
||||
NET "LED[3]" LOC = P116 ;
|
||||
NET "LED[2]" LOC = P114 ;
|
||||
NET "LED[1]" LOC = P112 ;
|
||||
NET "LED[0]" LOC = P111 ;
|
||||
|
||||
|
||||
NET "CORE_CLK" LOC = P84 ;
|
||||
|
||||
|
||||
NET "BUF1_OE_n" LOC = P59 ;
|
||||
NET "BUF2_OE_n" LOC = P21 ;
|
||||
NET "BUF2_DIR" LOC = P16 ;
|
||||
NET "SSO_n" LOC = P12 ;
|
||||
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
Release 14.7 - par P.20131013 (nt64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Wed Nov 11 19:11:34 2020
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
-g INIT_9K:Yes
|
||||
-w
|
||||
-g DebugBitstream:No
|
||||
-g Binary:no
|
||||
-g CRC:Enable
|
||||
-g Reset_on_err:No
|
||||
-g ConfigRate:10
|
||||
-g ProgPin:PullUp
|
||||
-g TckPin:PullUp
|
||||
-g TdiPin:PullUp
|
||||
-g TdoPin:PullUp
|
||||
-g TmsPin:PullUp
|
||||
-g UnusedPin:PullDown
|
||||
-g UserID:0xFFFFFFFF
|
||||
-g ExtMasterCclk_en:No
|
||||
-g SPI_buswidth:1
|
||||
-g TIMER_CFG:0xFFFF
|
||||
-g multipin_wakeup:No
|
||||
-g StartUpClk:CClk
|
||||
-g DONE_cycle:4
|
||||
-g GTS_cycle:5
|
||||
-g GWE_cycle:6
|
||||
-g LCK_cycle:NoWait
|
||||
-g Security:None
|
||||
-g DonePipe:Yes
|
||||
-g DriveDone:No
|
||||
-g en_sw_gsr:No
|
||||
-g drive_awake:No
|
||||
-g sw_clk:Startupclk
|
||||
-g sw_gwe_cycle:5
|
||||
-g sw_gts_cycle:4
|
||||
|
|
@ -0,0 +1,386 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="../src4synth/biu_min.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="../src4synth/MCL86jr.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
|
||||
</file>
|
||||
<file xil_pn:name="../src4synth/eu.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/EU4Kx32.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="MCL86jr.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/spartan6_pll.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/EU4Kx32.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/spartan6_pll.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="10" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|MCL86jr" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="../src4synth/MCL86jr.v" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MCL86jr" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="-g INIT_9K:Yes" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="MCL86jr" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MCL86jr_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="MCL86jr_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MCL86jr_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MCL86jr_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="On" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="MCL86jr" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-09-12T20:32:34" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="0F0A51A7D06B470287A989EDCA362445" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
PROGRAM=PAR
|
||||
STATE=ROUTED
|
||||
TIMESPECS_MET=YES
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
set -tmpdir "xst/projnav.tmp"
|
||||
set -xsthdpdir "xst"
|
||||
run
|
||||
-ifn MCL86jr.prj
|
||||
-ofn MCL86jr
|
||||
-ofmt NGC
|
||||
-p xc6slx9-3-tqg144
|
||||
-top MCL86jr
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-power NO
|
||||
-iuc NO
|
||||
-keep_hierarchy No
|
||||
-netlist_hierarchy As_Optimized
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-sd {"ipcore_dir" }
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case Maintain
|
||||
-slice_utilization_ratio 100
|
||||
-bram_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-lc Auto
|
||||
-reduce_control_sets Auto
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style LUT
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-shreg_extract YES
|
||||
-rom_style Auto
|
||||
-auto_bram_packing NO
|
||||
-resource_sharing YES
|
||||
-async_to_sync NO
|
||||
-shreg_min_size 2
|
||||
-use_dsp48 Auto
|
||||
-iobuf YES
|
||||
-max_fanout 100000
|
||||
-bufg 16
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob Auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
INTSTYLE=ise
|
||||
INFILE=C:\MCL\MCL86\MCL86jr\MCL86jr\MCL86jr.ncd
|
||||
OUTFILE=C:\MCL\MCL86\MCL86jr\MCL86jr\MCL86jr.bit
|
||||
FAMILY=Spartan6
|
||||
PART=xc6slx9-3tqg144
|
||||
WORKINGDIR=C:\MCL\MCL86\MCL86jr\MCL86jr
|
||||
LICENSE=WebPack
|
||||
USER_INFO=174191283_174191284_0_212
|
||||
|
|
@ -0,0 +1,568 @@
|
|||
<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<center><big><big><b>System Settings</b></big></big></center><br>
|
||||
<A NAME="Environment Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Environment Variable</b></td>
|
||||
<td><b>xst</b></td>
|
||||
<td><b>ngdbuild</b></td>
|
||||
<td><b>map</b></td>
|
||||
<td><b>par</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>PATHEXT</td>
|
||||
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
|
||||
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
|
||||
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
|
||||
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Path</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ProgramData\Oracle\Java\javapath;<br>C:\Program Files (x86)\SemanticDesigns\DMS\Executables;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Intel\WiFi\bin\;<br>C:\Program Files\Common Files\Intel\WirelessCommon\;<br>C:\altera_lite\15.1\modelsim_ase\win32aloem;<br>C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ProgramData\Oracle\Java\javapath;<br>C:\Program Files (x86)\SemanticDesigns\DMS\Executables;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Intel\WiFi\bin\;<br>C:\Program Files\Common Files\Intel\WirelessCommon\;<br>C:\altera_lite\15.1\modelsim_ase\win32aloem;<br>C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ProgramData\Oracle\Java\javapath;<br>C:\Program Files (x86)\SemanticDesigns\DMS\Executables;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Intel\WiFi\bin\;<br>C:\Program Files\Common Files\Intel\WirelessCommon\;<br>C:\altera_lite\15.1\modelsim_ase\win32aloem;<br>C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ProgramData\Oracle\Java\javapath;<br>C:\Program Files (x86)\SemanticDesigns\DMS\Executables;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Intel\WiFi\bin\;<br>C:\Program Files\Common Files\Intel\WirelessCommon\;<br>C:\altera_lite\15.1\modelsim_ase\win32aloem;<br>C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX_DSP</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX_EDK</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX_PLANAHEAD</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Synthesis Property Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Switch Name</b></td>
|
||||
<td><b>Property Name</b></td>
|
||||
<td><b>Value</b></td>
|
||||
<td><b>Default Value</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ifn</td>
|
||||
<td> </td>
|
||||
<td>MCL86jr.prj</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ofn</td>
|
||||
<td> </td>
|
||||
<td>MCL86jr</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ofmt</td>
|
||||
<td> </td>
|
||||
<td>NGC</td>
|
||||
<td>NGC</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-p</td>
|
||||
<td> </td>
|
||||
<td>xc6slx9-3-tqg144</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-top</td>
|
||||
<td> </td>
|
||||
<td>MCL86jr</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-opt_mode</td>
|
||||
<td>Optimization Goal</td>
|
||||
<td>Speed</td>
|
||||
<td>Speed</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-opt_level</td>
|
||||
<td>Optimization Effort</td>
|
||||
<td>1</td>
|
||||
<td>1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-power</td>
|
||||
<td>Power Reduction</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-iuc</td>
|
||||
<td>Use synthesis Constraints File</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-keep_hierarchy</td>
|
||||
<td>Keep Hierarchy</td>
|
||||
<td>No</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-netlist_hierarchy</td>
|
||||
<td>Netlist Hierarchy</td>
|
||||
<td>As_Optimized</td>
|
||||
<td>As_Optimized</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-rtlview</td>
|
||||
<td>Generate RTL Schematic</td>
|
||||
<td>Yes</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-glob_opt</td>
|
||||
<td>Global Optimization Goal</td>
|
||||
<td>AllClockNets</td>
|
||||
<td>AllClockNets</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-read_cores</td>
|
||||
<td>Read Cores</td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-sd</td>
|
||||
<td>Cores Search Directories</td>
|
||||
<td>{"ipcore_dir" }</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-write_timing_constraints</td>
|
||||
<td>Write Timing Constraints</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-cross_clock_analysis</td>
|
||||
<td>Cross Clock Analysis</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-bus_delimiter</td>
|
||||
<td>Bus Delimiter</td>
|
||||
<td><></td>
|
||||
<td><></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-slice_utilization_ratio</td>
|
||||
<td>Slice Utilization Ratio</td>
|
||||
<td>100</td>
|
||||
<td>100</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-bram_utilization_ratio</td>
|
||||
<td>BRAM Utilization Ratio</td>
|
||||
<td>100</td>
|
||||
<td>100</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-dsp_utilization_ratio</td>
|
||||
<td>DSP Utilization Ratio</td>
|
||||
<td>100</td>
|
||||
<td>100</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-reduce_control_sets</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-fsm_extract</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-fsm_encoding</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-safe_implementation</td>
|
||||
<td> </td>
|
||||
<td>No</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-fsm_style</td>
|
||||
<td> </td>
|
||||
<td>LUT</td>
|
||||
<td>LUT</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ram_extract</td>
|
||||
<td> </td>
|
||||
<td>Yes</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ram_style</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-rom_extract</td>
|
||||
<td> </td>
|
||||
<td>Yes</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-shreg_extract</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-rom_style</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-auto_bram_packing</td>
|
||||
<td> </td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-resource_sharing</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-async_to_sync</td>
|
||||
<td> </td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-use_dsp48</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-iobuf</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-max_fanout</td>
|
||||
<td> </td>
|
||||
<td>100000</td>
|
||||
<td>100000</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-bufg</td>
|
||||
<td> </td>
|
||||
<td>16</td>
|
||||
<td>16</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-register_duplication</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-register_balancing</td>
|
||||
<td> </td>
|
||||
<td>No</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-optimize_primitives</td>
|
||||
<td> </td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-use_clock_enable</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-use_sync_set</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-use_sync_reset</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-iob</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-equivalent_register_removal</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-slice_utilization_ratio_maxmargin</td>
|
||||
<td> </td>
|
||||
<td>5</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Translation Property Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Switch Name</b></td>
|
||||
<td><b>Property Name</b></td>
|
||||
<td><b>Value</b></td>
|
||||
<td><b>Default Value</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-intstyle</td>
|
||||
<td> </td>
|
||||
<td>ise</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-dd</td>
|
||||
<td> </td>
|
||||
<td>_ngo</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-p</td>
|
||||
<td> </td>
|
||||
<td>xc6slx9-tqg144-3</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-sd</td>
|
||||
<td>Macro Search Path</td>
|
||||
<td>ipcore_dir</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-uc</td>
|
||||
<td> </td>
|
||||
<td>MCL86jr.ucf</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Map Property Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Switch Name</b></td>
|
||||
<td><b>Property Name</b></td>
|
||||
<td><b>Value</b></td>
|
||||
<td><b>Default Value</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ol</td>
|
||||
<td>Place & Route Effort Level (Overall)</td>
|
||||
<td>high</td>
|
||||
<td>high</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-xe</td>
|
||||
<td>Placer Extra Effort Map</td>
|
||||
<td>NORMAL</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-xt</td>
|
||||
<td>Extra Cost Tables</td>
|
||||
<td>0</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ir</td>
|
||||
<td>Use RLOC Constraints</td>
|
||||
<td>OFF</td>
|
||||
<td>OFF</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-t</td>
|
||||
<td>Starting Placer Cost Table (1-100) Map</td>
|
||||
<td>2</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-r</td>
|
||||
<td>Register Ordering</td>
|
||||
<td>4</td>
|
||||
<td>4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-register_duplication</td>
|
||||
<td>Register Duplication Map</td>
|
||||
<td>TRUE</td>
|
||||
<td>FALSE</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-intstyle</td>
|
||||
<td> </td>
|
||||
<td>ise</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-lc</td>
|
||||
<td>LUT Combining</td>
|
||||
<td>off</td>
|
||||
<td>off</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-o</td>
|
||||
<td> </td>
|
||||
<td>MCL86jr_map.ncd</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-w</td>
|
||||
<td> </td>
|
||||
<td>true</td>
|
||||
<td>false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-pr</td>
|
||||
<td>Pack I/O Registers/Latches into IOBs</td>
|
||||
<td>b</td>
|
||||
<td>off</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-p</td>
|
||||
<td> </td>
|
||||
<td>xc6slx9-tqg144-3</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Place and Route Property Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Switch Name</b></td>
|
||||
<td><b>Property Name</b></td>
|
||||
<td><b>Value</b></td>
|
||||
<td><b>Default Value</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-xe</td>
|
||||
<td> </td>
|
||||
<td>n</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-intstyle</td>
|
||||
<td> </td>
|
||||
<td>ise</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-mt</td>
|
||||
<td>Enable Multi-Threading</td>
|
||||
<td>off</td>
|
||||
<td>off</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ol</td>
|
||||
<td>Place & Route Effort Level (Overall)</td>
|
||||
<td>high</td>
|
||||
<td>std</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-w</td>
|
||||
<td> </td>
|
||||
<td>true</td>
|
||||
<td>false</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Operating System Information"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Operating System Information</b></td>
|
||||
<td><b>xst</b></td>
|
||||
<td><b>ngdbuild</b></td>
|
||||
<td><b>map</b></td>
|
||||
<td><b>par</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>CPU Architecture/Speed</td>
|
||||
<td>Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz/2492 MHz</td>
|
||||
<td>Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz/2492 MHz</td>
|
||||
<td>Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz/2492 MHz</td>
|
||||
<td>Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz/2492 MHz</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Host</td>
|
||||
<td>MicroCoreLabs</td>
|
||||
<td>MicroCoreLabs</td>
|
||||
<td>MicroCoreLabs</td>
|
||||
<td>MicroCoreLabs</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>OS Name</td>
|
||||
<td>Microsoft Windows 7 , 64-bit</td>
|
||||
<td>Microsoft Windows 7 , 64-bit</td>
|
||||
<td>Microsoft Windows 7 , 64-bit</td>
|
||||
<td>Microsoft Windows 7 , 64-bit</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>OS Release</td>
|
||||
<td>Service Pack 1 (build 7601)</td>
|
||||
<td>Service Pack 1 (build 7601)</td>
|
||||
<td>Service Pack 1 (build 7601)</td>
|
||||
<td>Service Pack 1 (build 7601)</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
</BODY> </HTML>
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,178 @@
|
|||
Release 14.7 Map P.20131013 (nt64)
|
||||
Xilinx Map Application Log File for Design 'MCL86jr'
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
Command Line : map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol
|
||||
high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir
|
||||
off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
Target Device : xc6slx9
|
||||
Target Package : tqg144
|
||||
Target Speed : -3
|
||||
Mapper Version : spartan6 -- $Revision: 1.55 $
|
||||
Mapped Date : Wed Nov 11 19:10:23 2020
|
||||
|
||||
Mapping design into LUTs...
|
||||
Running directed packing...
|
||||
Running delay-based LUT packing...
|
||||
Updating timing models...
|
||||
WARNING:Timing:3402 - The Clock Modifying COMP, SPARTAN6PLL/dcm_sp_inst, has the attribute CLK_FEEDBACK set to NONE. No phase relationship
|
||||
exists between the input and output clocks of this Clock Modifying COMP. Data paths between these clock domains must be constrained using
|
||||
FROM/TO constraints.
|
||||
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
|
||||
(.mrp).
|
||||
Running timing-driven placement...
|
||||
Total REAL time at the beginning of Placer: 6 secs
|
||||
Total CPU time at the beginning of Placer: 5 secs
|
||||
|
||||
Phase 1.1 Initial Placement Analysis
|
||||
Phase 1.1 Initial Placement Analysis (Checksum:7c03570a) REAL time: 6 secs
|
||||
|
||||
Phase 2.7 Design Feasibility Check
|
||||
Phase 2.7 Design Feasibility Check (Checksum:7c03570a) REAL time: 7 secs
|
||||
|
||||
Phase 3.31 Local Placement Optimization
|
||||
Phase 3.31 Local Placement Optimization (Checksum:7c03570a) REAL time: 7 secs
|
||||
|
||||
Phase 4.2 Initial Placement for Architecture Specific Features
|
||||
|
||||
Phase 4.2 Initial Placement for Architecture Specific Features
|
||||
(Checksum:1a11c56) REAL time: 9 secs
|
||||
|
||||
Phase 5.36 Local Placement Optimization
|
||||
Phase 5.36 Local Placement Optimization (Checksum:1a11c56) REAL time: 9 secs
|
||||
|
||||
Phase 6.30 Global Clock Region Assignment
|
||||
Phase 6.30 Global Clock Region Assignment (Checksum:1a11c56) REAL time: 9 secs
|
||||
|
||||
Phase 7.3 Local Placement Optimization
|
||||
Phase 7.3 Local Placement Optimization (Checksum:1a11c56) REAL time: 9 secs
|
||||
|
||||
Phase 8.5 Local Placement Optimization
|
||||
Phase 8.5 Local Placement Optimization (Checksum:1a11c56) REAL time: 9 secs
|
||||
|
||||
Phase 9.8 Global Placement
|
||||
............................
|
||||
......................
|
||||
......................................................................................
|
||||
...........................................................................................................................................................................................
|
||||
.................................
|
||||
Phase 9.8 Global Placement (Checksum:eb9fb3e1) REAL time: 17 secs
|
||||
|
||||
Phase 10.5 Local Placement Optimization
|
||||
Phase 10.5 Local Placement Optimization (Checksum:eb9fb3e1) REAL time: 17 secs
|
||||
|
||||
Phase 11.18 Placement Optimization
|
||||
Phase 11.18 Placement Optimization (Checksum:7cbfab27) REAL time: 28 secs
|
||||
|
||||
Phase 12.5 Local Placement Optimization
|
||||
Phase 12.5 Local Placement Optimization (Checksum:7cbfab27) REAL time: 28 secs
|
||||
|
||||
Phase 13.34 Placement Validation
|
||||
Phase 13.34 Placement Validation (Checksum:20017819) REAL time: 28 secs
|
||||
|
||||
Total REAL time to Placer completion: 28 secs
|
||||
Total CPU time to Placer completion: 28 secs
|
||||
Running physical synthesis...
|
||||
|
||||
Physical synthesis completed.
|
||||
Running post-placement packing...
|
||||
Writing output files...
|
||||
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
|
||||
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
|
||||
default, may be incorrect and should not be used. For more information,
|
||||
please reference Xilinx Answer Record 39999.
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Design Summary:
|
||||
Number of errors: 0
|
||||
Number of warnings: 2
|
||||
Slice Logic Utilization:
|
||||
Number of Slice Registers: 853 out of 11,440 7%
|
||||
Number used as Flip Flops: 853
|
||||
Number used as Latches: 0
|
||||
Number used as Latch-thrus: 0
|
||||
Number used as AND/OR logics: 0
|
||||
Number of Slice LUTs: 959 out of 5,720 16%
|
||||
Number used as logic: 887 out of 5,720 15%
|
||||
Number using O6 output only: 681
|
||||
Number using O5 output only: 54
|
||||
Number using O5 and O6: 152
|
||||
Number used as ROM: 0
|
||||
Number used as Memory: 58 out of 1,440 4%
|
||||
Number used as Dual Port RAM: 0
|
||||
Number used as Single Port RAM: 0
|
||||
Number used as Shift Register: 58
|
||||
Number using O6 output only: 2
|
||||
Number using O5 output only: 0
|
||||
Number using O5 and O6: 56
|
||||
Number used exclusively as route-thrus: 14
|
||||
Number with same-slice register load: 8
|
||||
Number with same-slice carry load: 6
|
||||
Number with other load: 0
|
||||
|
||||
Slice Logic Distribution:
|
||||
Number of occupied Slices: 381 out of 1,430 26%
|
||||
Number of MUXCYs used: 196 out of 2,860 6%
|
||||
Number of LUT Flip Flop pairs used: 1,197
|
||||
Number with an unused Flip Flop: 437 out of 1,197 36%
|
||||
Number with an unused LUT: 238 out of 1,197 19%
|
||||
Number of fully used LUT-FF pairs: 522 out of 1,197 43%
|
||||
Number of unique control sets: 40
|
||||
Number of slice register sites lost
|
||||
to control set restrictions: 41 out of 11,440 1%
|
||||
|
||||
A LUT Flip Flop pair for this architecture represents one LUT paired with
|
||||
one Flip Flop within a slice. A control set is a unique combination of
|
||||
clock, reset, set, and enable signals for a registered element.
|
||||
The Slice Logic Distribution report is not meaningful if the design is
|
||||
over-mapped for a non-slice resource or if Placement fails.
|
||||
|
||||
IO Utilization:
|
||||
Number of bonded IOBs: 75 out of 102 73%
|
||||
Number of LOCed IOBs: 75 out of 75 100%
|
||||
IOB Flip Flops: 39
|
||||
|
||||
Specific Feature Utilization:
|
||||
Number of RAMB16BWERs: 7 out of 32 21%
|
||||
Number of RAMB8BWERs: 1 out of 64 1%
|
||||
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
|
||||
Number used as BUFIO2s: 1
|
||||
Number used as BUFIO2_2CLKs: 0
|
||||
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
|
||||
Number of BUFG/BUFGMUXs: 1 out of 16 6%
|
||||
Number used as BUFGs: 1
|
||||
Number used as BUFGMUX: 0
|
||||
Number of DCM/DCM_CLKGENs: 1 out of 4 25%
|
||||
Number used as DCMs: 1
|
||||
Number used as DCM_CLKGENs: 0
|
||||
Number of ILOGIC2/ISERDES2s: 12 out of 200 6%
|
||||
Number used as ILOGIC2s: 12
|
||||
Number used as ISERDES2s: 0
|
||||
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
|
||||
Number of OLOGIC2/OSERDES2s: 27 out of 200 13%
|
||||
Number used as OLOGIC2s: 27
|
||||
Number used as OSERDES2s: 0
|
||||
Number of BSCANs: 0 out of 4 0%
|
||||
Number of BUFHs: 0 out of 128 0%
|
||||
Number of BUFPLLs: 0 out of 8 0%
|
||||
Number of BUFPLL_MCBs: 0 out of 4 0%
|
||||
Number of DSP48A1s: 0 out of 16 0%
|
||||
Number of ICAPs: 0 out of 1 0%
|
||||
Number of MCBs: 0 out of 2 0%
|
||||
Number of PCILOGICSEs: 0 out of 2 0%
|
||||
Number of PLL_ADVs: 0 out of 2 0%
|
||||
Number of PMVs: 0 out of 1 0%
|
||||
Number of STARTUPs: 0 out of 1 0%
|
||||
Number of SUSPEND_SYNCs: 0 out of 1 0%
|
||||
|
||||
Average Fanout of Non-Clock Nets: 4.04
|
||||
|
||||
Peak Memory Usage: 441 MB
|
||||
Total REAL time to MAP completion: 33 secs
|
||||
Total CPU time to MAP completion: 32 secs
|
||||
|
||||
Mapping completed.
|
||||
See MAP report file "MCL86jr_map.mrp" for details.
|
||||
|
|
@ -0,0 +1,329 @@
|
|||
Release 14.7 Map P.20131013 (nt64)
|
||||
Xilinx Mapping Report File for Design 'MCL86jr'
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
Command Line : map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol
|
||||
high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir
|
||||
off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf
|
||||
Target Device : xc6slx9
|
||||
Target Package : tqg144
|
||||
Target Speed : -3
|
||||
Mapper Version : spartan6 -- $Revision: 1.55 $
|
||||
Mapped Date : Wed Nov 11 19:10:23 2020
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
Number of errors: 0
|
||||
Number of warnings: 2
|
||||
Slice Logic Utilization:
|
||||
Number of Slice Registers: 853 out of 11,440 7%
|
||||
Number used as Flip Flops: 853
|
||||
Number used as Latches: 0
|
||||
Number used as Latch-thrus: 0
|
||||
Number used as AND/OR logics: 0
|
||||
Number of Slice LUTs: 959 out of 5,720 16%
|
||||
Number used as logic: 887 out of 5,720 15%
|
||||
Number using O6 output only: 681
|
||||
Number using O5 output only: 54
|
||||
Number using O5 and O6: 152
|
||||
Number used as ROM: 0
|
||||
Number used as Memory: 58 out of 1,440 4%
|
||||
Number used as Dual Port RAM: 0
|
||||
Number used as Single Port RAM: 0
|
||||
Number used as Shift Register: 58
|
||||
Number using O6 output only: 2
|
||||
Number using O5 output only: 0
|
||||
Number using O5 and O6: 56
|
||||
Number used exclusively as route-thrus: 14
|
||||
Number with same-slice register load: 8
|
||||
Number with same-slice carry load: 6
|
||||
Number with other load: 0
|
||||
|
||||
Slice Logic Distribution:
|
||||
Number of occupied Slices: 381 out of 1,430 26%
|
||||
Number of MUXCYs used: 196 out of 2,860 6%
|
||||
Number of LUT Flip Flop pairs used: 1,197
|
||||
Number with an unused Flip Flop: 437 out of 1,197 36%
|
||||
Number with an unused LUT: 238 out of 1,197 19%
|
||||
Number of fully used LUT-FF pairs: 522 out of 1,197 43%
|
||||
Number of unique control sets: 40
|
||||
Number of slice register sites lost
|
||||
to control set restrictions: 41 out of 11,440 1%
|
||||
|
||||
A LUT Flip Flop pair for this architecture represents one LUT paired with
|
||||
one Flip Flop within a slice. A control set is a unique combination of
|
||||
clock, reset, set, and enable signals for a registered element.
|
||||
The Slice Logic Distribution report is not meaningful if the design is
|
||||
over-mapped for a non-slice resource or if Placement fails.
|
||||
|
||||
IO Utilization:
|
||||
Number of bonded IOBs: 75 out of 102 73%
|
||||
Number of LOCed IOBs: 75 out of 75 100%
|
||||
IOB Flip Flops: 39
|
||||
|
||||
Specific Feature Utilization:
|
||||
Number of RAMB16BWERs: 7 out of 32 21%
|
||||
Number of RAMB8BWERs: 1 out of 64 1%
|
||||
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
|
||||
Number used as BUFIO2s: 1
|
||||
Number used as BUFIO2_2CLKs: 0
|
||||
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
|
||||
Number of BUFG/BUFGMUXs: 1 out of 16 6%
|
||||
Number used as BUFGs: 1
|
||||
Number used as BUFGMUX: 0
|
||||
Number of DCM/DCM_CLKGENs: 1 out of 4 25%
|
||||
Number used as DCMs: 1
|
||||
Number used as DCM_CLKGENs: 0
|
||||
Number of ILOGIC2/ISERDES2s: 12 out of 200 6%
|
||||
Number used as ILOGIC2s: 12
|
||||
Number used as ISERDES2s: 0
|
||||
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
|
||||
Number of OLOGIC2/OSERDES2s: 27 out of 200 13%
|
||||
Number used as OLOGIC2s: 27
|
||||
Number used as OSERDES2s: 0
|
||||
Number of BSCANs: 0 out of 4 0%
|
||||
Number of BUFHs: 0 out of 128 0%
|
||||
Number of BUFPLLs: 0 out of 8 0%
|
||||
Number of BUFPLL_MCBs: 0 out of 4 0%
|
||||
Number of DSP48A1s: 0 out of 16 0%
|
||||
Number of ICAPs: 0 out of 1 0%
|
||||
Number of MCBs: 0 out of 2 0%
|
||||
Number of PCILOGICSEs: 0 out of 2 0%
|
||||
Number of PLL_ADVs: 0 out of 2 0%
|
||||
Number of PMVs: 0 out of 1 0%
|
||||
Number of STARTUPs: 0 out of 1 0%
|
||||
Number of SUSPEND_SYNCs: 0 out of 1 0%
|
||||
|
||||
Average Fanout of Non-Clock Nets: 4.04
|
||||
|
||||
Peak Memory Usage: 441 MB
|
||||
Total REAL time to MAP completion: 33 secs
|
||||
Total CPU time to MAP completion: 32 secs
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
Section 1 - Errors
|
||||
Section 2 - Warnings
|
||||
Section 3 - Informational
|
||||
Section 4 - Removed Logic Summary
|
||||
Section 5 - Removed Logic
|
||||
Section 6 - IOB Properties
|
||||
Section 7 - RPMs
|
||||
Section 8 - Guide Report
|
||||
Section 9 - Area Group and Partition Summary
|
||||
Section 10 - Timing Report
|
||||
Section 11 - Configuration String Information
|
||||
Section 12 - Control Set Information
|
||||
Section 13 - Utilization by Hierarchy
|
||||
|
||||
Section 1 - Errors
|
||||
------------------
|
||||
|
||||
Section 2 - Warnings
|
||||
--------------------
|
||||
WARNING:Timing:3402 - The Clock Modifying COMP, SPARTAN6PLL/dcm_sp_inst, has the attribute CLK_FEEDBACK set to NONE. No phase relationship
|
||||
exists between the input and output clocks of this Clock Modifying COMP. Data paths between these clock domains must be constrained using
|
||||
FROM/TO constraints.
|
||||
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
|
||||
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
|
||||
default, may be incorrect and should not be used. For more information,
|
||||
please reference Xilinx Answer Record 39999.
|
||||
|
||||
Section 3 - Informational
|
||||
-------------------------
|
||||
INFO:LIT:243 - Logical network EU_CORE/EU4Kx32_i/douta<31> has no load.
|
||||
INFO:MapLib:562 - No environment variables are currently set.
|
||||
INFO:LIT:244 - All of the single ended outputs in this design are using slew
|
||||
rate limited output drivers. The delay on speed critical single ended outputs
|
||||
can be dramatically reduced by designating them as fast outputs.
|
||||
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
|
||||
0.000 to 85.000 Celsius)
|
||||
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
|
||||
1.260 Volts)
|
||||
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
|
||||
(.mrp).
|
||||
INFO:Pack:1650 - Map created a placed design.
|
||||
INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance
|
||||
with the CLKFX and CLKFX180 outputs of the DCM comp SPARTAN6PLL/dcm_sp_inst,
|
||||
consult the device Data Sheet.
|
||||
|
||||
Section 4 - Removed Logic Summary
|
||||
---------------------------------
|
||||
1 block(s) removed
|
||||
4 block(s) optimized away
|
||||
3 signal(s) removed
|
||||
|
||||
Section 5 - Removed Logic
|
||||
-------------------------
|
||||
|
||||
The trimmed logic report below shows the logic removed from your design due to
|
||||
sourceless or loadless signals, and VCC or ground connections. If the removal
|
||||
of a signal or symbol results in the subsequent removal of an additional signal
|
||||
or symbol, the message explaining that second removal will be indented. This
|
||||
indentation will be repeated as a chain of related logic is removed.
|
||||
|
||||
To quickly locate the original cause for the removal of a chain of logic, look
|
||||
above the place where that logic is listed in the trimming report, then locate
|
||||
the lines that are least indented (begin at the leftmost edge).
|
||||
|
||||
The signal "EU_CORE/EU4Kx32_i/douta<31>" is sourceless and has been removed.
|
||||
The signal
|
||||
"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.
|
||||
cstr/ramloop[7].ram.ram_douta<8>" is sourceless and has been removed.
|
||||
Sourceless block
|
||||
"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.
|
||||
cstr/has_mux_a.A/Mmux_dout_mux251" (ROM) removed.
|
||||
The signal
|
||||
"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.
|
||||
cstr/ramloop[6].ram.ram_douta<8>" is sourceless and has been removed.
|
||||
|
||||
Optimized Block(s):
|
||||
TYPE BLOCK
|
||||
GND EU_CORE/EU4Kx32_i/XST_GND
|
||||
VCC EU_CORE/EU4Kx32_i/XST_VCC
|
||||
GND XST_GND
|
||||
VCC XST_VCC
|
||||
|
||||
To enable printing of redundant blocks removed and signals merged, set the
|
||||
detailed map report option and rerun map.
|
||||
|
||||
Section 6 - IOB Properties
|
||||
--------------------------
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
|
||||
| | | | | Term | Strength | Rate | | | Delay |
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
| A8 | IOB | OUTPUT | PCI33_3 | | | | OFF | | |
|
||||
| A9 | IOB | OUTPUT | PCI33_3 | | | | OFF | | |
|
||||
| A10 | IOB | OUTPUT | PCI33_3 | | | | OFF | | |
|
||||
| A11 | IOB | OUTPUT | PCI33_3 | | | | OFF | | |
|
||||
| A12 | IOB | OUTPUT | PCI33_3 | | | | OFF | | |
|
||||
| A13 | IOB | OUTPUT | PCI33_3 | | | | OFF | | |
|
||||
| A14 | IOB | OUTPUT | PCI33_3 | | | | OFF | | |
|
||||
| A15 | IOB | OUTPUT | PCI33_3 | | | | OFF | | |
|
||||
| A16 | IOB | OUTPUT | PCI33_3 | | | | OFF | | |
|
||||
| A17 | IOB | OUTPUT | PCI33_3 | | | | OFF | | |
|
||||
| A18 | IOB | OUTPUT | PCI33_3 | | | | OFF | | |
|
||||
| A19 | IOB | OUTPUT | PCI33_3 | | | | OFF | | |
|
||||
| AD0 | IOB | BIDIR | PCI33_3 | | | | IFF | | |
|
||||
| | | | | | | | OFF | | |
|
||||
| AD1 | IOB | BIDIR | PCI33_3 | | | | IFF | | |
|
||||
| | | | | | | | OFF | | |
|
||||
| AD2 | IOB | BIDIR | PCI33_3 | | | | IFF | | |
|
||||
| | | | | | | | OFF | | |
|
||||
| AD3 | IOB | BIDIR | PCI33_3 | | | | IFF | | |
|
||||
| | | | | | | | OFF | | |
|
||||
| AD4 | IOB | BIDIR | PCI33_3 | | | | IFF | | |
|
||||
| | | | | | | | OFF | | |
|
||||
| AD5 | IOB | BIDIR | PCI33_3 | | | | IFF | | |
|
||||
| | | | | | | | OFF | | |
|
||||
| AD6 | IOB | BIDIR | PCI33_3 | | | | IFF | | |
|
||||
| | | | | | | | OFF | | |
|
||||
| AD7 | IOB | BIDIR | PCI33_3 | | | | IFF | | |
|
||||
| | | | | | | | OFF | | |
|
||||
| ALE | IOB | OUTPUT | PCI33_3 | | | | OFF | | |
|
||||
| BUF1_OE_n | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| BUF2_DIR | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| BUF2_OE_n | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| CLK | IOB | INPUT | PCI33_3 | | | | IFF | | |
|
||||
| CORE_CLK | IOB | INPUT | PCI33_3 | | | | | | |
|
||||
| DEN | IOB | OUTPUT | PCI33_3 | | | | OFF | | |
|
||||
| DTR | IOB | OUTPUT | PCI33_3 | | | | OFF | | |
|
||||
| INTA_n | IOB | OUTPUT | PCI33_3 | | | | OFF | | |
|
||||
| INTR | IOB | INPUT | PCI33_3 | | | | IFF | | |
|
||||
| IOM | IOB | OUTPUT | PCI33_3 | | | | OFF | | |
|
||||
| LED<0> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| LED<1> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| LED<2> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| LED<3> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| LED<4> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| LED<5> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| LED<6> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| LED<7> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| NMI | IOB | INPUT | LVCMOS33 | | | | IFF | PULLDOWN | |
|
||||
| RD_n | IOB | OUTPUT | PCI33_3 | | | | OFF | | |
|
||||
| READY | IOB | INPUT | PCI33_3 | | | | IFF | | |
|
||||
| RESET | IOB | INPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_A<0> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_A<1> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_A<2> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_A<3> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_A<4> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_A<5> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_A<6> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_A<7> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_A<8> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_A<9> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_A<10> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_A<11> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_A<12> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_A<13> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_A<14> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_A<15> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_A<16> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_A<17> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_A<18> | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_CE_n | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_D<0> | IOB | BIDIR | PCI33_3 | | | | | | |
|
||||
| SRAM_D<1> | IOB | BIDIR | PCI33_3 | | | | | | |
|
||||
| SRAM_D<2> | IOB | BIDIR | PCI33_3 | | | | | | |
|
||||
| SRAM_D<3> | IOB | BIDIR | PCI33_3 | | | | | | |
|
||||
| SRAM_D<4> | IOB | BIDIR | PCI33_3 | | | | | | |
|
||||
| SRAM_D<5> | IOB | BIDIR | PCI33_3 | | | | | | |
|
||||
| SRAM_D<6> | IOB | BIDIR | PCI33_3 | | | | | | |
|
||||
| SRAM_D<7> | IOB | BIDIR | PCI33_3 | | | | | | |
|
||||
| SRAM_OE_n | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SRAM_WE_n | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| SSO_n | IOB | OUTPUT | PCI33_3 | | | | | | |
|
||||
| WR_n | IOB | OUTPUT | PCI33_3 | | | | OFF | | |
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
Section 7 - RPMs
|
||||
----------------
|
||||
|
||||
Section 8 - Guide Report
|
||||
------------------------
|
||||
Guide not run on this design.
|
||||
|
||||
Section 9 - Area Group and Partition Summary
|
||||
--------------------------------------------
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
Area Group Information
|
||||
----------------------
|
||||
|
||||
No area groups were found in this design.
|
||||
|
||||
----------------------
|
||||
|
||||
Section 10 - Timing Report
|
||||
--------------------------
|
||||
A logic-level (pre-route) timing report can be generated by using Xilinx static
|
||||
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
|
||||
mapped NCD and PCF files. Please note that this timing report will be generated
|
||||
using estimated delay information. For accurate numbers, please generate a
|
||||
timing report with the post Place and Route NCD file.
|
||||
|
||||
For more information about the Timing Analyzer, consult the Xilinx Timing
|
||||
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
|
||||
Command Line Tools User Guide "TRACE" chapter.
|
||||
|
||||
Section 11 - Configuration String Details
|
||||
-----------------------------------------
|
||||
Use the "-detail" map option to print out Configuration Strings
|
||||
|
||||
Section 12 - Control Set Information
|
||||
------------------------------------
|
||||
Use the "-detail" map option to print out Control Set Information.
|
||||
|
||||
Section 13 - Utilization by Hierarchy
|
||||
-------------------------------------
|
||||
Use the "-detail" map option to print out the Utilization by Hierarchy section.
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,62 @@
|
|||
Release 14.7 Physical Synthesis Report P.20131013 (nt64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
TABLE OF CONTENTS
|
||||
1) Physical Synthesis Options Summary
|
||||
2) Optimizations statistics and details
|
||||
|
||||
|
||||
=========================================================================
|
||||
* Physical Synthesis Options Summary *
|
||||
=========================================================================
|
||||
---- Options
|
||||
Global Optimization : OFF
|
||||
Retiming : OFF
|
||||
Equivalent Register Removal : OFF
|
||||
Timing-Driven Packing and Placement : ON
|
||||
Logic Optimization : OFF
|
||||
Register Duplication : ON
|
||||
|
||||
---- Intelligent clock gating : OFF
|
||||
|
||||
---- Target Parameters
|
||||
Target Device : 6slx9tqg144-3
|
||||
|
||||
=========================================================================
|
||||
|
||||
|
||||
=========================================================================
|
||||
* Optimizations *
|
||||
=========================================================================
|
||||
---- Statistics
|
||||
Number of LUTs added by Replication | 19
|
||||
|
||||
Overall change in number of design objects | +19
|
||||
|
||||
|
||||
---- Details
|
||||
|
||||
New or modified components | Optimization | Objective
|
||||
-------------------------------------------------------|--------------------------|----------------------
|
||||
EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux131_REPLICA_14| Replication | Fanout Optimization
|
||||
EU_CORE/Mmux_n045543_REPLICA_16 | Replication | Fanout Optimization
|
||||
EU_CORE/Mmux_n045572_REPLICA_15 | Replication | Fanout Optimization
|
||||
EU_CORE/carry<9>1_REPLICA_17 | Replication | Fanout Optimization
|
||||
EU_CORE/eu_rom_data<16>_REPLICA_10 | Replication | Fanout Optimization
|
||||
EU_CORE/eu_rom_data<17>_REPLICA_5 | Replication | Fanout Optimization
|
||||
EU_CORE/eu_rom_data<17>_REPLICA_6 | Replication | Fanout Optimization
|
||||
EU_CORE/eu_rom_data<17>_REPLICA_7 | Replication | Fanout Optimization
|
||||
EU_CORE/eu_rom_data<17>_REPLICA_8 | Replication | Fanout Optimization
|
||||
EU_CORE/eu_rom_data<17>_REPLICA_9 | Replication | Fanout Optimization
|
||||
EU_CORE/eu_rom_data<19>1_REPLICA_18 | Replication | Fanout Optimization
|
||||
EU_CORE/eu_rom_data<20>_REPLICA_0 | Replication | Fanout Optimization
|
||||
EU_CORE/eu_rom_data<20>_REPLICA_1 | Replication | Fanout Optimization
|
||||
EU_CORE/eu_rom_data<20>_REPLICA_2 | Replication | Fanout Optimization
|
||||
EU_CORE/eu_rom_data<20>_REPLICA_3 | Replication | Fanout Optimization
|
||||
EU_CORE/eu_rom_data<21>_REPLICA_4 | Replication | Fanout Optimization
|
||||
EU_CORE/eu_rom_data<22>_REPLICA_11 | Replication | Fanout Optimization
|
||||
EU_CORE/eu_rom_data<22>_REPLICA_12 | Replication | Fanout Optimization
|
||||
EU_CORE/eu_rom_data<22>_REPLICA_13 | Replication | Fanout Optimization
|
||||
|
||||
Flops added for Enable Generation
|
||||
-------------------------
|
||||
|
|
@ -0,0 +1,789 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<document OS="nt64" product="ISE" version="14.7">
|
||||
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Map" timeStamp="Wed Nov 11 19:10:57 2020">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
<column stringID="value"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="variable" value="Path"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ProgramData\Oracle\Java\javapath;C:\Program Files (x86)\SemanticDesigns\DMS\Executables;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\Intel\WiFi\bin\;C:\Program Files\Common Files\Intel\WirelessCommon\;C:\altera_lite\15.1\modelsim_ase\win32aloem;C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem"/>
|
||||
</row>
|
||||
<row stringID="row" value="1">
|
||||
<item stringID="variable" value="PATHEXT"/>
|
||||
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item stringID="variable" value="XILINX"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\"/>
|
||||
</row>
|
||||
<row stringID="row" value="3">
|
||||
<item stringID="variable" value="XILINX_DSP"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE"/>
|
||||
</row>
|
||||
<row stringID="row" value="4">
|
||||
<item stringID="variable" value="XILINX_EDK"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\EDK"/>
|
||||
</row>
|
||||
<row stringID="row" value="5">
|
||||
<item stringID="variable" value="XILINX_PLANAHEAD"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\PlanAhead"/>
|
||||
</row>
|
||||
</table>
|
||||
<item stringID="User_EnvOs" value="OS Information">
|
||||
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
|
||||
<item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/>
|
||||
</item>
|
||||
<item stringID="User_EnvHost" value="MicroCoreLabs"/>
|
||||
<table stringID="User_EnvCpu">
|
||||
<column stringID="arch"/>
|
||||
<column stringID="speed"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="arch" value="Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz"/>
|
||||
<item stringID="speed" value="2492 MHz"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
<section stringID="MAP_OPTION_SUMMARY">
|
||||
<item DEFAULT="high" label="-ol" stringID="MAP_EFFORTLEVEL" value="high"/>
|
||||
<item DEFAULT="" label="-xe" stringID="MAP_EXTRAEFFORTLEVEL" value="NORMAL"/>
|
||||
<item DEFAULT="0" label="-xt" stringID="MAP_EXTRA_COST_TABLE" value="0"/>
|
||||
<item DEFAULT="OFF" label="-ir" stringID="MAP_IGNORERLOCS" value="OFF"/>
|
||||
<item DEFAULT="OFF" stringID="MAP_LUTCOMPRESSIONMODE" value="OFF"/>
|
||||
<item DEFAULT="0" label="-t" stringID="MAP_PLACERCOSTTABLE" value="2"/>
|
||||
<item DEFAULT="4" label="-r" stringID="MAP_REGORDERING" value="4"/>
|
||||
<item DEFAULT="FALSE" stringID="MAP_REPLICATELUTS" value="TRUE"/>
|
||||
<item DEFAULT="FALSE" label="-register_duplication" stringID="MAP_REPLICATEREGISTERS" value="TRUE"/>
|
||||
<item DEFAULT="None" label="-intstyle" stringID="MAP_INTSTYLE" value="ise"/>
|
||||
<item DEFAULT="off" label="-lc" stringID="MAP_LUT_COMBINING" value="off"/>
|
||||
<item DEFAULT="None" label="-o" stringID="MAP_OUTFILE" value="MCL86jr_map.ncd"/>
|
||||
<item DEFAULT="false" label="-w" stringID="MAP_OVERWRITE_OUTPUT" value="true"/>
|
||||
<item DEFAULT="off" label="-pr" stringID="MAP_PACK_INTERNAL" value="b"/>
|
||||
<item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc6slx9-tqg144-3"/>
|
||||
</section>
|
||||
<task stringID="MAP_PACK_REPORT">
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="853">
|
||||
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="853"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="932">
|
||||
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="54"/>
|
||||
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="662"/>
|
||||
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="152"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="2"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="56"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="6"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="6"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="102" dataType="int" stringID="MAP_AGG_BONDED_IO" value="75"/>
|
||||
<item AVAILABLE="98" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="39"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
|
||||
<item AVAILABLE="49" dataType="int" stringID="MAP_NUM_IOBM" value="0"/>
|
||||
<item AVAILABLE="51" dataType="int" stringID="MAP_NUM_BONDED_IOBM" value="0"/>
|
||||
<item AVAILABLE="49" dataType="int" stringID="MAP_NUM_IOBS" value="0"/>
|
||||
<item AVAILABLE="51" dataType="int" stringID="MAP_NUM_BONDED_IOBS" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IPAD" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_IPAD" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_OPAD" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_OPAD" value="0"/>
|
||||
<section stringID="MAP_DESIGN_INFORMATION">
|
||||
<item stringID="MAP_PART" value="6slx9tqg144-3"/>
|
||||
<item stringID="MAP_DEVICE" value="xc6slx9"/>
|
||||
<item stringID="MAP_ARCHITECTURE" value="spartan6"/>
|
||||
<item stringID="MAP_PACKAGE" value="tqg144"/>
|
||||
<item stringID="MAP_SPEED" value="-3"/>
|
||||
</section>
|
||||
<section stringID="MAP_DESIGN_SUMMARY">
|
||||
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
|
||||
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="2"/>
|
||||
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="451876"/>
|
||||
<item stringID="MAP_TOTAL_REAL_TIME" value="33 secs "/>
|
||||
<item stringID="MAP_TOTAL_CPU_TIME" value="32 secs "/>
|
||||
</section>
|
||||
<section stringID="MAP_SLICE_REPORTING">
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="853">
|
||||
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="853"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="959">
|
||||
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="54"/>
|
||||
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="681"/>
|
||||
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="152"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="2"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="56"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="6"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="8"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="8"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="6"/>
|
||||
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
|
||||
</item>
|
||||
<item AVAILABLE="1430" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="381">
|
||||
<item AVAILABLE="355" dataType="int" stringID="MAP_NUM_SLICEL" value="83"/>
|
||||
<item AVAILABLE="360" dataType="int" stringID="MAP_NUM_SLICEM" value="15"/>
|
||||
<item AVAILABLE="715" dataType="int" stringID="MAP_NUM_SLICEX" value="283"/>
|
||||
</item>
|
||||
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="1197">
|
||||
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="437"/>
|
||||
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="238"/>
|
||||
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="522"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="MAP_IOB_REPORTING">
|
||||
<item AVAILABLE="102" dataType="int" stringID="MAP_AGG_BONDED_IO" value="75"/>
|
||||
<item AVAILABLE="98" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="39"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
|
||||
<item AVAILABLE="49" dataType="int" stringID="MAP_NUM_IOBM" value="0"/>
|
||||
<item AVAILABLE="51" dataType="int" stringID="MAP_NUM_BONDED_IOBM" value="0"/>
|
||||
<item AVAILABLE="49" dataType="int" stringID="MAP_NUM_IOBS" value="0"/>
|
||||
<item AVAILABLE="51" dataType="int" stringID="MAP_NUM_BONDED_IOBS" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IPAD" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_IPAD" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_OPAD" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_OPAD" value="0"/>
|
||||
</section>
|
||||
<section stringID="MAP_HARD_IP_REPORTING"/>
|
||||
<section stringID="MAP_RAM_FIFO_DATA">
|
||||
<item AVAILABLE="32" dataType="int" stringID="MAP_NUM_RAMB16BWER" value="7"/>
|
||||
<item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="1"/>
|
||||
</section>
|
||||
<section stringID="MAP_IP_DATA">
|
||||
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BSCAN" value="0"/>
|
||||
<item AVAILABLE="128" dataType="int" stringID="MAP_NUM_BUFH" value="0"/>
|
||||
<item AVAILABLE="8" dataType="int" stringID="MAP_NUM_BUFPLL" value="0"/>
|
||||
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BUFPLL_MCB" value="0"/>
|
||||
<item AVAILABLE="16" dataType="int" stringID="MAP_NUM_DSP48A1" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_GTPA1_DUAL" value="0"/>
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_ICAP" value="0"/>
|
||||
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_MCB" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_PCIE_A1" value="0"/>
|
||||
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PCILOGICSE" value="0"/>
|
||||
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PLL_ADV" value="0"/>
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_PMV" value="0"/>
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_STARTUP" value="0"/>
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
|
||||
</section>
|
||||
<section stringID="MAP_BUFG_DATA">
|
||||
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="1"/>
|
||||
<item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
|
||||
<item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
|
||||
</section>
|
||||
<section stringID="MAP_MACRO_RPM_REPORTING">
|
||||
<item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
|
||||
<item dataType="int" stringID="MAP_RPMS" value="0"/>
|
||||
</section>
|
||||
<section stringID="MAP_IOB_PROPERTIES">
|
||||
<table stringID="MAP_IOB_TABLE">
|
||||
<column label="IOB
Name" sort="smart" stringID="IOB_NAME"/>
|
||||
<column stringID="Type"/>
|
||||
<column stringID="Direction"/>
|
||||
<column label="IO
Standard" sort="smart" stringID="IO_STANDARD"/>
|
||||
<column label="Diff
Term" stringID="DIFF_TERM"/>
|
||||
<column label="Drive
Strength" stringID="DRIVE_STRENGTH"/>
|
||||
<column label="Slew
Rate" stringID="SLEW_RATE"/>
|
||||
<column label="Reg
(s)" stringID="REGS"/>
|
||||
<column stringID="Resistor"/>
|
||||
<column label="IOB
Delay" stringID="IOB_DELAY"/>
|
||||
<row stringID="row" value="1">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="A8"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="OFF"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="A9"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="OFF"/>
|
||||
</row>
|
||||
<row stringID="row" value="3">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="A10"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="OFF"/>
|
||||
</row>
|
||||
<row stringID="row" value="4">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="A11"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="OFF"/>
|
||||
</row>
|
||||
<row stringID="row" value="5">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="A12"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="OFF"/>
|
||||
</row>
|
||||
<row stringID="row" value="6">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="A13"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="OFF"/>
|
||||
</row>
|
||||
<row stringID="row" value="7">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="A14"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="OFF"/>
|
||||
</row>
|
||||
<row stringID="row" value="8">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="A15"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="OFF"/>
|
||||
</row>
|
||||
<row stringID="row" value="9">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="A16"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="OFF"/>
|
||||
</row>
|
||||
<row stringID="row" value="10">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="A17"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="OFF"/>
|
||||
</row>
|
||||
<row stringID="row" value="11">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="A18"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="OFF"/>
|
||||
</row>
|
||||
<row stringID="row" value="12">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="A19"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="OFF"/>
|
||||
</row>
|
||||
<row stringID="row" value="13">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="AD0"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF OFF"/>
|
||||
</row>
|
||||
<row stringID="row" value="14">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="AD1"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF OFF"/>
|
||||
</row>
|
||||
<row stringID="row" value="15">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="AD2"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
<item label="Reg
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
</row>
|
||||
<row stringID="row" value="68">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="SRAM_D<4>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
</row>
|
||||
<row stringID="row" value="69">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="SRAM_D<5>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
</row>
|
||||
<row stringID="row" value="70">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="SRAM_D<6>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
</row>
|
||||
<row stringID="row" value="71">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="SRAM_D<7>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
</row>
|
||||
<row stringID="row" value="72">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="SRAM_OE_n"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
</row>
|
||||
<row stringID="row" value="73">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="SRAM_WE_n"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
</row>
|
||||
<row stringID="row" value="74">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="SSO_n"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
</row>
|
||||
<row stringID="row" value="75">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="WR_n"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="OFF"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
<section stringID="MAP_RPM_MACROS">
|
||||
<section stringID="MAP_SHAPE_SECTION">
|
||||
<item dataType="int" stringID="MAP_NUM_SHAPE" value="11"/>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="MAP_GUIDE_REPORT"/>
|
||||
<section stringID="MAP_AREA_GROUPS_PARTITIONS"/>
|
||||
<section stringID="MAP_TIMING_REPORT"/>
|
||||
<section stringID="MAP_CONFIGURATION_STRING_DETAILS"/>
|
||||
<section stringID="MAP_GENERAL_CONFIG_DATA">
|
||||
<item stringID="MAP_CLKDV_DIVIDE" value="2.0"/>
|
||||
<item stringID="MAP_CLKIN_DIVIDE_BY_2" value="FALSE"/>
|
||||
<item stringID="MAP_CLKOUT_PHASE_SHIFT" value="NONE"/>
|
||||
<item stringID="MAP_CLK_FEEDBACK" value="NONE"/>
|
||||
<item stringID="MAP_DESKEW_ADJUST" value="5"/>
|
||||
<item stringID="MAP_DFS_FREQUENCY_MODE" value="LOW"/>
|
||||
<item stringID="MAP_DLL_FREQUENCY_MODE" value="LOW"/>
|
||||
<item stringID="MAP_DSS_MODE" value="NONE"/>
|
||||
<item stringID="MAP_DUTY_CYCLE_CORRECTION" value="TRUE"/>
|
||||
<item stringID="MAP_STARTUP_WAIT" value="FALSE"/>
|
||||
<item stringID="MAP_VERY_HIGH_FREQUENCY" value="FALSE"/>
|
||||
<item stringID="MAP_CLKFX_DIVIDE" value="5"/>
|
||||
<item stringID="MAP_CLKFX_MULTIPLY" value="11"/>
|
||||
<item stringID="MAP_CLKIN_PERIOD" value="20.000000"/>
|
||||
<item stringID="MAP_PHASE_SHIFT" value="0"/>
|
||||
</section>
|
||||
<section stringID="MAP_CONTROL_SET_INFORMATION">
|
||||
<item dataType="int" label="Number of unique control sets" stringID="MAP_NUM_CONTROL_SETS" value="40"/>
|
||||
<tree stringID="MAP_CONTROL_SET_HIERARCHY">
|
||||
<property stringID="MAP_CLOCK_SIGNAL"/>
|
||||
<property stringID="MAP_RESET_SIGNAL"/>
|
||||
<property stringID="MAP_SET_SIGNAL"/>
|
||||
<property stringID="MAP_ENABLE_SIGNAL"/>
|
||||
<property label="Slice
Load Count" stringID="MAP_SLICE_LOAD_COUNT"/>
|
||||
<property label="Bel
Load Count" stringID="MAP_BEL_LOAD_COUNT"/>
|
||||
</tree>
|
||||
</section>
|
||||
</task>
|
||||
<section stringID="MAP_RAM_FIFO_DATA">
|
||||
<item AVAILABLE="32" dataType="int" stringID="MAP_NUM_RAMB16BWER" value="7"/>
|
||||
<item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="1"/>
|
||||
</section>
|
||||
<section stringID="MAP_IP_DATA">
|
||||
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BSCAN" value="0"/>
|
||||
<item AVAILABLE="128" dataType="int" stringID="MAP_NUM_BUFH" value="0"/>
|
||||
<item AVAILABLE="8" dataType="int" stringID="MAP_NUM_BUFPLL" value="0"/>
|
||||
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BUFPLL_MCB" value="0"/>
|
||||
<item AVAILABLE="16" dataType="int" stringID="MAP_NUM_DSP48A1" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_GTPA1_DUAL" value="0"/>
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_ICAP" value="0"/>
|
||||
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_MCB" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_PCIE_A1" value="0"/>
|
||||
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PCILOGICSE" value="0"/>
|
||||
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PLL_ADV" value="0"/>
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_PMV" value="0"/>
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_STARTUP" value="0"/>
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
|
||||
</section>
|
||||
<section stringID="MAP_BUFG_DATA">
|
||||
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="1"/>
|
||||
<item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
|
||||
<item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
|
||||
<item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
|
||||
<item dataType="int" stringID="MAP_RPMS" value="0"/>
|
||||
<item stringID="MAP_CLKDV_DIVIDE" value="2.0"/>
|
||||
<item stringID="MAP_CLKIN_DIVIDE_BY_2" value="FALSE"/>
|
||||
<item stringID="MAP_CLKOUT_PHASE_SHIFT" value="NONE"/>
|
||||
<item stringID="MAP_CLK_FEEDBACK" value="NONE"/>
|
||||
<item stringID="MAP_DESKEW_ADJUST" value="5"/>
|
||||
<item stringID="MAP_DFS_FREQUENCY_MODE" value="LOW"/>
|
||||
<item stringID="MAP_DLL_FREQUENCY_MODE" value="LOW"/>
|
||||
<item stringID="MAP_DSS_MODE" value="NONE"/>
|
||||
<item stringID="MAP_DUTY_CYCLE_CORRECTION" value="TRUE"/>
|
||||
<item stringID="MAP_STARTUP_WAIT" value="FALSE"/>
|
||||
<item stringID="MAP_VERY_HIGH_FREQUENCY" value="FALSE"/>
|
||||
<item stringID="MAP_CLKFX_DIVIDE" value="5"/>
|
||||
<item stringID="MAP_CLKFX_MULTIPLY" value="11"/>
|
||||
<item stringID="MAP_CLKIN_PERIOD" value="20.000000"/>
|
||||
<item stringID="MAP_PHASE_SHIFT" value="0"/>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
</document>
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<document OS="nt64" product="ISE" version="14.7">
|
||||
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="NgdBuild" timeStamp="Wed Nov 11 19:10:20 2020">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
<column stringID="value"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="variable" value="Path"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ProgramData\Oracle\Java\javapath;C:\Program Files (x86)\SemanticDesigns\DMS\Executables;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\Intel\WiFi\bin\;C:\Program Files\Common Files\Intel\WirelessCommon\;C:\altera_lite\15.1\modelsim_ase\win32aloem;C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem"/>
|
||||
</row>
|
||||
<row stringID="row" value="1">
|
||||
<item stringID="variable" value="PATHEXT"/>
|
||||
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item stringID="variable" value="XILINX"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\"/>
|
||||
</row>
|
||||
<row stringID="row" value="3">
|
||||
<item stringID="variable" value="XILINX_DSP"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE"/>
|
||||
</row>
|
||||
<row stringID="row" value="4">
|
||||
<item stringID="variable" value="XILINX_EDK"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\EDK"/>
|
||||
</row>
|
||||
<row stringID="row" value="5">
|
||||
<item stringID="variable" value="XILINX_PLANAHEAD"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\PlanAhead"/>
|
||||
</row>
|
||||
</table>
|
||||
<item stringID="User_EnvOs" value="OS Information">
|
||||
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
|
||||
<item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/>
|
||||
</item>
|
||||
<item stringID="User_EnvHost" value="MicroCoreLabs"/>
|
||||
<table stringID="User_EnvCpu">
|
||||
<column stringID="arch"/>
|
||||
<column stringID="speed"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="arch" value="Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz"/>
|
||||
<item stringID="speed" value="2492 MHz"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
<task stringID="NGDBUILD_OPTION_SUMMARY">
|
||||
<section stringID="NGDBUILD_OPTION_SUMMARY">
|
||||
<item DEFAULT="None" label="-intstyle" stringID="NGDBUILD_intstyle" value="ise"/>
|
||||
<item DEFAULT="None" label="-dd" stringID="NGDBUILD_output_dir" value="_ngo"/>
|
||||
<item DEFAULT="None" label="-p" stringID="NGDBUILD_partname" value="xc6slx9-tqg144-3"/>
|
||||
<item DEFAULT="None" label="-sd" stringID="NGDBUILD_search_path" value="ipcore_dir"/>
|
||||
<item DEFAULT="None" label="-uc" stringID="NGDBUILD_ucf_file" value="MCL86jr.ucf"/>
|
||||
</section>
|
||||
</task>
|
||||
<task stringID="NGDBUILD_REPORT">
|
||||
<section stringID="NGDBUILD_DESIGN_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="1"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_DCM_SP" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="48"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="183"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="125"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="503"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="13"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="20"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="5"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="15"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IOBUF" value="16"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="60"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="87"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="116"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="73"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="223"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="384"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="175"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="59"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXF8" value="25"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="53"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_RAMB16BWER" value="7"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_RAMB8BWER" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="114"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="186"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_DCM_SP" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="48"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="183"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="125"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="503"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="13"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="20"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="21"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="15"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="60"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="87"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="116"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="73"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="223"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="384"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="175"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="59"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXF8" value="25"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="53"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="16"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_PULLDOWN" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_RAMB16BWER" value="7"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_RAMB8BWER" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="114"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="186"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_CORE_SUMMARY">
|
||||
<item COUNT="1" stringID="NGDBUILD_CORE" value="blk_mem_gen_v7_3, Xilinx CORE Generator 14.7"/>
|
||||
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
|
||||
<section stringID="NGDBUILD_CORE_INSTANCES">
|
||||
<scope stringID="NGDBUILD_CORE_INSTANCE" value="EU4Kx32">
|
||||
<item stringID="NGDBUILD_CORE_INFO" type="blk_mem_gen_v7_3" value="EU4Kx32"/>
|
||||
<item c_addra_width="12" c_addrb_width="12" c_algorithm="1" c_axi_id_width="4" c_axi_slave_type="0" c_axi_type="1" c_byte_size="9" c_common_clk="0" c_default_data="0" c_disable_warn_bhv_coll="0" c_disable_warn_bhv_range="0" c_elaboration_dir="masked_value" c_enable_32bit_address="0" c_family="spartan6" c_has_axi_id="0" c_has_ena="0" c_has_enb="0" c_has_injecterr="0" c_has_mem_output_regs_a="0" c_has_mem_output_regs_b="0" c_has_mux_output_regs_a="0" c_has_mux_output_regs_b="0" c_has_regcea="0" c_has_regceb="0" c_has_rsta="0" c_has_rstb="0" c_has_softecc_input_regs_a="0" c_has_softecc_output_regs_b="0" c_init_file="BlankString" c_init_file_name="fname.mif" c_inita_val="0" c_initb_val="0" c_interface_type="0" c_load_init_file="1" c_mem_type="3" c_mux_pipeline_stages="0" c_prim_type="1" c_read_depth_a="4096" c_read_depth_b="4096" c_read_width_a="32" c_read_width_b="32" c_rst_priority_a="CE" c_rst_priority_b="CE" c_rst_type="SYNC" c_rstram_a="0" c_rstram_b="0" c_sim_collision_check="ALL" c_use_bram_block="0" c_use_byte_wea="0" c_use_byte_web="0" c_use_default_data="0" c_use_ecc="0" c_use_softecc="0" c_wea_width="1" c_web_width="1" c_write_depth_a="4096" c_write_depth_b="4096" c_write_mode_a="WRITE_FIRST" c_write_mode_b="WRITE_FIRST" c_write_width_a="32" c_write_width_b="32" c_xdevicefamily="spartan6" stringID="NGDBUILD_CORE_PARAMETERS" value="EU4Kx32"/>
|
||||
</scope>
|
||||
<scope stringID="NGDBUILD_CORE_INSTANCE" value="spartan6_pll">
|
||||
<item stringID="NGDBUILD_CORE_INFO" type="clk_wiz_v3_6" value="spartan6_pll"/>
|
||||
<item clkin1_period="20.0" clkin2_period="20.0" clock_mgr_type="AUTO" component_name="spartan6_pll" feedback_source="FDBK_AUTO" feedback_type="SINGLE" manual_override="false" num_out_clk="1" primtype_sel="DCM_SP" stringID="NGDBUILD_CORE_PARAMETERS" use_clk_valid="false" use_dyn_phase_shift="false" use_dyn_reconfig="false" use_freeze="false" use_inclk_stopped="false" use_inclk_switchover="false" use_locked="false" use_max_i_jitter="false" use_min_o_jitter="false" use_phase_alignment="false" use_power_down="false" use_reset="false" use_status="false" value="spartan6_pll"/>
|
||||
</scope>
|
||||
</section>
|
||||
</section>
|
||||
</section>
|
||||
</task>
|
||||
</application>
|
||||
|
||||
</document>
|
||||
|
|
@ -0,0 +1,175 @@
|
|||
#Release 14.7 - par P.20131013 (nt64)
|
||||
#Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
#Wed Nov 11 19:11:33 2020
|
||||
|
||||
#
|
||||
## NOTE: This file is designed to be imported into a spreadsheet program
|
||||
# such as Microsoft Excel for viewing, printing and sorting. The |
|
||||
# character is used as the data field separator. This file is also designed
|
||||
# to support parsing.
|
||||
#
|
||||
#INPUT FILE: MCL86jr_map.ncd
|
||||
#OUTPUT FILE: MCL86jr_pad.csv
|
||||
#PART TYPE: xc6slx9
|
||||
#SPEED GRADE: -3
|
||||
#PACKAGE: tqg144
|
||||
#
|
||||
# Pinout by Pin Number:
|
||||
#
|
||||
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
|
||||
Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity,
|
||||
P1,A13,IOB,IO_L83N_VREF_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,YES,NONE,
|
||||
P2,A16,IOB,IO_L83P_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,YES,NONE,
|
||||
P3,,,GND,,,,,,,,,,,,
|
||||
P4,,,VCCO_3,,,3,,,,,3.30,,,,
|
||||
P5,A12,IOB,IO_L52N_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,YES,NONE,
|
||||
P6,A17,IOB,IO_L52P_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,YES,NONE,
|
||||
P7,A11,IOB,IO_L51N_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,YES,NONE,
|
||||
P8,A18,IOB,IO_L51P_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,YES,NONE,
|
||||
P9,A10,IOB,IO_L50N_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,YES,NONE,
|
||||
P10,A19,IOB,IO_L50P_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,YES,NONE,
|
||||
P11,A9,IOB,IO_L49N_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,YES,NONE,
|
||||
P12,SSO_n,IOB,IO_L49P_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,NO,NONE,
|
||||
P13,,,GND,,,,,,,,,,,,
|
||||
P14,A8,IOB,IO_L44N_GCLK20_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,YES,NONE,
|
||||
P15,,IOBM,IO_L44P_GCLK21_3,UNUSED,,3,,,,,,,,,
|
||||
P16,BUF2_DIR,IOB,IO_L43N_GCLK22_IRDY2_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,NO,NONE,
|
||||
P17,,IOBM,IO_L43P_GCLK23_3,UNUSED,,3,,,,,,,,,
|
||||
P18,,,VCCO_3,,,3,,,,,3.30,,,,
|
||||
P19,,,VCCINT,,,,,,,,1.2,,,,
|
||||
P20,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
P21,BUF2_OE_n,IOB,IO_L42N_GCLK24_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,NO,NONE,
|
||||
P22,AD7,IOB,IO_L42P_GCLK25_TRDY2_3,BIDIR,PCI33_3,3,,,,NONE,,LOCATED,YES,NONE,
|
||||
P23,AD6,IOB,IO_L41N_GCLK26_3,BIDIR,PCI33_3,3,,,,NONE,,LOCATED,YES,NONE,
|
||||
P24,,IOBM,IO_L41P_GCLK27_3,UNUSED,,3,,,,,,,,,
|
||||
P25,,,GND,,,,,,,,,,,,
|
||||
P26,AD5,IOB,IO_L37N_3,BIDIR,PCI33_3,3,,,,NONE,,LOCATED,YES,NONE,
|
||||
P27,AD4,IOB,IO_L37P_3,BIDIR,PCI33_3,3,,,,NONE,,LOCATED,YES,NONE,
|
||||
P28,,,VCCINT,,,,,,,,1.2,,,,
|
||||
P29,,IOBS,IO_L36N_3,UNUSED,,3,,,,,,,,,
|
||||
P30,,IOBM,IO_L36P_3,UNUSED,,3,,,,,,,,,
|
||||
P31,,,VCCO_3,,,3,,,,,3.30,,,,
|
||||
P32,AD3,IOB,IO_L2N_3,BIDIR,PCI33_3,3,,,,NONE,,LOCATED,YES,NONE,
|
||||
P33,AD2,IOB,IO_L2P_3,BIDIR,PCI33_3,3,,,,NONE,,LOCATED,YES,NONE,
|
||||
P34,AD1,IOB,IO_L1N_VREF_3,BIDIR,PCI33_3,3,,,,NONE,,LOCATED,YES,NONE,
|
||||
P35,AD0,IOB,IO_L1P_3,BIDIR,PCI33_3,3,,,,NONE,,LOCATED,YES,NONE,
|
||||
P36,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
P37,,,PROGRAM_B_2,,,,,,,,,,,,
|
||||
P38,,IOBS,IO_L65N_CSO_B_2,UNUSED,,2,,,,,,,,,
|
||||
P39,,IOBM,IO_L65P_INIT_B_2,UNUSED,,2,,,,,,,,,
|
||||
P40,,IOBS,IO_L64N_D9_2,UNUSED,,2,,,,,,,,,
|
||||
P41,ALE,IOB,IO_L64P_D8_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,YES,NONE,
|
||||
P42,,,VCCO_2,,,2,,,,,3.30,,,,
|
||||
P43,,IOBS,IO_L62N_D6_2,UNUSED,,2,,,,,,,,,
|
||||
P44,NMI,IOB,IO_L62P_D5_2,INPUT,LVCMOS33,2,,,PULLDOWN,NONE,,LOCATED,YES,NONE,
|
||||
P45,INTR,IOB,IO_L49N_D4_2,INPUT,PCI33_3,2,,,,NONE,,LOCATED,YES,NONE,
|
||||
P46,CLK,IOB,IO_L49P_D3_2,INPUT,PCI33_3,2,,,,NONE,,LOCATED,YES,NONE,
|
||||
P47,RESET,IOB,IO_L48N_RDWR_B_VREF_2,INPUT,PCI33_3,2,,,,NONE,,LOCATED,NO,NONE,
|
||||
P48,READY,IOB,IO_L48P_D7_2,INPUT,PCI33_3,2,,,,NONE,,LOCATED,YES,NONE,
|
||||
P49,,,GND,,,,,,,,,,,,
|
||||
P50,RD_n,IOB,IO_L31N_GCLK30_D15_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,YES,NONE,
|
||||
P51,WR_n,IOB,IO_L31P_GCLK31_D14_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,YES,NONE,
|
||||
P52,,,VCCINT,,,,,,,,1.2,,,,
|
||||
P53,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
P54,,,GND,,,,,,,,,,,,
|
||||
P55,IOM,IOB,IO_L30N_GCLK0_USERCCLK_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,YES,NONE,
|
||||
P56,DTR,IOB,IO_L30P_GCLK1_D13_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,YES,NONE,
|
||||
P57,DEN,IOB,IO_L14N_D12_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,YES,NONE,
|
||||
P58,INTA_n,IOB,IO_L14P_D11_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,YES,NONE,
|
||||
P59,BUF1_OE_n,IOB,IO_L13N_D10_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,NO,NONE,
|
||||
P60,,IOBM,IO_L13P_M1_2,UNUSED,,2,,,,,,,,,
|
||||
P61,SRAM_A<4>,IOB,IO_L12N_D2_MISO3_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,NO,NONE,
|
||||
P62,SRAM_A<5>,IOB,IO_L12P_D1_MISO2_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,NO,NONE,
|
||||
P63,,,VCCO_2,,,2,,,,,3.30,,,,
|
||||
P64,,IOBS,IO_L3N_MOSI_CSI_B_MISO0_2,UNUSED,,2,,,,,,,,,
|
||||
P65,,IOBM,IO_L3P_D0_DIN_MISO_MISO1_2,UNUSED,,2,,,,,,,,,
|
||||
P66,SRAM_A<6>,IOB,IO_L2N_CMPMOSI_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,NO,NONE,
|
||||
P67,SRAM_A<7>,IOB,IO_L2P_CMPCLK_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,NO,NONE,
|
||||
P68,,,GND,,,,,,,,,,,,
|
||||
P69,,IOBS,IO_L1N_M0_CMPMISO_2,UNUSED,,2,,,,,,,,,
|
||||
P70,,IOBM,IO_L1P_CCLK_2,UNUSED,,2,,,,,,,,,
|
||||
P71,,,DONE_2,,,,,,,,,,,,
|
||||
P72,,,CMPCS_B_2,,,,,,,,,,,,
|
||||
P73,,,SUSPEND,,,,,,,,,,,,
|
||||
P74,SRAM_A<12>,IOB,IO_L74N_DOUT_BUSY_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
|
||||
P75,SRAM_A<14>,IOB,IO_L74P_AWAKE_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
|
||||
P76,,,VCCO_1,,,1,,,,,3.30,,,,
|
||||
P77,,,GND,,,,,,,,,,,,
|
||||
P78,SRAM_A<16>,IOB,IO_L47N_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
|
||||
P79,SRAM_A<17>,IOB,IO_L47P_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
|
||||
P80,SRAM_D<3>,IOB,IO_L46N_1,BIDIR,PCI33_3,1,,,,NONE,,LOCATED,NO,NONE,
|
||||
P81,SRAM_D<4>,IOB,IO_L46P_1,BIDIR,PCI33_3,1,,,,NONE,,LOCATED,NO,NONE,
|
||||
P82,SRAM_D<5>,IOB,IO_L45N_1,BIDIR,PCI33_3,1,,,,NONE,,LOCATED,NO,NONE,
|
||||
P83,SRAM_D<6>,IOB,IO_L45P_1,BIDIR,PCI33_3,1,,,,NONE,,LOCATED,NO,NONE,
|
||||
P84,CORE_CLK,IOB,IO_L43N_GCLK4_1,INPUT,PCI33_3,1,,,,NONE,,LOCATED,NO,NONE,
|
||||
P85,SRAM_D<7>,IOB,IO_L43P_GCLK5_1,BIDIR,PCI33_3,1,,,,NONE,,LOCATED,NO,NONE,
|
||||
P86,,,VCCO_1,,,1,,,,,3.30,,,,
|
||||
P87,SRAM_CE_n,IOB,IO_L42N_GCLK6_TRDY1_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
|
||||
P88,SRAM_A<10>,IOB,IO_L42P_GCLK7_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
|
||||
P89,,,VCCINT,,,,,,,,1.2,,,,
|
||||
P90,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
P91,,,GND,,,,,,,,,,,,
|
||||
P92,SRAM_OE_n,IOB,IO_L41N_GCLK8_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
|
||||
P93,SRAM_A<11>,IOB,IO_L41P_GCLK9_IRDY1_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
|
||||
P94,SRAM_A<9>,IOB,IO_L40N_GCLK10_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
|
||||
P95,SRAM_A<8>,IOB,IO_L40P_GCLK11_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
|
||||
P96,,,GND,,,,,,,,,,,,
|
||||
P97,SRAM_A<13>,IOB,IO_L34N_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
|
||||
P98,SRAM_WE_n,IOB,IO_L34P_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
|
||||
P99,SRAM_A<18>,IOB,IO_L33N_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
|
||||
P100,SRAM_A<15>,IOB,IO_L33P_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
|
||||
P101,,IOBS,IO_L32N_1,UNUSED,,1,,,,,,,,,
|
||||
P102,,IOBM,IO_L32P_1,UNUSED,,1,,,,,,,,,
|
||||
P103,,,VCCO_1,,,1,,,,,3.30,,,,
|
||||
P104,,IOBS,IO_L1N_VREF_1,UNUSED,,1,,,,,,,,,
|
||||
P105,,IOBM,IO_L1P_1,UNUSED,,1,,,,,,,,,
|
||||
P106,,,TDO,,,,,,,,,,,,
|
||||
P107,,,TMS,,,,,,,,,,,,
|
||||
P108,,,GND,,,,,,,,,,,,
|
||||
P109,,,TCK,,,,,,,,,,,,
|
||||
P110,,,TDI,,,,,,,,,,,,
|
||||
P111,LED<0>,IOB,IO_L66N_SCP0_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
|
||||
P112,LED<1>,IOB,IO_L66P_SCP1_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
|
||||
P113,,,GND,,,,,,,,,,,,
|
||||
P114,LED<2>,IOB,IO_L65N_SCP2_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
|
||||
P115,,IOBM,IO_L65P_SCP3_0,UNUSED,,0,,,,,,,,,
|
||||
P116,LED<3>,IOB,IO_L64N_SCP4_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
|
||||
P117,SRAM_D<2>,IOB,IO_L64P_SCP5_0,BIDIR,PCI33_3,0,,,,NONE,,LOCATED,NO,NONE,
|
||||
P118,SRAM_D<1>,IOB,IO_L63N_SCP6_0,BIDIR,PCI33_3,0,,,,NONE,,LOCATED,NO,NONE,
|
||||
P119,SRAM_D<0>,IOB,IO_L63P_SCP7_0,BIDIR,PCI33_3,0,,,,NONE,,LOCATED,NO,NONE,
|
||||
P120,LED<4>,IOB,IO_L62N_VREF_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
|
||||
P121,LED<5>,IOB,IO_L62P_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
|
||||
P122,,,VCCO_0,,,0,,,,,3.30,,,,
|
||||
P123,SRAM_A<3>,IOB,IO_L37N_GCLK12_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
|
||||
P124,SRAM_A<2>,IOB,IO_L37P_GCLK13_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
|
||||
P125,,,VCCO_0,,,0,,,,,3.30,,,,
|
||||
P126,SRAM_A<1>,IOB,IO_L36N_GCLK14_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
|
||||
P127,LED<6>,IOB,IO_L36P_GCLK15_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
|
||||
P128,,,VCCINT,,,,,,,,1.2,,,,
|
||||
P129,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
P130,,,GND,,,,,,,,,,,,
|
||||
P131,LED<7>,IOB,IO_L35N_GCLK16_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
|
||||
P132,SRAM_A<0>,IOB,IO_L35P_GCLK17_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
|
||||
P133,,IOBS,IO_L34N_GCLK18_0,UNUSED,,0,,,,,,,,,
|
||||
P134,,IOBM,IO_L34P_GCLK19_0,UNUSED,,0,,,,,,,,,
|
||||
P135,,,VCCO_0,,,0,,,,,3.30,,,,
|
||||
P136,,,GND,,,,,,,,,,,,
|
||||
P137,,IOBS,IO_L4N_0,UNUSED,,0,,,,,,,,,
|
||||
P138,,IOBM,IO_L4P_0,UNUSED,,0,,,,,,,,,
|
||||
P139,,IOBS,IO_L3N_0,UNUSED,,0,,,,,,,,,
|
||||
P140,,IOBM,IO_L3P_0,UNUSED,,0,,,,,,,,,
|
||||
P141,,IOBS,IO_L2N_0,UNUSED,,0,,,,,,,,,
|
||||
P142,A14,IOB,IO_L2P_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,YES,NONE,
|
||||
P143,A15,IOB,IO_L1N_VREF_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,YES,NONE,
|
||||
P144,,IOBM,IO_L1P_HSWAPEN_0,UNUSED,,0,,,,,,,,,
|
||||
|
||||
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
|
||||
#
|
||||
#* Default value.
|
||||
#** This default Pullup/Pulldown value can be overridden in Bitgen.
|
||||
#****** Special VCCO requirements may apply. Please consult the device
|
||||
# family datasheet for specific guideline on VCCO requirements.
|
||||
#
|
||||
#
|
||||
#
|
||||
|
|
|
@ -0,0 +1,174 @@
|
|||
Release 14.7 - par P.20131013 (nt64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Wed Nov 11 19:11:33 2020
|
||||
|
||||
|
||||
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
|
||||
1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
|
||||
2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
|
||||
3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator.
|
||||
|
||||
INPUT FILE: MCL86jr_map.ncd
|
||||
OUTPUT FILE: MCL86jr_pad.txt
|
||||
PART TYPE: xc6slx9
|
||||
SPEED GRADE: -3
|
||||
PACKAGE: tqg144
|
||||
|
||||
Pinout by Pin Number:
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|P1 |A13 |IOB |IO_L83N_VREF_3 |OUTPUT |PCI33_3 |3 | | | | | |LOCATED |YES |NONE |
|
||||
|P2 |A16 |IOB |IO_L83P_3 |OUTPUT |PCI33_3 |3 | | | | | |LOCATED |YES |NONE |
|
||||
|P3 | | |GND | | | | | | | | | | | |
|
||||
|P4 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|P5 |A12 |IOB |IO_L52N_3 |OUTPUT |PCI33_3 |3 | | | | | |LOCATED |YES |NONE |
|
||||
|P6 |A17 |IOB |IO_L52P_3 |OUTPUT |PCI33_3 |3 | | | | | |LOCATED |YES |NONE |
|
||||
|P7 |A11 |IOB |IO_L51N_3 |OUTPUT |PCI33_3 |3 | | | | | |LOCATED |YES |NONE |
|
||||
|P8 |A18 |IOB |IO_L51P_3 |OUTPUT |PCI33_3 |3 | | | | | |LOCATED |YES |NONE |
|
||||
|P9 |A10 |IOB |IO_L50N_3 |OUTPUT |PCI33_3 |3 | | | | | |LOCATED |YES |NONE |
|
||||
|P10 |A19 |IOB |IO_L50P_3 |OUTPUT |PCI33_3 |3 | | | | | |LOCATED |YES |NONE |
|
||||
|P11 |A9 |IOB |IO_L49N_3 |OUTPUT |PCI33_3 |3 | | | | | |LOCATED |YES |NONE |
|
||||
|P12 |SSO_n |IOB |IO_L49P_3 |OUTPUT |PCI33_3 |3 | | | | | |LOCATED |NO |NONE |
|
||||
|P13 | | |GND | | | | | | | | | | | |
|
||||
|P14 |A8 |IOB |IO_L44N_GCLK20_3 |OUTPUT |PCI33_3 |3 | | | | | |LOCATED |YES |NONE |
|
||||
|P15 | |IOBM |IO_L44P_GCLK21_3 |UNUSED | |3 | | | | | | | | |
|
||||
|P16 |BUF2_DIR |IOB |IO_L43N_GCLK22_IRDY2_3 |OUTPUT |PCI33_3 |3 | | | | | |LOCATED |NO |NONE |
|
||||
|P17 | |IOBM |IO_L43P_GCLK23_3 |UNUSED | |3 | | | | | | | | |
|
||||
|P18 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|P19 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|P20 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|P21 |BUF2_OE_n |IOB |IO_L42N_GCLK24_3 |OUTPUT |PCI33_3 |3 | | | | | |LOCATED |NO |NONE |
|
||||
|P22 |AD7 |IOB |IO_L42P_GCLK25_TRDY2_3 |BIDIR |PCI33_3 |3 | | | |NONE | |LOCATED |YES |NONE |
|
||||
|P23 |AD6 |IOB |IO_L41N_GCLK26_3 |BIDIR |PCI33_3 |3 | | | |NONE | |LOCATED |YES |NONE |
|
||||
|P24 | |IOBM |IO_L41P_GCLK27_3 |UNUSED | |3 | | | | | | | | |
|
||||
|P25 | | |GND | | | | | | | | | | | |
|
||||
|P26 |AD5 |IOB |IO_L37N_3 |BIDIR |PCI33_3 |3 | | | |NONE | |LOCATED |YES |NONE |
|
||||
|P27 |AD4 |IOB |IO_L37P_3 |BIDIR |PCI33_3 |3 | | | |NONE | |LOCATED |YES |NONE |
|
||||
|P28 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|P29 | |IOBS |IO_L36N_3 |UNUSED | |3 | | | | | | | | |
|
||||
|P30 | |IOBM |IO_L36P_3 |UNUSED | |3 | | | | | | | | |
|
||||
|P31 | | |VCCO_3 | | |3 | | | | |3.30 | | | |
|
||||
|P32 |AD3 |IOB |IO_L2N_3 |BIDIR |PCI33_3 |3 | | | |NONE | |LOCATED |YES |NONE |
|
||||
|P33 |AD2 |IOB |IO_L2P_3 |BIDIR |PCI33_3 |3 | | | |NONE | |LOCATED |YES |NONE |
|
||||
|P34 |AD1 |IOB |IO_L1N_VREF_3 |BIDIR |PCI33_3 |3 | | | |NONE | |LOCATED |YES |NONE |
|
||||
|P35 |AD0 |IOB |IO_L1P_3 |BIDIR |PCI33_3 |3 | | | |NONE | |LOCATED |YES |NONE |
|
||||
|P36 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|P37 | | |PROGRAM_B_2 | | | | | | | | | | | |
|
||||
|P38 | |IOBS |IO_L65N_CSO_B_2 |UNUSED | |2 | | | | | | | | |
|
||||
|P39 | |IOBM |IO_L65P_INIT_B_2 |UNUSED | |2 | | | | | | | | |
|
||||
|P40 | |IOBS |IO_L64N_D9_2 |UNUSED | |2 | | | | | | | | |
|
||||
|P41 |ALE |IOB |IO_L64P_D8_2 |OUTPUT |PCI33_3 |2 | | | | | |LOCATED |YES |NONE |
|
||||
|P42 | | |VCCO_2 | | |2 | | | | |3.30 | | | |
|
||||
|P43 | |IOBS |IO_L62N_D6_2 |UNUSED | |2 | | | | | | | | |
|
||||
|P44 |NMI |IOB |IO_L62P_D5_2 |INPUT |LVCMOS33 |2 | | |PULLDOWN |NONE | |LOCATED |YES |NONE |
|
||||
|P45 |INTR |IOB |IO_L49N_D4_2 |INPUT |PCI33_3 |2 | | | |NONE | |LOCATED |YES |NONE |
|
||||
|P46 |CLK |IOB |IO_L49P_D3_2 |INPUT |PCI33_3 |2 | | | |NONE | |LOCATED |YES |NONE |
|
||||
|P47 |RESET |IOB |IO_L48N_RDWR_B_VREF_2 |INPUT |PCI33_3 |2 | | | |NONE | |LOCATED |NO |NONE |
|
||||
|P48 |READY |IOB |IO_L48P_D7_2 |INPUT |PCI33_3 |2 | | | |NONE | |LOCATED |YES |NONE |
|
||||
|P49 | | |GND | | | | | | | | | | | |
|
||||
|P50 |RD_n |IOB |IO_L31N_GCLK30_D15_2 |OUTPUT |PCI33_3 |2 | | | | | |LOCATED |YES |NONE |
|
||||
|P51 |WR_n |IOB |IO_L31P_GCLK31_D14_2 |OUTPUT |PCI33_3 |2 | | | | | |LOCATED |YES |NONE |
|
||||
|P52 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|P53 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|P54 | | |GND | | | | | | | | | | | |
|
||||
|P55 |IOM |IOB |IO_L30N_GCLK0_USERCCLK_2 |OUTPUT |PCI33_3 |2 | | | | | |LOCATED |YES |NONE |
|
||||
|P56 |DTR |IOB |IO_L30P_GCLK1_D13_2 |OUTPUT |PCI33_3 |2 | | | | | |LOCATED |YES |NONE |
|
||||
|P57 |DEN |IOB |IO_L14N_D12_2 |OUTPUT |PCI33_3 |2 | | | | | |LOCATED |YES |NONE |
|
||||
|P58 |INTA_n |IOB |IO_L14P_D11_2 |OUTPUT |PCI33_3 |2 | | | | | |LOCATED |YES |NONE |
|
||||
|P59 |BUF1_OE_n |IOB |IO_L13N_D10_2 |OUTPUT |PCI33_3 |2 | | | | | |LOCATED |NO |NONE |
|
||||
|P60 | |IOBM |IO_L13P_M1_2 |UNUSED | |2 | | | | | | | | |
|
||||
|P61 |SRAM_A<4> |IOB |IO_L12N_D2_MISO3_2 |OUTPUT |PCI33_3 |2 | | | | | |LOCATED |NO |NONE |
|
||||
|P62 |SRAM_A<5> |IOB |IO_L12P_D1_MISO2_2 |OUTPUT |PCI33_3 |2 | | | | | |LOCATED |NO |NONE |
|
||||
|P63 | | |VCCO_2 | | |2 | | | | |3.30 | | | |
|
||||
|P64 | |IOBS |IO_L3N_MOSI_CSI_B_MISO0_2 |UNUSED | |2 | | | | | | | | |
|
||||
|P65 | |IOBM |IO_L3P_D0_DIN_MISO_MISO1_2|UNUSED | |2 | | | | | | | | |
|
||||
|P66 |SRAM_A<6> |IOB |IO_L2N_CMPMOSI_2 |OUTPUT |PCI33_3 |2 | | | | | |LOCATED |NO |NONE |
|
||||
|P67 |SRAM_A<7> |IOB |IO_L2P_CMPCLK_2 |OUTPUT |PCI33_3 |2 | | | | | |LOCATED |NO |NONE |
|
||||
|P68 | | |GND | | | | | | | | | | | |
|
||||
|P69 | |IOBS |IO_L1N_M0_CMPMISO_2 |UNUSED | |2 | | | | | | | | |
|
||||
|P70 | |IOBM |IO_L1P_CCLK_2 |UNUSED | |2 | | | | | | | | |
|
||||
|P71 | | |DONE_2 | | | | | | | | | | | |
|
||||
|P72 | | |CMPCS_B_2 | | | | | | | | | | | |
|
||||
|P73 | | |SUSPEND | | | | | | | | | | | |
|
||||
|P74 |SRAM_A<12> |IOB |IO_L74N_DOUT_BUSY_1 |OUTPUT |PCI33_3 |1 | | | | | |LOCATED |NO |NONE |
|
||||
|P75 |SRAM_A<14> |IOB |IO_L74P_AWAKE_1 |OUTPUT |PCI33_3 |1 | | | | | |LOCATED |NO |NONE |
|
||||
|P76 | | |VCCO_1 | | |1 | | | | |3.30 | | | |
|
||||
|P77 | | |GND | | | | | | | | | | | |
|
||||
|P78 |SRAM_A<16> |IOB |IO_L47N_1 |OUTPUT |PCI33_3 |1 | | | | | |LOCATED |NO |NONE |
|
||||
|P79 |SRAM_A<17> |IOB |IO_L47P_1 |OUTPUT |PCI33_3 |1 | | | | | |LOCATED |NO |NONE |
|
||||
|P80 |SRAM_D<3> |IOB |IO_L46N_1 |BIDIR |PCI33_3 |1 | | | |NONE | |LOCATED |NO |NONE |
|
||||
|P81 |SRAM_D<4> |IOB |IO_L46P_1 |BIDIR |PCI33_3 |1 | | | |NONE | |LOCATED |NO |NONE |
|
||||
|P82 |SRAM_D<5> |IOB |IO_L45N_1 |BIDIR |PCI33_3 |1 | | | |NONE | |LOCATED |NO |NONE |
|
||||
|P83 |SRAM_D<6> |IOB |IO_L45P_1 |BIDIR |PCI33_3 |1 | | | |NONE | |LOCATED |NO |NONE |
|
||||
|P84 |CORE_CLK |IOB |IO_L43N_GCLK4_1 |INPUT |PCI33_3 |1 | | | |NONE | |LOCATED |NO |NONE |
|
||||
|P85 |SRAM_D<7> |IOB |IO_L43P_GCLK5_1 |BIDIR |PCI33_3 |1 | | | |NONE | |LOCATED |NO |NONE |
|
||||
|P86 | | |VCCO_1 | | |1 | | | | |3.30 | | | |
|
||||
|P87 |SRAM_CE_n |IOB |IO_L42N_GCLK6_TRDY1_1 |OUTPUT |PCI33_3 |1 | | | | | |LOCATED |NO |NONE |
|
||||
|P88 |SRAM_A<10> |IOB |IO_L42P_GCLK7_1 |OUTPUT |PCI33_3 |1 | | | | | |LOCATED |NO |NONE |
|
||||
|P89 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|P90 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|P91 | | |GND | | | | | | | | | | | |
|
||||
|P92 |SRAM_OE_n |IOB |IO_L41N_GCLK8_1 |OUTPUT |PCI33_3 |1 | | | | | |LOCATED |NO |NONE |
|
||||
|P93 |SRAM_A<11> |IOB |IO_L41P_GCLK9_IRDY1_1 |OUTPUT |PCI33_3 |1 | | | | | |LOCATED |NO |NONE |
|
||||
|P94 |SRAM_A<9> |IOB |IO_L40N_GCLK10_1 |OUTPUT |PCI33_3 |1 | | | | | |LOCATED |NO |NONE |
|
||||
|P95 |SRAM_A<8> |IOB |IO_L40P_GCLK11_1 |OUTPUT |PCI33_3 |1 | | | | | |LOCATED |NO |NONE |
|
||||
|P96 | | |GND | | | | | | | | | | | |
|
||||
|P97 |SRAM_A<13> |IOB |IO_L34N_1 |OUTPUT |PCI33_3 |1 | | | | | |LOCATED |NO |NONE |
|
||||
|P98 |SRAM_WE_n |IOB |IO_L34P_1 |OUTPUT |PCI33_3 |1 | | | | | |LOCATED |NO |NONE |
|
||||
|P99 |SRAM_A<18> |IOB |IO_L33N_1 |OUTPUT |PCI33_3 |1 | | | | | |LOCATED |NO |NONE |
|
||||
|P100 |SRAM_A<15> |IOB |IO_L33P_1 |OUTPUT |PCI33_3 |1 | | | | | |LOCATED |NO |NONE |
|
||||
|P101 | |IOBS |IO_L32N_1 |UNUSED | |1 | | | | | | | | |
|
||||
|P102 | |IOBM |IO_L32P_1 |UNUSED | |1 | | | | | | | | |
|
||||
|P103 | | |VCCO_1 | | |1 | | | | |3.30 | | | |
|
||||
|P104 | |IOBS |IO_L1N_VREF_1 |UNUSED | |1 | | | | | | | | |
|
||||
|P105 | |IOBM |IO_L1P_1 |UNUSED | |1 | | | | | | | | |
|
||||
|P106 | | |TDO | | | | | | | | | | | |
|
||||
|P107 | | |TMS | | | | | | | | | | | |
|
||||
|P108 | | |GND | | | | | | | | | | | |
|
||||
|P109 | | |TCK | | | | | | | | | | | |
|
||||
|P110 | | |TDI | | | | | | | | | | | |
|
||||
|P111 |LED<0> |IOB |IO_L66N_SCP0_0 |OUTPUT |PCI33_3 |0 | | | | | |LOCATED |NO |NONE |
|
||||
|P112 |LED<1> |IOB |IO_L66P_SCP1_0 |OUTPUT |PCI33_3 |0 | | | | | |LOCATED |NO |NONE |
|
||||
|P113 | | |GND | | | | | | | | | | | |
|
||||
|P114 |LED<2> |IOB |IO_L65N_SCP2_0 |OUTPUT |PCI33_3 |0 | | | | | |LOCATED |NO |NONE |
|
||||
|P115 | |IOBM |IO_L65P_SCP3_0 |UNUSED | |0 | | | | | | | | |
|
||||
|P116 |LED<3> |IOB |IO_L64N_SCP4_0 |OUTPUT |PCI33_3 |0 | | | | | |LOCATED |NO |NONE |
|
||||
|P117 |SRAM_D<2> |IOB |IO_L64P_SCP5_0 |BIDIR |PCI33_3 |0 | | | |NONE | |LOCATED |NO |NONE |
|
||||
|P118 |SRAM_D<1> |IOB |IO_L63N_SCP6_0 |BIDIR |PCI33_3 |0 | | | |NONE | |LOCATED |NO |NONE |
|
||||
|P119 |SRAM_D<0> |IOB |IO_L63P_SCP7_0 |BIDIR |PCI33_3 |0 | | | |NONE | |LOCATED |NO |NONE |
|
||||
|P120 |LED<4> |IOB |IO_L62N_VREF_0 |OUTPUT |PCI33_3 |0 | | | | | |LOCATED |NO |NONE |
|
||||
|P121 |LED<5> |IOB |IO_L62P_0 |OUTPUT |PCI33_3 |0 | | | | | |LOCATED |NO |NONE |
|
||||
|P122 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|
||||
|P123 |SRAM_A<3> |IOB |IO_L37N_GCLK12_0 |OUTPUT |PCI33_3 |0 | | | | | |LOCATED |NO |NONE |
|
||||
|P124 |SRAM_A<2> |IOB |IO_L37P_GCLK13_0 |OUTPUT |PCI33_3 |0 | | | | | |LOCATED |NO |NONE |
|
||||
|P125 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|
||||
|P126 |SRAM_A<1> |IOB |IO_L36N_GCLK14_0 |OUTPUT |PCI33_3 |0 | | | | | |LOCATED |NO |NONE |
|
||||
|P127 |LED<6> |IOB |IO_L36P_GCLK15_0 |OUTPUT |PCI33_3 |0 | | | | | |LOCATED |NO |NONE |
|
||||
|P128 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|P129 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|P130 | | |GND | | | | | | | | | | | |
|
||||
|P131 |LED<7> |IOB |IO_L35N_GCLK16_0 |OUTPUT |PCI33_3 |0 | | | | | |LOCATED |NO |NONE |
|
||||
|P132 |SRAM_A<0> |IOB |IO_L35P_GCLK17_0 |OUTPUT |PCI33_3 |0 | | | | | |LOCATED |NO |NONE |
|
||||
|P133 | |IOBS |IO_L34N_GCLK18_0 |UNUSED | |0 | | | | | | | | |
|
||||
|P134 | |IOBM |IO_L34P_GCLK19_0 |UNUSED | |0 | | | | | | | | |
|
||||
|P135 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|
||||
|P136 | | |GND | | | | | | | | | | | |
|
||||
|P137 | |IOBS |IO_L4N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|P138 | |IOBM |IO_L4P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|P139 | |IOBS |IO_L3N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|P140 | |IOBM |IO_L3P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|P141 | |IOBS |IO_L2N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|P142 |A14 |IOB |IO_L2P_0 |OUTPUT |PCI33_3 |0 | | | | | |LOCATED |YES |NONE |
|
||||
|P143 |A15 |IOB |IO_L1N_VREF_0 |OUTPUT |PCI33_3 |0 | | | | | |LOCATED |YES |NONE |
|
||||
|P144 | |IOBM |IO_L1P_HSWAPEN_0 |UNUSED | |0 | | | | | | | | |
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
* Default value.
|
||||
** This default Pullup/Pulldown value can be overridden in Bitgen.
|
||||
****** Special VCCO requirements may apply. Please consult the device
|
||||
family datasheet for specific guideline on VCCO requirements.
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,502 @@
|
|||
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>MCL86jr Project Status (11/11/2020 - 19:12:10)</B></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
|
||||
<TD>MCL86jr.xise</TD>
|
||||
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
|
||||
<TD> No Errors </TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
|
||||
<TD>MCL86jr</TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
|
||||
<TD>Programming File Generated</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
|
||||
<TD>xc6slx9-3tqg144</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
|
||||
<TD>
|
||||
No Errors</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
|
||||
<TD ALIGN=LEFT><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/*.xmsgs?&DataKey=Warning'>60 Warnings (0 new)</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
|
||||
<TD>Balanced</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
|
||||
<TD>
|
||||
<A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr.unroutes'>All Signals Completely Routed</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
|
||||
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
|
||||
<TD>
|
||||
<A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
|
||||
<TD>
|
||||
<A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr_envsettings.html'>
|
||||
System Settings</A>
|
||||
</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
|
||||
<TD>0 <A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
|
||||
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
|
||||
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
|
||||
<TD ALIGN=RIGHT>853</TD>
|
||||
<TD ALIGN=RIGHT>11,440</TD>
|
||||
<TD ALIGN=RIGHT>7%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Flip Flops</TD>
|
||||
<TD ALIGN=RIGHT>853</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latches</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latch-thrus</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as AND/OR logics</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
|
||||
<TD ALIGN=RIGHT>959</TD>
|
||||
<TD ALIGN=RIGHT>5,720</TD>
|
||||
<TD ALIGN=RIGHT>16%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD>
|
||||
<TD ALIGN=RIGHT>887</TD>
|
||||
<TD ALIGN=RIGHT>5,720</TD>
|
||||
<TD ALIGN=RIGHT>15%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD>
|
||||
<TD ALIGN=RIGHT>681</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD>
|
||||
<TD ALIGN=RIGHT>54</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD>
|
||||
<TD ALIGN=RIGHT>152</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ROM</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Memory</TD>
|
||||
<TD ALIGN=RIGHT>58</TD>
|
||||
<TD ALIGN=RIGHT>1,440</TD>
|
||||
<TD ALIGN=RIGHT>4%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Dual Port RAM</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Single Port RAM</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Shift Register</TD>
|
||||
<TD ALIGN=RIGHT>58</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD>
|
||||
<TD ALIGN=RIGHT>2</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD>
|
||||
<TD ALIGN=RIGHT>56</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used exclusively as route-thrus</TD>
|
||||
<TD ALIGN=RIGHT>14</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice register load</TD>
|
||||
<TD ALIGN=RIGHT>8</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice carry load</TD>
|
||||
<TD ALIGN=RIGHT>6</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with other load</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
|
||||
<TD ALIGN=RIGHT>381</TD>
|
||||
<TD ALIGN=RIGHT>1,430</TD>
|
||||
<TD ALIGN=RIGHT>26%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MUXCYs used</TD>
|
||||
<TD ALIGN=RIGHT>196</TD>
|
||||
<TD ALIGN=RIGHT>2,860</TD>
|
||||
<TD ALIGN=RIGHT>6%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
|
||||
<TD ALIGN=RIGHT>1,197</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused Flip Flop</TD>
|
||||
<TD ALIGN=RIGHT>437</TD>
|
||||
<TD ALIGN=RIGHT>1,197</TD>
|
||||
<TD ALIGN=RIGHT>36%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused LUT</TD>
|
||||
<TD ALIGN=RIGHT>238</TD>
|
||||
<TD ALIGN=RIGHT>1,197</TD>
|
||||
<TD ALIGN=RIGHT>19%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of fully used LUT-FF pairs</TD>
|
||||
<TD ALIGN=RIGHT>522</TD>
|
||||
<TD ALIGN=RIGHT>1,197</TD>
|
||||
<TD ALIGN=RIGHT>43%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of unique control sets</TD>
|
||||
<TD ALIGN=RIGHT>40</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of slice register sites lost<BR> to control set restrictions</TD>
|
||||
<TD ALIGN=RIGHT>41</TD>
|
||||
<TD ALIGN=RIGHT>11,440</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
|
||||
<TD ALIGN=RIGHT>75</TD>
|
||||
<TD ALIGN=RIGHT>102</TD>
|
||||
<TD ALIGN=RIGHT>73%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of LOCed IOBs</TD>
|
||||
<TD ALIGN=RIGHT>75</TD>
|
||||
<TD ALIGN=RIGHT>75</TD>
|
||||
<TD ALIGN=RIGHT>100%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> IOB Flip Flops</TD>
|
||||
<TD ALIGN=RIGHT>39</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
|
||||
<TD ALIGN=RIGHT>7</TD>
|
||||
<TD ALIGN=RIGHT>32</TD>
|
||||
<TD ALIGN=RIGHT>21%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>64</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>32</TD>
|
||||
<TD ALIGN=RIGHT>3%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFIO2s</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFIO2_2CLKs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>32</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>16</TD>
|
||||
<TD ALIGN=RIGHT>6%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGs</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGMUX</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>4</TD>
|
||||
<TD ALIGN=RIGHT>25%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as DCMs</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as DCM_CLKGENs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
|
||||
<TD ALIGN=RIGHT>12</TD>
|
||||
<TD ALIGN=RIGHT>200</TD>
|
||||
<TD ALIGN=RIGHT>6%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ILOGIC2s</TD>
|
||||
<TD ALIGN=RIGHT>12</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ISERDES2s</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>200</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
|
||||
<TD ALIGN=RIGHT>27</TD>
|
||||
<TD ALIGN=RIGHT>200</TD>
|
||||
<TD ALIGN=RIGHT>13%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as OLOGIC2s</TD>
|
||||
<TD ALIGN=RIGHT>27</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as OSERDES2s</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>4</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>128</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>8</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>4</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>16</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>2</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>2</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>2</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
|
||||
<TD ALIGN=RIGHT>4.04</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
|
||||
<TD>0 (Setup: 0, Hold: 0, Component Switching Limit: 0)</TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
|
||||
<TD COLSPAN='2'><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
|
||||
<A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr.unroutes'>All Signals Completely Routed</A></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
|
||||
<TD COLSPAN='2'><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
|
||||
<TD>
|
||||
<A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B> </B></TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TABLE>
|
||||
|
||||
|
||||
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
|
||||
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Nov 11 19:10:14 2020</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/xst.xmsgs?&DataKey=Warning'>55 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/xst.xmsgs?&DataKey=Info'>4 Infos (2 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed Nov 11 19:10:21 2020</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/ngdbuild.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed Nov 11 19:10:57 2020</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/map.xmsgs?&DataKey=Warning'>2 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/map.xmsgs?&DataKey=Info'>8 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed Nov 11 19:11:34 2020</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/par.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Wed Nov 11 19:11:41 2020</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/trce.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Wed Nov 11 19:11:55 2020</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/bitgen.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
|
||||
</TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr_map.psr'>Physical Synthesis Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Nov 11 19:10:57 2020</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Nov 11 19:11:55 2020</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Nov 11 19:12:10 2020</TD></TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
<br><center><b>Date Generated:</b> 11/11/2020 - 19:12:11</center>
|
||||
</BODY></HTML>
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<DesignSummary rev="208">
|
||||
<CmdHistory>
|
||||
</CmdHistory>
|
||||
</DesignSummary>
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,65 @@
|
|||
Creating log file C:\MCL\MCL86\MCL86jr\MCL86jr\MCL86jr_xpa.log.
|
||||
Loading device for application Rf_Device from file '6slx9.nph' in environment
|
||||
C:\Xilinx\14.7\ISE_DS\ISE\.
|
||||
"MCL86jr" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -3
|
||||
|
||||
INFO:Power:1693 -
|
||||
--------------------------------------------------------------
|
||||
The power estimate will be calculated using PRODUCTION
|
||||
data.
|
||||
--------------------------------------------------------------
|
||||
|
||||
Design load 20% complete
Design load 25% complete
Design load 30% complete
Design load 60% complete
Design load 95% complete
Design load 100% complete
Running Vector-less Activity Propagation
|
||||
........
|
||||
Finished Running Vector-less Activity Propagation
|
||||
Finished Running Vector-less Activity Propagation 0 secs
|
||||
|
||||
Design 'MCL86jr.ncd' and constraints 'MCL86jr.pcf' opened successfully
|
||||
|
||||
|
||||
Updating power analysis...
|
||||
WARNING:Power:91 - Can't change frequency of net BIU_CORE/RESET_INT_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0848_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0852_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0856_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0860_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0864_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0866_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0869_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0873_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0877_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0881_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0885_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0888_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0896_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0904_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0909_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net BIU_CORE/biu_state[7]_GND_10_o_equal_153_o to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net BIU_CORE/biu_state[7]_GND_10_o_equal_155_o to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1079_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1083_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1087_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1091_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1095_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1099_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1103_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1107_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1111_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1115_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1119_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1123_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1127_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1131_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1135_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1156<0>2 to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1156_inv to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net EU_CORE/eu_stall_pipeline_eu_opcode_type[2]_AND_112_o to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net EU_CORE/eu_stall_pipeline_eu_opcode_type[2]_AND_114_o to 1.00Mhz.
|
||||
WARNING:Power:91 - Can't change frequency of net X245_DIR_OBUF to 1.00Mhz.
|
||||
WARNING:Power:90 - Can't change activity rate of net t_reset_d4 to 1.0% of CORE_CLK_BUFGP.
|
||||
WARNING:Power:91 - Can't change frequency of net t_reset_d4/t_reset_d4_rstpot to 1.00Mhz.
|
||||
Running Vector-less Activity Propagation
|
||||
........
|
||||
Finished Running Vector-less Activity Propagation
|
||||
Finished Running Vector-less Activity Propagation 0 secs
|
||||
Update Power Analysis is complete.
|
||||
|
|
@ -0,0 +1,260 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<document OS="nt64" product="ISE" version="14.7">
|
||||
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Xst" timeStamp="Wed Nov 11 19:09:58 2020">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
<column stringID="value"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="variable" value="Path"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ProgramData\Oracle\Java\javapath;C:\Program Files (x86)\SemanticDesigns\DMS\Executables;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\Intel\WiFi\bin\;C:\Program Files\Common Files\Intel\WirelessCommon\;C:\altera_lite\15.1\modelsim_ase\win32aloem;C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem"/>
|
||||
</row>
|
||||
<row stringID="row" value="1">
|
||||
<item stringID="variable" value="PATHEXT"/>
|
||||
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item stringID="variable" value="XILINX"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\"/>
|
||||
</row>
|
||||
<row stringID="row" value="3">
|
||||
<item stringID="variable" value="XILINX_DSP"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE"/>
|
||||
</row>
|
||||
<row stringID="row" value="4">
|
||||
<item stringID="variable" value="XILINX_EDK"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\EDK"/>
|
||||
</row>
|
||||
<row stringID="row" value="5">
|
||||
<item stringID="variable" value="XILINX_PLANAHEAD"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\PlanAhead"/>
|
||||
</row>
|
||||
</table>
|
||||
<item stringID="User_EnvOs" value="OS Information">
|
||||
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
|
||||
<item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/>
|
||||
</item>
|
||||
<item stringID="User_EnvHost" value="MicroCoreLabs"/>
|
||||
<table stringID="User_EnvCpu">
|
||||
<column stringID="arch"/>
|
||||
<column stringID="speed"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="arch" value="Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz"/>
|
||||
<item stringID="speed" value="2492 MHz"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
<section stringID="XST_OPTION_SUMMARY">
|
||||
<item DEFAULT="" label="-ifn" stringID="XST_IFN" value="MCL86jr.prj"/>
|
||||
<item DEFAULT="" label="-ofn" stringID="XST_OFN" value="MCL86jr"/>
|
||||
<item DEFAULT="NGC" label="-ofmt" stringID="XST_OFMT" value="NGC"/>
|
||||
<item DEFAULT="" label="-p" stringID="XST_P" value="xc6slx9-3-tqg144"/>
|
||||
<item DEFAULT="" label="-top" stringID="XST_TOP" value="MCL86jr"/>
|
||||
<item DEFAULT="Speed" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/>
|
||||
<item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/>
|
||||
<item DEFAULT="No" label="-power" stringID="XST_POWER" value="NO"/>
|
||||
<item DEFAULT="No" label="-iuc" stringID="XST_IUC" value="NO"/>
|
||||
<item DEFAULT="No" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="No"/>
|
||||
<item DEFAULT="As_Optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/>
|
||||
<item DEFAULT="No" label="-rtlview" stringID="XST_RTLVIEW" value="Yes"/>
|
||||
<item DEFAULT="AllClockNets" label="-glob_opt" stringID="XST_GLOBOPT" value="AllClockNets"/>
|
||||
<item DEFAULT="Yes" label="-read_cores" stringID="XST_READCORES" value="YES"/>
|
||||
<item DEFAULT="" label="-sd" stringID="XST_SD" value="{"ipcore_dir" }"/>
|
||||
<item DEFAULT="No" label="-write_timing_constraints" stringID="XST_WRITETIMINGCONSTRAINTS" value="NO"/>
|
||||
<item DEFAULT="No" label="-cross_clock_analysis" stringID="XST_CROSSCLOCKANALYSIS" value="NO"/>
|
||||
<item DEFAULT="/" stringID="XST_HIERARCHYSEPARATOR" value="/"/>
|
||||
<item DEFAULT="<>" label="-bus_delimiter" stringID="XST_BUSDELIMITER" value="<>"/>
|
||||
<item DEFAULT="Maintain" stringID="XST_CASE" value="Maintain"/>
|
||||
<item DEFAULT="100" label="-slice_utilization_ratio" stringID="XST_SLICEUTILIZATIONRATIO" value="100"/>
|
||||
<item DEFAULT="100" label="-bram_utilization_ratio" stringID="XST_BRAMUTILIZATIONRATIO" value="100"/>
|
||||
<item DEFAULT="100" label="-dsp_utilization_ratio" stringID="XST_DSPUTILIZATIONRATIO" value="100"/>
|
||||
<item DEFAULT="Auto" stringID="XST_LC" value="Auto"/>
|
||||
<item DEFAULT="Auto" label="-reduce_control_sets" stringID="XST_REDUCECONTROLSETS" value="Auto"/>
|
||||
<item DEFAULT="Yes" label="-fsm_extract" stringID="XST_FSMEXTRACT" value="YES"/>
|
||||
<item DEFAULT="Auto" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Auto"/>
|
||||
<item DEFAULT="No" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="No"/>
|
||||
<item DEFAULT="LUT" label="-fsm_style" stringID="XST_FSMSTYLE" value="LUT"/>
|
||||
<item DEFAULT="Yes" label="-ram_extract" stringID="XST_RAMEXTRACT" value="Yes"/>
|
||||
<item DEFAULT="Auto" label="-ram_style" stringID="XST_RAMSTYLE" value="Auto"/>
|
||||
<item DEFAULT="Yes" label="-rom_extract" stringID="XST_ROMEXTRACT" value="Yes"/>
|
||||
<item DEFAULT="Yes" label="-shreg_extract" stringID="XST_SHREGEXTRACT" value="YES"/>
|
||||
<item DEFAULT="Auto" label="-rom_style" stringID="XST_ROMSTYLE" value="Auto"/>
|
||||
<item DEFAULT="No" label="-auto_bram_packing" stringID="XST_AUTOBRAMPACKING" value="NO"/>
|
||||
<item DEFAULT="Yes" label="-resource_sharing" stringID="XST_RESOURCESHARING" value="YES"/>
|
||||
<item DEFAULT="No" label="-async_to_sync" stringID="XST_ASYNCTOSYNC" value="NO"/>
|
||||
<item DEFAULT="2" stringID="XST_SHREGMINSIZE" value="2"/>
|
||||
<item DEFAULT="Auto" label="-use_dsp48" stringID="XST_USEDSP48" value="Auto"/>
|
||||
<item DEFAULT="Yes" label="-iobuf" stringID="XST_IOBUF" value="YES"/>
|
||||
<item DEFAULT="100000" label="-max_fanout" stringID="XST_MAXFANOUT" value="100000"/>
|
||||
<item DEFAULT="16" label="-bufg" stringID="XST_BUFG" value="16"/>
|
||||
<item DEFAULT="Yes" label="-register_duplication" stringID="XST_REGISTERDUPLICATION" value="YES"/>
|
||||
<item DEFAULT="No" label="-register_balancing" stringID="XST_REGISTERBALANCING" value="No"/>
|
||||
<item DEFAULT="No" label="-optimize_primitives" stringID="XST_OPTIMIZEPRIMITIVES" value="NO"/>
|
||||
<item DEFAULT="Auto" label="-use_clock_enable" stringID="XST_USECLOCKENABLE" value="Auto"/>
|
||||
<item DEFAULT="Auto" label="-use_sync_set" stringID="XST_USESYNCSET" value="Auto"/>
|
||||
<item DEFAULT="Auto" label="-use_sync_reset" stringID="XST_USESYNCRESET" value="Auto"/>
|
||||
<item DEFAULT="Auto" label="-iob" stringID="XST_IOB" value="Auto"/>
|
||||
<item DEFAULT="Yes" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
|
||||
<item DEFAULT="0" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/>
|
||||
</section>
|
||||
<section stringID="XST_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="XST_NUM_BUFG" value="1"/>
|
||||
<item dataType="int" stringID="XST_NUM_IBUFG" value="1"/>
|
||||
</section>
|
||||
<section stringID="XST_HDL_SYNTHESIS_REPORT">
|
||||
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="12">
|
||||
<item dataType="int" stringID="XST_16BIT_ADDER" value="3"/>
|
||||
<item dataType="int" stringID="XST_8BIT_ADDER" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="129">
|
||||
<item dataType="int" stringID="XST_1BIT_REGISTER" value="68"/>
|
||||
<item dataType="int" stringID="XST_16BIT_REGISTER" value="41"/>
|
||||
<item dataType="int" stringID="XST_19BIT_REGISTER" value="1"/>
|
||||
<item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
|
||||
<item dataType="int" stringID="XST_8BIT_REGISTER" value="10"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COMPARATORS" value="4">
|
||||
<item dataType="int" stringID="XST_1BIT_COMPARATOR_EQUAL" value="1"/>
|
||||
<item dataType="int" stringID="XST_2BIT_COMPARATOR_EQUAL" value="1"/>
|
||||
<item dataType="int" stringID="XST_4BIT_COMPARATOR_GREATER" value="2"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_MULTIPLEXERS" value="156">
|
||||
<item dataType="int" stringID="XST_1BIT_2TO1_MULTIPLEXER" value="118"/>
|
||||
<item dataType="int" stringID="XST_16BIT_2TO1_MULTIPLEXER" value="3"/>
|
||||
<item dataType="int" stringID="XST_16BIT_4TO1_MULTIPLEXER" value="1"/>
|
||||
<item dataType="int" stringID="XST_2BIT_2TO1_MULTIPLEXER" value="1"/>
|
||||
<item dataType="int" stringID="XST_3BIT_2TO1_MULTIPLEXER" value="1"/>
|
||||
<item dataType="int" stringID="XST_8BIT_2TO1_MULTIPLEXER" value="14"/>
|
||||
<item dataType="int" stringID="XST_8BIT_4TO1_MULTIPLEXER" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_TRISTATES" value="16">
|
||||
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="16"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_XORS" value="20">
|
||||
<item dataType="int" stringID="XST_1BIT_XOR2" value="2"/>
|
||||
<item dataType="int" stringID="XST_1BIT_XOR3" value="16"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
|
||||
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="7">
|
||||
<item dataType="int" stringID="XST_16BIT_ADDER" value="1"/>
|
||||
<item dataType="int" stringID="XST_8BIT_ADDER" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COUNTERS" value="5"></item>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="913">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="913"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COMPARATORS" value="4">
|
||||
<item dataType="int" stringID="XST_1BIT_COMPARATOR_EQUAL" value="1"/>
|
||||
<item dataType="int" stringID="XST_2BIT_COMPARATOR_EQUAL" value="1"/>
|
||||
<item dataType="int" stringID="XST_4BIT_COMPARATOR_GREATER" value="2"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_MULTIPLEXERS" value="209">
|
||||
<item dataType="int" stringID="XST_1BIT_2TO1_MULTIPLEXER" value="131"/>
|
||||
<item dataType="int" stringID="XST_1BIT_4TO1_MULTIPLEXER" value="16"/>
|
||||
<item dataType="int" stringID="XST_16BIT_2TO1_MULTIPLEXER" value="1"/>
|
||||
<item dataType="int" stringID="XST_2BIT_2TO1_MULTIPLEXER" value="1"/>
|
||||
<item dataType="int" stringID="XST_3BIT_2TO1_MULTIPLEXER" value="1"/>
|
||||
<item dataType="int" stringID="XST_8BIT_2TO1_MULTIPLEXER" value="14"/>
|
||||
<item dataType="int" stringID="XST_8BIT_4TO1_MULTIPLEXER" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_XORS" value="20">
|
||||
<item dataType="int" stringID="XST_1BIT_XOR2" value="2"/>
|
||||
<item dataType="int" stringID="XST_1BIT_XOR3" value="16"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="XST_FINAL_REGISTER_REPORT">
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="777">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="777"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_SHIFT_REGISTERS" value="114">
|
||||
<item dataType="int" stringID="XST_2BIT_SHIFT_REGISTER" value="114"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="XST_PARTITION_REPORT">
|
||||
<section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
|
||||
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="XST_DESIGN_SUMMARY">
|
||||
<section stringID="XST_">
|
||||
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="MCL86jr.ngc"/>
|
||||
</section>
|
||||
<section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
|
||||
<item dataType="int" stringID="XST_BELS" value="1407">
|
||||
<item dataType="int" stringID="XST_GND" value="2"/>
|
||||
<item dataType="int" stringID="XST_INV" value="15"/>
|
||||
<item dataType="int" stringID="XST_LUT1" value="60"/>
|
||||
<item dataType="int" stringID="XST_LUT2" value="87"/>
|
||||
<item dataType="int" stringID="XST_LUT3" value="116"/>
|
||||
<item dataType="int" stringID="XST_LUT4" value="73"/>
|
||||
<item dataType="int" stringID="XST_LUT5" value="223"/>
|
||||
<item dataType="int" stringID="XST_LUT6" value="384"/>
|
||||
<item dataType="int" stringID="XST_MUXCY" value="175"/>
|
||||
<item dataType="int" stringID="XST_MUXF7" value="59"/>
|
||||
<item dataType="int" stringID="XST_MUXF8" value="25"/>
|
||||
<item dataType="int" stringID="XST_VCC" value="2"/>
|
||||
<item dataType="int" stringID="XST_XORCY" value="186"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="892">
|
||||
<item dataType="int" stringID="XST_FD" value="48"/>
|
||||
<item dataType="int" stringID="XST_FDE" value="183"/>
|
||||
<item dataType="int" stringID="XST_FDR" value="125"/>
|
||||
<item dataType="int" stringID="XST_FDRE" value="503"/>
|
||||
<item dataType="int" stringID="XST_FDS" value="13"/>
|
||||
<item dataType="int" stringID="XST_FDSE" value="20"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_RAMS" value="8">
|
||||
<item dataType="int" stringID="XST_RAMB16BWER" value="7"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_SHIFT_REGISTERS" value="114">
|
||||
<item dataType="int" stringID="XST_SRLC16E" value="114"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="1">
|
||||
<item dataType="int" label="-bufg" stringID="XST_BUFG" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_IO_BUFFERS" value="75">
|
||||
<item dataType="int" stringID="XST_IBUF" value="5"/>
|
||||
<item dataType="int" stringID="XST_IBUFG" value="1"/>
|
||||
<item dataType="int" label="-iobuf" stringID="XST_IOBUF" value="16"/>
|
||||
<item dataType="int" stringID="XST_OBUF" value="53"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_DCMS" value="1">
|
||||
<item dataType="int" stringID="XST_DCMSP" value="1"/>
|
||||
</item>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
|
||||
<item stringID="XST_SELECTED_DEVICE" value="6slx9tqg144-3"/>
|
||||
<item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="892"/>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="1072"/>
|
||||
<item AVAILABLE="5720" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="958"/>
|
||||
<item AVAILABLE="1440" dataType="int" stringID="XST_NUMBER_USED_AS_MEMORY" value="114"/>
|
||||
<item dataType="int" stringID="XST_NUMBER_USED_AS_SRL" value="114"/>
|
||||
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="1452"/>
|
||||
<item AVAILABLE="1452" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="560"/>
|
||||
<item AVAILABLE="1452" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="380"/>
|
||||
<item AVAILABLE="1452" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="512"/>
|
||||
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="41"/>
|
||||
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="75"/>
|
||||
<item AVAILABLE="102" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="75"/>
|
||||
<item AVAILABLE="32" dataType="int" label="Number of Block RAM/FIFO" stringID="XST_NUMBER_OF_BLOCK_RAMFIFO" value="8"/>
|
||||
<item dataType="int" label="Number using Block RAM only" stringID="XST_NUMBER_USING_BLOCK_RAM_ONLY" value="8"/>
|
||||
<item AVAILABLE="16" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="1"/>
|
||||
</section>
|
||||
<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
|
||||
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
|
||||
</section>
|
||||
<section stringID="XST_ERRORS_STATISTICS">
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="55"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="4"/>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
</document>
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
setMode -bs
|
||||
setMode -ss
|
||||
setMode -sm
|
||||
setMode -hw140
|
||||
setMode -spi
|
||||
setMode -acecf
|
||||
setMode -acempm
|
||||
setMode -pff
|
||||
loadProjectFile -file "C:\MCL\MCL86\MCL86jr\MCL86jr_Impact.ipf"
|
||||
setMode -ss
|
||||
setMode -sm
|
||||
setMode -hw140
|
||||
setMode -spi
|
||||
setMode -acecf
|
||||
setMode -acempm
|
||||
setMode -pff
|
||||
setMode -bs
|
||||
setMode -pff
|
||||
setMode -pff
|
||||
setMode -pff
|
||||
setMode -pff
|
||||
setMode -pff
|
||||
setCurrentDesign -version 0
|
||||
setMode -pff
|
||||
setCurrentDeviceChain -index 0
|
||||
setMode -bs
|
||||
setMode -bs
|
||||
setMode -bs
|
||||
setMode -bs
|
||||
setCable -port auto
|
||||
Identify -inferir
|
||||
identifyMPM
|
||||
assignFile -p 1 -file "C:/MCL/MCL86/MCL86jr/MCL86jr/mcl86jr.bit"
|
||||
Program -p 1
|
||||
attachflash -position 1 -spi "W25Q128FV"
|
||||
assignfiletoattachedflash -position 1 -file "C:/MCL/MCL86/MCL86jr/Untitled.mcs"
|
||||
setMode -bs
|
||||
deleteDevice -position 1
|
||||
setMode -bs
|
||||
setMode -ss
|
||||
setMode -sm
|
||||
setMode -hw140
|
||||
setMode -spi
|
||||
setMode -acecf
|
||||
setMode -acempm
|
||||
setMode -pff
|
||||
loadProjectFile -file "C:\MCL\MCL86\MCL86jr\MCL86jr_Impact.ipf"
|
||||
setMode -ss
|
||||
setMode -sm
|
||||
setMode -hw140
|
||||
setMode -spi
|
||||
setMode -acecf
|
||||
setMode -acempm
|
||||
setMode -pff
|
||||
setMode -bs
|
||||
setMode -pff
|
||||
setMode -pff
|
||||
setMode -pff
|
||||
setMode -pff
|
||||
setMode -pff
|
||||
setCurrentDesign -version 0
|
||||
setMode -pff
|
||||
setCurrentDeviceChain -index 0
|
||||
setSubmode -pffspi
|
||||
setMode -pff
|
||||
setMode -bs
|
||||
setMode -pff
|
||||
setSubmode -pffspi
|
||||
setSubmode -pffspi
|
||||
setMode -bs
|
||||
setMode -bs
|
||||
setMode -bs
|
||||
setMode -pff
|
||||
setSubmode -pffspi
|
||||
setSubmode -pffspi
|
||||
setMode -pff
|
||||
setSubmode -pffspi
|
||||
generate
|
||||
setCurrentDesign -version 0
|
||||
setMode -bs
|
||||
setMode -bs
|
||||
setMode -bs
|
||||
setMode -pff
|
||||
setSubmode -pffspi
|
||||
setSubmode -pffspi
|
||||
setMode -bs
|
||||
setMode -bs
|
||||
setMode -bs
|
||||
setMode -pff
|
||||
setSubmode -pffspi
|
||||
setSubmode -pffspi
|
||||
setMode -bs
|
||||
setMode -bs
|
||||
setMode -bs
|
||||
setCable -port auto
|
||||
Identify -inferir
|
||||
identifyMPM
|
||||
attachflash -position 1 -spi "W25Q128FV"
|
||||
assignfiletoattachedflash -position 1 -file "C:/MCL/MCL86/MCL86jr/Untitled.mcs"
|
||||
setMode -bs
|
||||
setMode -bs
|
||||
setMode -ss
|
||||
setMode -sm
|
||||
setMode -hw140
|
||||
setMode -spi
|
||||
setMode -acecf
|
||||
setMode -acempm
|
||||
setMode -pff
|
||||
setMode -bs
|
||||
saveProjectFile -file "C:\MCL\MCL86\MCL86jr\MCL86jr_Impact.ipf"
|
||||
Program -p 1 -dataWidth 1 -spionly -e -v -loadfpga
|
||||
setMode -bs
|
||||
setMode -bs
|
||||
setMode -ss
|
||||
setMode -sm
|
||||
setMode -hw140
|
||||
setMode -spi
|
||||
setMode -acecf
|
||||
setMode -acempm
|
||||
setMode -pff
|
||||
setMode -bs
|
||||
saveProjectFile -file "C:\MCL\MCL86\MCL86jr\MCL86jr_Impact.ipf"
|
||||
setMode -bs
|
||||
setMode -bs
|
||||
setMode -ss
|
||||
setMode -sm
|
||||
setMode -hw140
|
||||
setMode -spi
|
||||
setMode -acecf
|
||||
setMode -acempm
|
||||
setMode -pff
|
||||
setMode -bs
|
||||
saveProjectFile -file "C:\MCL\MCL86\MCL86jr\MCL86jr_Impact.ipf"
|
||||
setMode -bs
|
||||
setMode -pff
|
||||
setMode -bs
|
||||
deleteDevice -position 1
|
||||
setMode -bs
|
||||
setMode -ss
|
||||
setMode -sm
|
||||
setMode -hw140
|
||||
setMode -spi
|
||||
setMode -acecf
|
||||
setMode -acempm
|
||||
setMode -pff
|
||||
deletePromDevice -position 1
|
||||
setCurrentDesign -version 0
|
||||
deleteDevice -position 1
|
||||
deleteDesign -version 0
|
||||
setCurrentDesign -version -1
|
||||
|
|
@ -0,0 +1,330 @@
|
|||
iMPACT Version: 14.7
|
||||
|
||||
iMPACT log file Started on Sat Nov 07 21:58:06 2020
|
||||
|
||||
Welcome to iMPACT
|
||||
iMPACT Version: 14.7
|
||||
// *** BATCH CMD : setMode -bs
|
||||
// *** BATCH CMD : setMode -ss
|
||||
// *** BATCH CMD : setMode -sm
|
||||
// *** BATCH CMD : setMode -hw140
|
||||
// *** BATCH CMD : setMode -spi
|
||||
// *** BATCH CMD : setMode -acecf
|
||||
// *** BATCH CMD : setMode -acempm
|
||||
// *** BATCH CMD : setMode -pff
|
||||
// *** BATCH CMD : loadProjectFile -file"C:\MCL\MCL86\MCL86jr\MCL86jr_Impact.ipf"
|
||||
'1': Loading file 'C:\MCL\MCL86\MCL86jr\MCL86jr\mcl86jr.bit' ...
|
||||
INFO:iMPACT - Elapsed time = 0 sec.
|
||||
done.
|
||||
INFO:iMPACT:501 - '1': Added Device xc6slx9 successfully.
|
||||
----------------------------------------------------------------------
|
||||
'1': Added Device 16M successfully.
|
||||
----------------------------------------------------------------------
|
||||
Active mode is BS
|
||||
// *** BATCH CMD : setMode -ss
|
||||
// *** BATCH CMD : setMode -sm
|
||||
// *** BATCH CMD : setMode -hw140
|
||||
// *** BATCH CMD : setMode -spi
|
||||
// *** BATCH CMD : setMode -acecf
|
||||
// *** BATCH CMD : setMode -acempm
|
||||
// *** BATCH CMD : setMode -pff
|
||||
// *** BATCH CMD : setMode -bs
|
||||
// *** BATCH CMD : setMode -pff
|
||||
// *** BATCH CMD : setCurrentDesign -version 0
|
||||
// *** BATCH CMD : setMode -pff
|
||||
// *** BATCH CMD : setCurrentDeviceChain -index 0
|
||||
// *** BATCH CMD : setMode -bs
|
||||
GUI --- Auto connect to cable...
|
||||
// *** BATCH CMD : setCable -port auto
|
||||
AutoDetecting cable. Please wait.
|
||||
*** WARNING ***: When port is set to auto detect mode, cable speed is set todefault 6 MHz regardless of explicit arguments supplied for setting the baudrates
|
||||
PROGRESS_START - Starting Operation.
|
||||
Connecting to cable (Usb Port - USB21).
|
||||
Checking cable driver.
|
||||
Driver file xusb_xp2.sys found.
|
||||
Driver version: src=2301, dest=2301.
|
||||
Driver windrvr6.sys version = 10.2.1.0. WinDriver v10.21 Jungo (c) 1997 - 2010 Build Date: Aug 31 2010 x86_64 64bit SYS14:14:44, version = 1021.
|
||||
Cable PID = 0008.
|
||||
Max current requested during enumeration is 300 mA.
|
||||
Type = 0x0005.
|
||||
write (count, cmdBuffer, dataBuffer) failed C0000004.
|
||||
Cable Type = 3, Revision = 0.
|
||||
Setting cable speed to 6 MHz.
|
||||
Cable connection established.
|
||||
Firmware version = 2301.
|
||||
File version of C:/Xilinx/14.7/ISE_DS/ISE/data/xusb_xp2.hex = 2401.
|
||||
Firmware hex file version = 2401.
|
||||
Downloading C:/Xilinx/14.7/ISE_DS/ISE/data/xusb_xp2.hex.
|
||||
Downloaded firmware version = 2401.
|
||||
PLD file version = 200Dh.
|
||||
PLD version = 200Dh.
|
||||
PROGRESS_END - End Operation.
|
||||
Elapsed time = 1 sec.
|
||||
Type = 0x0005.
|
||||
ESN option: 0000149BE10901.
|
||||
Attempting to identify devices in the boundary-scan chain configuration...
|
||||
INFO:iMPACT - Current time: 11/7/2020 9:58:25 PM
|
||||
// *** BATCH CMD : Identify -inferir
|
||||
PROGRESS_START - Starting Operation.
|
||||
Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc6slx9, Version : 2
|
||||
INFO:iMPACT:1777 -
|
||||
Reading C:/Xilinx/14.7/ISE_DS/ISE/spartan6/data/xc6slx9.bsd...
|
||||
INFO:iMPACT:501 - '1': Added Device xc6slx9 successfully.
|
||||
----------------------------------------------------------------------
|
||||
done.
|
||||
PROGRESS_END - End Operation.
|
||||
Elapsed time = 0 sec.
|
||||
// *** BATCH CMD : identifyMPM
|
||||
// *** BATCH CMD : assignFile -p 1 -file"C:/MCL/MCL86/MCL86jr/MCL86jr/mcl86jr.bit"
|
||||
'1': Loading file 'C:/MCL/MCL86/MCL86jr/MCL86jr/mcl86jr.bit' ...
|
||||
done.
|
||||
INFO:iMPACT:2257 - Startup Clock has been changed to 'JtagClk' in the bitstream stored in memory,
|
||||
but the original bitstream file remains unchanged.
|
||||
UserID read from the bitstream file = 0xFFFFFFFF.
|
||||
Data width read from the bitstream file = 1.
|
||||
INFO:iMPACT:501 - '1': Added Device xc6slx9 successfully.
|
||||
----------------------------------------------------------------------
|
||||
INFO:iMPACT - Current time: 11/7/2020 9:59:04 PM
|
||||
// *** BATCH CMD : Program -p 1
|
||||
Maximum TCK operating frequency for this device chain: 25000000.
|
||||
Validating chain...
|
||||
Boundary-scan chain validated successfully.
|
||||
'1': Programming device...
|
||||
PROGRESS_START - Starting Operation.
|
||||
LCK_cycle = NoWait.
|
||||
LCK cycle: NoWait
|
||||
done.
|
||||
'1': Reading status register contents...
|
||||
[0] CRC ERROR : 0
|
||||
[1] IDCODE ERROR : 0
|
||||
[2] DCM LOCK STATUS : 1
|
||||
[3] GTS_CFG_B STATUS : 1
|
||||
[4] GWE STATUS : 1
|
||||
[5] GHIGH STATUS : 1
|
||||
[6] DECRYPTION ERROR : 0
|
||||
[7] DECRYPTOR ENABLE : 0
|
||||
[8] HSWAPEN PIN : 1
|
||||
[9] MODE PIN M[0] : 1
|
||||
[10] MODE PIN M[1] : 1
|
||||
[11] RESERVED : 0
|
||||
[12] INIT_B PIN : 1
|
||||
[13] DONE PIN : 1
|
||||
[14] SUSPEND STATUS : 0
|
||||
[15] FALLBACK STATUS : 0
|
||||
INFO:iMPACT:2219 - Status register values:
|
||||
INFO:iMPACT - 0011 1100 1110 1100
|
||||
INFO:iMPACT:579 - '1': Completed downloading bit file to device.
|
||||
INFO:iMPACT:188 - '1': Programming completed successfully.
|
||||
LCK_cycle = NoWait.
|
||||
LCK cycle: NoWait
|
||||
INFO:iMPACT - '1': Checking done pin....done.
|
||||
'1': Programmed successfully.
|
||||
PROGRESS_END - End Operation.
|
||||
Elapsed time = 1 sec.
|
||||
Selected part: W25Q128FV
|
||||
// *** BATCH CMD : attachflash -position 1 -spi "W25Q128FV"
|
||||
Unprotect sectors: FALSE
|
||||
// *** BATCH CMD : assignfiletoattachedflash -position 1 -file"C:/MCL/MCL86/MCL86jr/Untitled.mcs"
|
||||
// *** BATCH CMD : setMode -bs
|
||||
// *** BATCH CMD : deleteDevice -position 1
|
||||
// *** BATCH CMD : setMode -bs
|
||||
// *** BATCH CMD : setMode -ss
|
||||
// *** BATCH CMD : setMode -sm
|
||||
// *** BATCH CMD : setMode -hw140
|
||||
// *** BATCH CMD : setMode -spi
|
||||
// *** BATCH CMD : setMode -acecf
|
||||
// *** BATCH CMD : setMode -acempm
|
||||
// *** BATCH CMD : setMode -pff
|
||||
// *** BATCH CMD : loadProjectFile -file"C:\MCL\MCL86\MCL86jr\MCL86jr_Impact.ipf"
|
||||
'1': Loading file 'C:\MCL\MCL86\MCL86jr\MCL86jr\mcl86jr.bit' ...
|
||||
INFO:iMPACT - Elapsed time = 0 sec.
|
||||
done.
|
||||
INFO:iMPACT:501 - '1': Added Device xc6slx9 successfully.
|
||||
----------------------------------------------------------------------
|
||||
'1': Added Device 16M successfully.
|
||||
----------------------------------------------------------------------
|
||||
Active mode is BS
|
||||
// *** BATCH CMD : setMode -ss
|
||||
// *** BATCH CMD : setMode -sm
|
||||
// *** BATCH CMD : setMode -hw140
|
||||
// *** BATCH CMD : setMode -spi
|
||||
// *** BATCH CMD : setMode -acecf
|
||||
// *** BATCH CMD : setMode -acempm
|
||||
// *** BATCH CMD : setMode -pff
|
||||
// *** BATCH CMD : setMode -bs
|
||||
// *** BATCH CMD : setMode -pff
|
||||
// *** BATCH CMD : setCurrentDesign -version 0
|
||||
// *** BATCH CMD : setMode -pff
|
||||
// *** BATCH CMD : setCurrentDeviceChain -index 0
|
||||
// *** BATCH CMD : setSubmode -pffspi
|
||||
// *** BATCH CMD : setMode -pff
|
||||
------------------------ GUI: Wizard Data Report ---------------------------
|
||||
Compression : false
|
||||
Fill Value : FF
|
||||
Output Format : mcs
|
||||
Swap Bits : false
|
||||
LoadDirection : UP
|
||||
PROM Basename : Untitled
|
||||
File Location : C:\MCL\MCL86\MCL86jr/
|
||||
Auto Select : false
|
||||
Number of Revisions : 1
|
||||
Number of PROMs : 1
|
||||
PROM Name : 16M PROM Size : 16777216 bits
|
||||
------ Revision: 0 '0', 1 device(s) chain -----
|
||||
Device 0, pn=xc6slx9 fn=mcl86jr.bit
|
||||
-------------------------- END of Report ----------------------------
|
||||
// *** BATCH CMD : setMode -bs
|
||||
// *** BATCH CMD : setMode -pff
|
||||
// *** BATCH CMD : setSubmode -pffspi
|
||||
// *** BATCH CMD : setMode -bs
|
||||
// *** BATCH CMD : setMode -pff
|
||||
// *** BATCH CMD : setSubmode -pffspi
|
||||
INFO:iMPACT - Current time: 11/7/2020 10:00:53 PM
|
||||
// *** BATCH CMD : setMode -pff
|
||||
// *** BATCH CMD : setSubmode -pffspi
|
||||
Total configuration bit size = 2727072 bits.
|
||||
Total configuration byte size = 340884 bytes.
|
||||
// *** BATCH CMD : generate
|
||||
0x53394 (340884) bytes loaded up from 0x0
|
||||
Using user-specified prom size of 16384K
|
||||
Writing file "C:\MCL\MCL86\MCL86jr\Untitled.mcs".
|
||||
Writing file "C:\MCL\MCL86\MCL86jr\Untitled.prm".
|
||||
Writing file "C:\MCL\MCL86\MCL86jr\Untitled.cfi".
|
||||
// *** BATCH CMD : setCurrentDesign -version 0
|
||||
// *** BATCH CMD : setMode -bs
|
||||
// *** BATCH CMD : setMode -pff
|
||||
// *** BATCH CMD : setSubmode -pffspi
|
||||
// *** BATCH CMD : setMode -bs
|
||||
// *** BATCH CMD : setMode -pff
|
||||
// *** BATCH CMD : setSubmode -pffspi
|
||||
// *** BATCH CMD : setMode -bs
|
||||
GUI --- Auto connect to cable...
|
||||
// *** BATCH CMD : setCable -port auto
|
||||
AutoDetecting cable. Please wait.
|
||||
*** WARNING ***: When port is set to auto detect mode, cable speed is set todefault 6 MHz regardless of explicit arguments supplied for setting the baudrates
|
||||
PROGRESS_START - Starting Operation.
|
||||
Connecting to cable (Usb Port - USB21).
|
||||
Checking cable driver.
|
||||
Driver file xusb_xp2.sys found.
|
||||
Driver version: src=2301, dest=2301.
|
||||
Driver windrvr6.sys version = 10.2.1.0. WinDriver v10.21 Jungo (c) 1997 - 2010 Build Date: Aug 31 2010 x86_64 64bit SYS14:14:44, version = 1021.
|
||||
Cable PID = 0008.
|
||||
Max current requested during enumeration is 300 mA.
|
||||
Type = 0x0005.
|
||||
Cable Type = 3, Revision = 0.
|
||||
Setting cable speed to 6 MHz.
|
||||
Cable connection established.
|
||||
Firmware version = 2401.
|
||||
File version of C:/Xilinx/14.7/ISE_DS/ISE/data/xusb_xp2.hex = 2401.
|
||||
Firmware hex file version = 2401.
|
||||
PLD file version = 200Dh.
|
||||
PLD version = 200Dh.
|
||||
PROGRESS_END - End Operation.
|
||||
Elapsed time = 1 sec.
|
||||
Type = 0x0005.
|
||||
ESN option: 0000149BE10901.
|
||||
Attempting to identify devices in the boundary-scan chain configuration...
|
||||
INFO:iMPACT - Current time: 11/7/2020 10:01:13 PM
|
||||
// *** BATCH CMD : Identify -inferir
|
||||
PROGRESS_START - Starting Operation.
|
||||
Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc6slx9, Version : 2
|
||||
INFO:iMPACT:1777 -
|
||||
Reading C:/Xilinx/14.7/ISE_DS/ISE/spartan6/data/xc6slx9.bsd...
|
||||
INFO:iMPACT:501 - '1': Added Device xc6slx9 successfully.
|
||||
----------------------------------------------------------------------
|
||||
done.
|
||||
PROGRESS_END - End Operation.
|
||||
Elapsed time = 0 sec.
|
||||
// *** BATCH CMD : identifyMPM
|
||||
Selected part: W25Q128FV
|
||||
// *** BATCH CMD : attachflash -position 1 -spi "W25Q128FV"
|
||||
Unprotect sectors: FALSE
|
||||
// *** BATCH CMD : assignfiletoattachedflash -position 1 -file"C:/MCL/MCL86/MCL86jr/Untitled.mcs"
|
||||
// *** BATCH CMD : setMode -bs
|
||||
// *** BATCH CMD : setMode -ss
|
||||
// *** BATCH CMD : setMode -sm
|
||||
// *** BATCH CMD : setMode -hw140
|
||||
// *** BATCH CMD : setMode -spi
|
||||
// *** BATCH CMD : setMode -acecf
|
||||
// *** BATCH CMD : setMode -acempm
|
||||
// *** BATCH CMD : setMode -pff
|
||||
// *** BATCH CMD : setMode -bs
|
||||
// *** BATCH CMD : saveProjectFile -file"C:\MCL\MCL86\MCL86jr\MCL86jr_Impact.ipf"
|
||||
INFO:iMPACT - Current time: 11/7/2020 10:01:48 PM
|
||||
// *** BATCH CMD : Program -p 1 -dataWidth 1 -spionly -e -v -loadfpga
|
||||
Maximum TCK operating frequency for this device chain: 25000000.
|
||||
Validating chain...
|
||||
Boundary-scan chain validated successfully.
|
||||
'1': SPI access core not detected. SPI access core will be downloaded to thedevice to enable operations.
|
||||
INFO:iMPACT - Downloading core file C:/Xilinx/14.7/ISE_DS/ISE/spartan6/data/xc6slx9_spi.cor.
|
||||
PROGRESS_START - Starting Operation.
|
||||
'1': Downloading core...
|
||||
LCK_cycle = NoWait.
|
||||
LCK cycle: NoWait
|
||||
done.
|
||||
'1': Reading status register contents...
|
||||
INFO:iMPACT:2219 - Status register values:
|
||||
INFO:iMPACT - 0011 1100 1110 1100
|
||||
INFO:iMPACT:2492 - '1': Completed downloading core to device.
|
||||
'1': IDCODE is 'ef4018' (in hex).
|
||||
'1': ID Check passed.
|
||||
'1': IDCODE is 'ef4018' (in hex).
|
||||
'1': ID Check passed.
|
||||
'1': Erasing Device.
|
||||
'1': Using Bulk Erase.
|
||||
'1': Erasing non-volatile quad-enable bit...
|
||||
'1': Programming Flash.
|
||||
'1': Reading device contents...
|
||||
done.
|
||||
'1': Verification completed.
|
||||
'1':Programming in x1 mode.
|
||||
W25Q128FV Status Register Contents = 0x0200.
|
||||
STATUS REGISTER PROTECT 0 : 0
|
||||
SECTOR PROTECT : 0
|
||||
TOP/BOTTOM PROTECT : 0
|
||||
BLOCK PROTECT BIT 2 : 0
|
||||
BLOCK PROTECT BIT 1 : 0
|
||||
BLOCK PROTECT BIT 0 : 0
|
||||
'1': Configuration data download to FPGA was not successful. DONE did not gohigh, please check your configuration setup and mode settings.
|
||||
INFO:iMPACT - '1': Flash was not programmed successfully.
|
||||
PROGRESS_END - End Operation.
|
||||
Elapsed time = 141 sec.
|
||||
// *** BATCH CMD : setMode -bs
|
||||
// *** BATCH CMD : setMode -ss
|
||||
// *** BATCH CMD : setMode -sm
|
||||
// *** BATCH CMD : setMode -hw140
|
||||
// *** BATCH CMD : setMode -spi
|
||||
// *** BATCH CMD : setMode -acecf
|
||||
// *** BATCH CMD : setMode -acempm
|
||||
// *** BATCH CMD : setMode -pff
|
||||
// *** BATCH CMD : setMode -bs
|
||||
// *** BATCH CMD : saveProjectFile -file"C:\MCL\MCL86\MCL86jr\MCL86jr_Impact.ipf"
|
||||
// *** BATCH CMD : setMode -bs
|
||||
// *** BATCH CMD : setMode -ss
|
||||
// *** BATCH CMD : setMode -sm
|
||||
// *** BATCH CMD : setMode -hw140
|
||||
// *** BATCH CMD : setMode -spi
|
||||
// *** BATCH CMD : setMode -acecf
|
||||
// *** BATCH CMD : setMode -acempm
|
||||
// *** BATCH CMD : setMode -pff
|
||||
// *** BATCH CMD : setMode -bs
|
||||
// *** BATCH CMD : saveProjectFile -file"C:\MCL\MCL86\MCL86jr\MCL86jr_Impact.ipf"
|
||||
// *** BATCH CMD : setMode -bs
|
||||
// *** BATCH CMD : setMode -pff
|
||||
INFO:iMPACT - Launching WebTalk, please refer to the webtalk log at C:\MCL\MCL86\MCL86jr/webtalk.log for details.
|
||||
INFO:iMPACT - Running wbtc successfully.
|
||||
// *** BATCH CMD : setMode -bs
|
||||
// *** BATCH CMD : deleteDevice -position 1
|
||||
// *** BATCH CMD : setMode -bs
|
||||
// *** BATCH CMD : setMode -ss
|
||||
// *** BATCH CMD : setMode -sm
|
||||
// *** BATCH CMD : setMode -hw140
|
||||
// *** BATCH CMD : setMode -spi
|
||||
// *** BATCH CMD : setMode -acecf
|
||||
// *** BATCH CMD : setMode -acempm
|
||||
// *** BATCH CMD : setMode -pff
|
||||
// *** BATCH CMD : deletePromDevice -position 1
|
||||
// *** BATCH CMD : setCurrentDesign -version 0
|
||||
// *** BATCH CMD : deleteDevice -position 1
|
||||
// *** BATCH CMD : deleteDesign -version 0
|
||||
// *** BATCH CMD : setCurrentDesign -version -1
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
C:\MCL\MCL86\MCL86jr\MCL86jr\MCL86jr.ngc 1605150614
|
||||
ipcore_dir/EU4Kx32.ngc 1599965148
|
||||
OK
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="info" file="Bitgen" num="341" delta="old" >This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, requires a special bit stream format. For more information, please reference Xilinx Answer Record 39999.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="PhysDesignRules" num="1861" delta="old" >To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp <arg fmt="%s" index="1">SPARTAN6PLL/dcm_sp_inst</arg>, consult the device Data Sheet.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="2410" delta="old" >This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used. For more information, please reference Xilinx Answer Record 39999.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">EU_CORE/EU4Kx32_i/douta<31></arg> has no load.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Timing" num="3402" delta="old" >The Clock Modifying COMP, <arg fmt="%s" index="1">SPARTAN6PLL/dcm_sp_inst</arg>, has the attribute CLK_FEEDBACK set to NONE. No phase relationship exists between the input and output clocks of this Clock Modifying COMP. Data paths between these clock domains must be constrained using FROM/TO constraints.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="PhysDesignRules" num="1861" delta="old" >To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp <arg fmt="%s" index="1">SPARTAN6PLL/dcm_sp_inst</arg>, consult the device Data Sheet.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="2410" delta="old" >This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used. For more information, please reference Xilinx Answer Record 39999.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> '<arg fmt="%s" index="2">CORE_CLK</arg>', used in period specification '<arg fmt="%s" index="3">TS_CORE_CLK</arg>', was traced into <arg fmt="%s" index="4">DCM_SP</arg> instance <arg fmt="%s" index="5">SPARTAN6PLL/dcm_sp_inst</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">DCM_SP</arg> output(s):
|
||||
<arg fmt="%s" index="7">CLKFX</arg>: <arg fmt="%s" index="8"><TIMESPEC TS_SPARTAN6PLL_clkfx = PERIOD "SPARTAN6PLL_clkfx" TS_CORE_CLK / 2.2 HIGH 50%></arg>
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="warning" file="Timing" num="3402" delta="old" >The Clock Modifying COMP, <arg fmt="%s" index="1">SPARTAN6PLL/dcm_sp_inst</arg>, has the attribute CLK_FEEDBACK set to NONE. No phase relationship exists between the input and output clocks of this Clock Modifying COMP. Data paths between these clock domains must be constrained using FROM/TO constraints.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated -->
|
||||
<!-- by the Xilinx ISE software. Any direct editing or -->
|
||||
<!-- changes made to this file may result in unpredictable -->
|
||||
<!-- behavior or data corruption. It is strongly advised that -->
|
||||
<!-- users do not edit the contents of this file. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<messages>
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/MCL/MCL86/MCL86jr/src4synth/MCL86jr.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/MCL/MCL86/MCL86jr/src4synth/biu_min.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/MCL/MCL86/MCL86jr/src4synth/eu.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="warning" file="Timing" num="3402" delta="old" >The Clock Modifying COMP, <arg fmt="%s" index="1">SPARTAN6PLL/dcm_sp_inst</arg>, has the attribute CLK_FEEDBACK set to NONE. No phase relationship exists between the input and output clocks of this Clock Modifying COMP. Data paths between these clock domains must be constrained using FROM/TO constraints.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="3412" delta="old" >To improve timing, see the Timing Closure User Guide (UG612).</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
|
|
@ -0,0 +1,186 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\spartan6_pll.v" Line 111: Assignment to <arg fmt="%s" index="1">clk0</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\spartan6_pll.v" Line 126: Assignment to <arg fmt="%s" index="1">locked_int</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\spartan6_pll.v" Line 127: Assignment to <arg fmt="%s" index="1">status_int</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 182: Result of <arg fmt="%d" index="1">32</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">1</arg>-bit target.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 183: Result of <arg fmt="%d" index="1">32</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">1</arg>-bit target.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 184: Result of <arg fmt="%d" index="1">32</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">1</arg>-bit target.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 185: Result of <arg fmt="%d" index="1">32</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">1</arg>-bit target.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 186: Result of <arg fmt="%d" index="1">32</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">1</arg>-bit target.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 187: Result of <arg fmt="%d" index="1">32</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">1</arg>-bit target.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 188: Result of <arg fmt="%d" index="1">32</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">1</arg>-bit target.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 189: Result of <arg fmt="%d" index="1">32</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">1</arg>-bit target.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 213: Assignment to <arg fmt="%s" index="1">t_eu_flag_i_d</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 231: Assignment to <arg fmt="%s" index="1">eu_qs_out</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 477: Result of <arg fmt="%d" index="1">32</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">13</arg>-bit target.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 493: Result of <arg fmt="%d" index="1">17</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">16</arg>-bit target.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 503: Result of <arg fmt="%d" index="1">17</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">16</arg>-bit target.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 835: Result of <arg fmt="%d" index="1">17</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">16</arg>-bit target.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 276: Assignment to <arg fmt="%s" index="1">ready_d3</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1499" delta="old" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\EU4Kx32.v" Line 39: Empty module <<arg fmt="%s" index="1">EU4Kx32</arg>> remains a black box.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 264: Assignment to <arg fmt="%s" index="1">eu_prefix_repnz</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 265: Assignment to <arg fmt="%s" index="1">eu_prefix_rep</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 268: Assignment to <arg fmt="%s" index="1">eu_flag_o</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 269: Assignment to <arg fmt="%s" index="1">eu_flag_d</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 272: Assignment to <arg fmt="%s" index="1">eu_flag_s</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 273: Assignment to <arg fmt="%s" index="1">eu_flag_z</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 275: Assignment to <arg fmt="%s" index="1">eu_flag_a</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 276: Assignment to <arg fmt="%s" index="1">eu_nmi_pending</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 277: Assignment to <arg fmt="%s" index="1">eu_flag_p</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 278: Assignment to <arg fmt="%s" index="1">eu_flag_temp</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 279: Assignment to <arg fmt="%s" index="1">eu_flag_c</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 298: Result of <arg fmt="%d" index="1">20</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">16</arg>-bit target.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 338: Assignment to <arg fmt="%s" index="1">biu_done_d2</arg> ignored, since the identifier is never used
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 147: Net <<arg fmt="%s" index="1">system_signals[15]</arg>> does not have a driver.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="new" >"<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v</arg>" line <arg fmt="%s" index="2">269</arg>: Output port <<arg fmt="%s" index="3">BIU_SEGMENT</arg>> of the instance <<arg fmt="%s" index="4">BIU_CORE</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="3210" delta="new" >"<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v</arg>" line <arg fmt="%s" index="2">322</arg>: Output port <<arg fmt="%s" index="3">EU_FLAG_I</arg>> of the instance <<arg fmt="%s" index="4">EU_CORE</arg>> is unconnected or connected to loadless signal.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">EU_BIU_COMMAND<3:2></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">EU_BIU_COMMAND<15:15></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">EU_PREFIX_LOCK</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">system_signals<15:14></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="old" >Signal <<arg fmt="%s" index="1">system_signals<10></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">mcl6_feature_2</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">BIU_CORE</arg>>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">mcl6_feature_3</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">BIU_CORE</arg>>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">mcl6_feature_4</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">BIU_CORE</arg>>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">mcl6_feature_5</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">BIU_CORE</arg>>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">mcl6_feature_6</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">BIU_CORE</arg>>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">mcl6_feature_7</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">BIU_CORE</arg>>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">mcl6_feature_2</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">biu_min</arg>>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">mcl6_feature_3</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">biu_min</arg>>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">mcl6_feature_4</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">biu_min</arg>>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">mcl6_feature_5</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">biu_min</arg>>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">mcl6_feature_6</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">biu_min</arg>>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">mcl6_feature_7</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">biu_min</arg>>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">prescaler_22</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">MCL86jr</arg>>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">prescaler_23</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">MCL86jr</arg>>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">prescaler_24</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">MCL86jr</arg>>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">prescaler_25</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">MCL86jr</arg>>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">prescaler_26</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">MCL86jr</arg>>.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">BIU_CORE/eu_biu_req_d1</arg>> in Unit <<arg fmt="%s" index="2">MCL86jr</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><EU_CORE/eu_biu_req_d1> </arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 EU4Kx32
|
||||
RECTANGLE Normal 32 32 544 1376
|
||||
LINE Wide 0 80 32 80
|
||||
PIN 0 80 LEFT 36
|
||||
PINATTR PinName addra[11:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 272 32 272
|
||||
PIN 0 272 LEFT 36
|
||||
PINATTR PinName clka
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 576 80 544 80
|
||||
PIN 576 80 RIGHT 36
|
||||
PINATTR PinName douta[31:0]
|
||||
PINATTR Polarity OUT
|
||||
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="EU4Kx32.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="EU4Kx32.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VEO" xil_pn:name="EU4Kx32.veo" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1599968965" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1599968965">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1605150596" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3493971842567525973" xil_pn:start_ts="1605150596">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1605150596" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="2061036881009002330" xil_pn:start_ts="1605150596">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1605150596" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1605150596">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1605150596" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1277724965906371437" xil_pn:start_ts="1605150596">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
</generated_project>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,176 @@
|
|||
/*******************************************************************************
|
||||
* This file is owned and controlled by Xilinx and must be used solely *
|
||||
* for design, simulation, implementation and creation of design files *
|
||||
* limited to Xilinx devices or technologies. Use with non-Xilinx *
|
||||
* devices or technologies is expressly prohibited and immediately *
|
||||
* terminates your license. *
|
||||
* *
|
||||
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
|
||||
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
|
||||
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
|
||||
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
|
||||
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
|
||||
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
|
||||
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
|
||||
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
|
||||
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
|
||||
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
|
||||
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
|
||||
* PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* Xilinx products are not intended for use in life support appliances, *
|
||||
* devices, or systems. Use in such applications are expressly *
|
||||
* prohibited. *
|
||||
* *
|
||||
* (c) Copyright 1995-2020 Xilinx, Inc. *
|
||||
* All rights reserved. *
|
||||
*******************************************************************************/
|
||||
// You must compile the wrapper file EU4Kx32.v when simulating
|
||||
// the core, EU4Kx32. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
// The synthesis directives "translate_off/translate_on" specified below are
|
||||
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
|
||||
// tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module EU4Kx32(
|
||||
clka,
|
||||
addra,
|
||||
douta
|
||||
);
|
||||
|
||||
input clka;
|
||||
input [11 : 0] addra;
|
||||
output [31 : 0] douta;
|
||||
|
||||
// synthesis translate_off
|
||||
|
||||
BLK_MEM_GEN_V7_3 #(
|
||||
.C_ADDRA_WIDTH(12),
|
||||
.C_ADDRB_WIDTH(12),
|
||||
.C_ALGORITHM(1),
|
||||
.C_AXI_ID_WIDTH(4),
|
||||
.C_AXI_SLAVE_TYPE(0),
|
||||
.C_AXI_TYPE(1),
|
||||
.C_BYTE_SIZE(9),
|
||||
.C_COMMON_CLK(0),
|
||||
.C_DEFAULT_DATA("0"),
|
||||
.C_DISABLE_WARN_BHV_COLL(0),
|
||||
.C_DISABLE_WARN_BHV_RANGE(0),
|
||||
.C_ENABLE_32BIT_ADDRESS(0),
|
||||
.C_FAMILY("spartan6"),
|
||||
.C_HAS_AXI_ID(0),
|
||||
.C_HAS_ENA(0),
|
||||
.C_HAS_ENB(0),
|
||||
.C_HAS_INJECTERR(0),
|
||||
.C_HAS_MEM_OUTPUT_REGS_A(0),
|
||||
.C_HAS_MEM_OUTPUT_REGS_B(0),
|
||||
.C_HAS_MUX_OUTPUT_REGS_A(0),
|
||||
.C_HAS_MUX_OUTPUT_REGS_B(0),
|
||||
.C_HAS_REGCEA(0),
|
||||
.C_HAS_REGCEB(0),
|
||||
.C_HAS_RSTA(0),
|
||||
.C_HAS_RSTB(0),
|
||||
.C_HAS_SOFTECC_INPUT_REGS_A(0),
|
||||
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
|
||||
.C_INIT_FILE("BlankString"),
|
||||
.C_INIT_FILE_NAME("EU4Kx32.mif"),
|
||||
.C_INITA_VAL("0"),
|
||||
.C_INITB_VAL("0"),
|
||||
.C_INTERFACE_TYPE(0),
|
||||
.C_LOAD_INIT_FILE(1),
|
||||
.C_MEM_TYPE(3),
|
||||
.C_MUX_PIPELINE_STAGES(0),
|
||||
.C_PRIM_TYPE(1),
|
||||
.C_READ_DEPTH_A(4096),
|
||||
.C_READ_DEPTH_B(4096),
|
||||
.C_READ_WIDTH_A(32),
|
||||
.C_READ_WIDTH_B(32),
|
||||
.C_RST_PRIORITY_A("CE"),
|
||||
.C_RST_PRIORITY_B("CE"),
|
||||
.C_RST_TYPE("SYNC"),
|
||||
.C_RSTRAM_A(0),
|
||||
.C_RSTRAM_B(0),
|
||||
.C_SIM_COLLISION_CHECK("ALL"),
|
||||
.C_USE_BRAM_BLOCK(0),
|
||||
.C_USE_BYTE_WEA(0),
|
||||
.C_USE_BYTE_WEB(0),
|
||||
.C_USE_DEFAULT_DATA(0),
|
||||
.C_USE_ECC(0),
|
||||
.C_USE_SOFTECC(0),
|
||||
.C_WEA_WIDTH(1),
|
||||
.C_WEB_WIDTH(1),
|
||||
.C_WRITE_DEPTH_A(4096),
|
||||
.C_WRITE_DEPTH_B(4096),
|
||||
.C_WRITE_MODE_A("WRITE_FIRST"),
|
||||
.C_WRITE_MODE_B("WRITE_FIRST"),
|
||||
.C_WRITE_WIDTH_A(32),
|
||||
.C_WRITE_WIDTH_B(32),
|
||||
.C_XDEVICEFAMILY("spartan6")
|
||||
)
|
||||
inst (
|
||||
.CLKA(clka),
|
||||
.ADDRA(addra),
|
||||
.DOUTA(douta),
|
||||
.RSTA(),
|
||||
.ENA(),
|
||||
.REGCEA(),
|
||||
.WEA(),
|
||||
.DINA(),
|
||||
.CLKB(),
|
||||
.RSTB(),
|
||||
.ENB(),
|
||||
.REGCEB(),
|
||||
.WEB(),
|
||||
.ADDRB(),
|
||||
.DINB(),
|
||||
.DOUTB(),
|
||||
.INJECTSBITERR(),
|
||||
.INJECTDBITERR(),
|
||||
.SBITERR(),
|
||||
.DBITERR(),
|
||||
.RDADDRECC(),
|
||||
.S_ACLK(),
|
||||
.S_ARESETN(),
|
||||
.S_AXI_AWID(),
|
||||
.S_AXI_AWADDR(),
|
||||
.S_AXI_AWLEN(),
|
||||
.S_AXI_AWSIZE(),
|
||||
.S_AXI_AWBURST(),
|
||||
.S_AXI_AWVALID(),
|
||||
.S_AXI_AWREADY(),
|
||||
.S_AXI_WDATA(),
|
||||
.S_AXI_WSTRB(),
|
||||
.S_AXI_WLAST(),
|
||||
.S_AXI_WVALID(),
|
||||
.S_AXI_WREADY(),
|
||||
.S_AXI_BID(),
|
||||
.S_AXI_BRESP(),
|
||||
.S_AXI_BVALID(),
|
||||
.S_AXI_BREADY(),
|
||||
.S_AXI_ARID(),
|
||||
.S_AXI_ARADDR(),
|
||||
.S_AXI_ARLEN(),
|
||||
.S_AXI_ARSIZE(),
|
||||
.S_AXI_ARBURST(),
|
||||
.S_AXI_ARVALID(),
|
||||
.S_AXI_ARREADY(),
|
||||
.S_AXI_RID(),
|
||||
.S_AXI_RDATA(),
|
||||
.S_AXI_RRESP(),
|
||||
.S_AXI_RLAST(),
|
||||
.S_AXI_RVALID(),
|
||||
.S_AXI_RREADY(),
|
||||
.S_AXI_INJECTSBITERR(),
|
||||
.S_AXI_INJECTDBITERR(),
|
||||
.S_AXI_SBITERR(),
|
||||
.S_AXI_DBITERR(),
|
||||
.S_AXI_RDADDRECC()
|
||||
);
|
||||
|
||||
// synthesis translate_on
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
/*******************************************************************************
|
||||
* This file is owned and controlled by Xilinx and must be used solely *
|
||||
* for design, simulation, implementation and creation of design files *
|
||||
* limited to Xilinx devices or technologies. Use with non-Xilinx *
|
||||
* devices or technologies is expressly prohibited and immediately *
|
||||
* terminates your license. *
|
||||
* *
|
||||
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
|
||||
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
|
||||
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
|
||||
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
|
||||
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
|
||||
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
|
||||
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
|
||||
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
|
||||
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
|
||||
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
|
||||
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
|
||||
* PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* Xilinx products are not intended for use in life support appliances, *
|
||||
* devices, or systems. Use in such applications are expressly *
|
||||
* prohibited. *
|
||||
* *
|
||||
* (c) Copyright 1995-2020 Xilinx, Inc. *
|
||||
* All rights reserved. *
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.3 *
|
||||
* *
|
||||
* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port *
|
||||
* Block Memory and Single Port Block Memory LogiCOREs, but is not a *
|
||||
* direct drop-in replacement. It should be used in all new Xilinx *
|
||||
* designs. The core supports RAM and ROM functions over a wide range of *
|
||||
* widths and depths. Use this core to generate block memories with *
|
||||
* symmetric or asymmetric read and write port widths, as well as cores *
|
||||
* which can perform simultaneous write operations to separate *
|
||||
* locations, and simultaneous read operations from the same location. *
|
||||
* For more information on differences in interface and feature support *
|
||||
* between this core and the Dual Port Block Memory and Single Port *
|
||||
* Block Memory LogiCOREs, please consult the data sheet. *
|
||||
*******************************************************************************/
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
EU4Kx32 your_instance_name (
|
||||
.clka(clka), // input clka
|
||||
.addra(addra), // input [11 : 0] addra
|
||||
.douta(douta) // output [31 : 0] douta
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file EU4Kx32.v when simulating
|
||||
// the core, EU4Kx32. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.7
|
||||
# Date: Sun Sep 13 03:44:44 2020
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:blk_mem_gen:7.3
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc6slx9
|
||||
SET devicefamily = spartan6
|
||||
SET flowvendor = Other
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = tqg144
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -2
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET additional_inputs_for_power_estimation=false
|
||||
CSET algorithm=Minimum_Area
|
||||
CSET assume_synchronous_clk=false
|
||||
CSET axi_id_width=4
|
||||
CSET axi_slave_type=Memory_Slave
|
||||
CSET axi_type=AXI4_Full
|
||||
CSET byte_size=9
|
||||
CSET coe_file=C:\MCL\MCL86\MCL86jr\src4synth\MCL86_Microcode_Xilinx.coe
|
||||
CSET collision_warnings=ALL
|
||||
CSET component_name=EU4Kx32
|
||||
CSET disable_collision_warnings=false
|
||||
CSET disable_out_of_range_warnings=false
|
||||
CSET ecc=false
|
||||
CSET ecctype=No_ECC
|
||||
CSET enable_32bit_address=false
|
||||
CSET enable_a=Always_Enabled
|
||||
CSET enable_b=Always_Enabled
|
||||
CSET error_injection_type=Single_Bit_Error_Injection
|
||||
CSET fill_remaining_memory_locations=false
|
||||
CSET interface_type=Native
|
||||
CSET load_init_file=true
|
||||
CSET mem_file=no_Mem_file_loaded
|
||||
CSET memory_type=Single_Port_ROM
|
||||
CSET operating_mode_a=WRITE_FIRST
|
||||
CSET operating_mode_b=WRITE_FIRST
|
||||
CSET output_reset_value_a=0
|
||||
CSET output_reset_value_b=0
|
||||
CSET pipeline_stages=0
|
||||
CSET port_a_clock=100
|
||||
CSET port_a_enable_rate=100
|
||||
CSET port_a_write_rate=0
|
||||
CSET port_b_clock=0
|
||||
CSET port_b_enable_rate=0
|
||||
CSET port_b_write_rate=0
|
||||
CSET primitive=8kx2
|
||||
CSET read_width_a=32
|
||||
CSET read_width_b=32
|
||||
CSET register_porta_input_of_softecc=false
|
||||
CSET register_porta_output_of_memory_core=false
|
||||
CSET register_porta_output_of_memory_primitives=false
|
||||
CSET register_portb_output_of_memory_core=false
|
||||
CSET register_portb_output_of_memory_primitives=false
|
||||
CSET register_portb_output_of_softecc=false
|
||||
CSET remaining_memory_locations=0
|
||||
CSET reset_memory_latch_a=false
|
||||
CSET reset_memory_latch_b=false
|
||||
CSET reset_priority_a=CE
|
||||
CSET reset_priority_b=CE
|
||||
CSET reset_type=SYNC
|
||||
CSET softecc=false
|
||||
CSET use_axi_id=false
|
||||
CSET use_bram_block=Stand_Alone
|
||||
CSET use_byte_write_enable=false
|
||||
CSET use_error_injection_pins=false
|
||||
CSET use_regcea_pin=false
|
||||
CSET use_regceb_pin=false
|
||||
CSET use_rsta_pin=false
|
||||
CSET use_rstb_pin=false
|
||||
CSET write_depth_a=4096
|
||||
CSET write_width_a=32
|
||||
CSET write_width_b=32
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-11-19T16:22:25Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: e19ac0b2
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
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|
@ -0,0 +1,213 @@
|
|||
Core name: Xilinx LogiCORE Block Memory Generator
|
||||
Version: 7.3 Rev 1
|
||||
Release: ISE 14.4 / Vivado 2012.4
|
||||
Release Date: October 16, 2012
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURES HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
|
||||
|
||||
For system requirements:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.3
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
All Virtex-6 devices
|
||||
All Spartan-6 devices
|
||||
All Virtex-5 devices
|
||||
All Spartan-3 devices
|
||||
All Virtex-4 devices
|
||||
|
||||
|
||||
2.2 Vivado
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
|
||||
................................................................................
|
||||
|
||||
3. NEW FEATURES HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- ISE 14.4 software support
|
||||
|
||||
|
||||
3.2 Vivado
|
||||
|
||||
- 2012.4 software support
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
The following issues are resolved in Block Memory Generator v7.3:
|
||||
|
||||
4.1 ISE
|
||||
|
||||
|
||||
4.2 Vivado
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
The following are known issues for v7.3 of this core at time of release:
|
||||
|
||||
1. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
|
||||
|
||||
3. Core does not generate for large memories. Depending on the
|
||||
machine the ISE CORE Generator software runs on, the maximum size of the memory that
|
||||
can be generated will vary. For example, a Dual Pentium-4 server
|
||||
with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
|
||||
- CR 415768
|
||||
- AR 24034
|
||||
|
||||
|
||||
5.2 Vivado
|
||||
|
||||
The following are known issues for v7.3 of this core at time of release:
|
||||
|
||||
The most recent information, including known issues, workarounds, and resolutions for
|
||||
this version is provided in the IP Release Notes User Guide located at
|
||||
|
||||
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
To obtain technical support, create a WebCase at www.xilinx.com/support.
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
12/16/2012 Xilinx, Inc. 7.3 Rev 1 ISE 14.4 and Vivado 2012.4 support;
|
||||
10/16/2012 Xilinx, Inc. 7.3 ISE 14.3 and Vivado 2012.3 support;
|
||||
07/25/2012 Xilinx, Inc. 7.2 ISE 14.2 and Vivado 2012.2 support;
|
||||
04/24/2012 Xilinx, Inc. 7.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
|
||||
01/18/2011 Xilinx, Inc. 6.3 ISE 13.4 support;Artix7L*, AArtix-7* device support
|
||||
06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
|
||||
03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
|
||||
09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support
|
||||
07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support
|
||||
03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue
|
||||
12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power
|
||||
Device support; Automotive Spartan 3A
|
||||
DSP device support
|
||||
09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3
|
||||
06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2
|
||||
04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1
|
||||
09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8
|
||||
03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7
|
||||
10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6
|
||||
07/2007 Xilinx, Inc. 2.5 Revised to v2.5
|
||||
04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1
|
||||
02/2007 Xilinx, Inc. 2.4 Revised to v2.4
|
||||
11/2006 Xilinx, Inc. 2.3 Revised to v2.3
|
||||
09/2006 Xilinx, Inc. 2.2 Revised to v2.2
|
||||
06/2006 Xilinx, Inc. 2.1 Revised to v2.1
|
||||
01/2006 Xilinx, Inc. 1.1 Initial release
|
||||
================================================================================
|
||||
|
||||
8. Legal Disclaimer
|
||||
|
||||
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
|
|
@ -0,0 +1,224 @@
|
|||
<HTML>
|
||||
<HEAD>
|
||||
<TITLE>blk_mem_gen_v7_3_vinfo</TITLE>
|
||||
<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
|
||||
</HEAD>
|
||||
<BODY>
|
||||
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
|
||||
Core name: Xilinx LogiCORE Block Memory Generator
|
||||
Version: 7.3 Rev 1
|
||||
Release: ISE 14.4 / Vivado 2012.4
|
||||
Release Date: October 16, 2012
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURES HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
|
||||
|
||||
For system requirements:
|
||||
|
||||
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.3
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
<A HREF="http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm">www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm</A>
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
All Virtex-6 devices
|
||||
All Spartan-6 devices
|
||||
All Virtex-5 devices
|
||||
All Spartan-3 devices
|
||||
All Virtex-4 devices
|
||||
|
||||
|
||||
2.2 Vivado
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
|
||||
................................................................................
|
||||
|
||||
3. NEW FEATURES HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- ISE 14.4 software support
|
||||
|
||||
|
||||
3.2 Vivado
|
||||
|
||||
- 2012.4 software support
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
The following issues are resolved in Block Memory Generator v7.3:
|
||||
|
||||
4.1 ISE
|
||||
|
||||
|
||||
4.2 Vivado
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
The following are known issues for v7.3 of this core at time of release:
|
||||
|
||||
1. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
|
||||
|
||||
3. Core does not generate for large memories. Depending on the
|
||||
machine the ISE CORE Generator software runs on, the maximum size of the memory that
|
||||
can be generated will vary. For example, a Dual Pentium-4 server
|
||||
with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
|
||||
- CR 415768
|
||||
- AR 24034
|
||||
|
||||
|
||||
5.2 Vivado
|
||||
|
||||
The following are known issues for v7.3 of this core at time of release:
|
||||
|
||||
The most recent information, including known issues, workarounds, and resolutions for
|
||||
this version is provided in the IP Release Notes User Guide located at
|
||||
|
||||
<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
12/16/2012 Xilinx, Inc. 7.3 Rev 1 ISE 14.4 and Vivado 2012.4 support;
|
||||
10/16/2012 Xilinx, Inc. 7.3 ISE 14.3 and Vivado 2012.3 support;
|
||||
07/25/2012 Xilinx, Inc. 7.2 ISE 14.2 and Vivado 2012.2 support;
|
||||
04/24/2012 Xilinx, Inc. 7.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
|
||||
01/18/2011 Xilinx, Inc. 6.3 ISE 13.4 support;Artix7L*, AArtix-7* device support
|
||||
06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
|
||||
03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
|
||||
09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support
|
||||
07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support
|
||||
03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue
|
||||
12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power
|
||||
Device support; Automotive Spartan 3A
|
||||
DSP device support
|
||||
09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3
|
||||
06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2
|
||||
04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1
|
||||
09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8
|
||||
03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7
|
||||
10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6
|
||||
07/2007 Xilinx, Inc. 2.5 Revised to v2.5
|
||||
04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1
|
||||
02/2007 Xilinx, Inc. 2.4 Revised to v2.4
|
||||
11/2006 Xilinx, Inc. 2.3 Revised to v2.3
|
||||
09/2006 Xilinx, Inc. 2.2 Revised to v2.2
|
||||
06/2006 Xilinx, Inc. 2.1 Revised to v2.1
|
||||
01/2006 Xilinx, Inc. 1.1 Initial release
|
||||
================================================================================
|
||||
|
||||
8. Legal Disclaimer
|
||||
|
||||
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
</FONT>
|
||||
</PRE>
|
||||
</BODY>
|
||||
</HTML>
|
||||
Binary file not shown.
|
|
@ -0,0 +1,57 @@
|
|||
################################################################################
|
||||
#
|
||||
# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
# Tx Core Period Constraint. This constraint can be modified, and is
|
||||
# valid as long as it is met after place and route.
|
||||
NET "CLKA" TNM_NET = "CLKA";
|
||||
|
||||
TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ;
|
||||
|
||||
################################################################################
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: EU4Kx32_exdes.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- This is the actual BMG core wrapper.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: August 31, 2005 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
LIBRARY UNISIM;
|
||||
USE UNISIM.VCOMPONENTS.ALL;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Entity Declaration
|
||||
--------------------------------------------------------------------------------
|
||||
ENTITY EU4Kx32_exdes IS
|
||||
PORT (
|
||||
--Inputs - Port A
|
||||
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
|
||||
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
CLKA : IN STD_LOGIC
|
||||
|
||||
|
||||
);
|
||||
|
||||
END EU4Kx32_exdes;
|
||||
|
||||
|
||||
ARCHITECTURE xilinx OF EU4Kx32_exdes IS
|
||||
|
||||
COMPONENT BUFG IS
|
||||
PORT (
|
||||
I : IN STD_ULOGIC;
|
||||
O : OUT STD_ULOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT EU4Kx32 IS
|
||||
PORT (
|
||||
--Port A
|
||||
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
|
||||
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
|
||||
CLKA : IN STD_LOGIC
|
||||
|
||||
|
||||
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
SIGNAL CLKA_buf : STD_LOGIC;
|
||||
SIGNAL CLKB_buf : STD_LOGIC;
|
||||
SIGNAL S_ACLK_buf : STD_LOGIC;
|
||||
|
||||
BEGIN
|
||||
|
||||
bufg_A : BUFG
|
||||
PORT MAP (
|
||||
I => CLKA,
|
||||
O => CLKA_buf
|
||||
);
|
||||
|
||||
|
||||
|
||||
bmg0 : EU4Kx32
|
||||
PORT MAP (
|
||||
--Port A
|
||||
ADDRA => ADDRA,
|
||||
|
||||
DOUTA => DOUTA,
|
||||
|
||||
CLKA => CLKA_buf
|
||||
|
||||
|
||||
);
|
||||
|
||||
END xilinx;
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
################################################################################
|
||||
#
|
||||
# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
# Core Period Constraint. This constraint can be modified, and is
|
||||
# valid as long as it is met after place and route.
|
||||
create_clock -name "TS_CLKA" -period 20.0 [ get_ports CLKA ]
|
||||
################################################################################
|
||||
|
|
@ -0,0 +1,260 @@
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7.1 Core - Top-level wrapper
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: EU4Kx32_prod.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- This is the top-level BMG wrapper (over BMG core).
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: August 31, 2005 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Configured Core Parameter Values:
|
||||
-- (Refer to the SIM Parameters table in the datasheet for more information on
|
||||
-- the these parameters.)
|
||||
-- C_FAMILY : spartan6
|
||||
-- C_XDEVICEFAMILY : spartan6
|
||||
-- C_INTERFACE_TYPE : 0
|
||||
-- C_ENABLE_32BIT_ADDRESS : 0
|
||||
-- C_AXI_TYPE : 1
|
||||
-- C_AXI_SLAVE_TYPE : 0
|
||||
-- C_AXI_ID_WIDTH : 4
|
||||
-- C_MEM_TYPE : 3
|
||||
-- C_BYTE_SIZE : 9
|
||||
-- C_ALGORITHM : 1
|
||||
-- C_PRIM_TYPE : 1
|
||||
-- C_LOAD_INIT_FILE : 1
|
||||
-- C_INIT_FILE_NAME : EU4Kx32.mif
|
||||
-- C_USE_DEFAULT_DATA : 0
|
||||
-- C_DEFAULT_DATA : 0
|
||||
-- C_RST_TYPE : SYNC
|
||||
-- C_HAS_RSTA : 0
|
||||
-- C_RST_PRIORITY_A : CE
|
||||
-- C_RSTRAM_A : 0
|
||||
-- C_INITA_VAL : 0
|
||||
-- C_HAS_ENA : 0
|
||||
-- C_HAS_REGCEA : 0
|
||||
-- C_USE_BYTE_WEA : 0
|
||||
-- C_WEA_WIDTH : 1
|
||||
-- C_WRITE_MODE_A : WRITE_FIRST
|
||||
-- C_WRITE_WIDTH_A : 32
|
||||
-- C_READ_WIDTH_A : 32
|
||||
-- C_WRITE_DEPTH_A : 4096
|
||||
-- C_READ_DEPTH_A : 4096
|
||||
-- C_ADDRA_WIDTH : 12
|
||||
-- C_HAS_RSTB : 0
|
||||
-- C_RST_PRIORITY_B : CE
|
||||
-- C_RSTRAM_B : 0
|
||||
-- C_INITB_VAL : 0
|
||||
-- C_HAS_ENB : 0
|
||||
-- C_HAS_REGCEB : 0
|
||||
-- C_USE_BYTE_WEB : 0
|
||||
-- C_WEB_WIDTH : 1
|
||||
-- C_WRITE_MODE_B : WRITE_FIRST
|
||||
-- C_WRITE_WIDTH_B : 32
|
||||
-- C_READ_WIDTH_B : 32
|
||||
-- C_WRITE_DEPTH_B : 4096
|
||||
-- C_READ_DEPTH_B : 4096
|
||||
-- C_ADDRB_WIDTH : 12
|
||||
-- C_HAS_MEM_OUTPUT_REGS_A : 0
|
||||
-- C_HAS_MEM_OUTPUT_REGS_B : 0
|
||||
-- C_HAS_MUX_OUTPUT_REGS_A : 0
|
||||
-- C_HAS_MUX_OUTPUT_REGS_B : 0
|
||||
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
|
||||
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
|
||||
-- C_MUX_PIPELINE_STAGES : 0
|
||||
-- C_USE_ECC : 0
|
||||
-- C_USE_SOFTECC : 0
|
||||
-- C_HAS_INJECTERR : 0
|
||||
-- C_SIM_COLLISION_CHECK : ALL
|
||||
-- C_COMMON_CLK : 0
|
||||
-- C_DISABLE_WARN_BHV_COLL : 0
|
||||
-- C_DISABLE_WARN_BHV_RANGE : 0
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
LIBRARY UNISIM;
|
||||
USE UNISIM.VCOMPONENTS.ALL;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Entity Declaration
|
||||
--------------------------------------------------------------------------------
|
||||
ENTITY EU4Kx32_prod IS
|
||||
PORT (
|
||||
--Port A
|
||||
CLKA : IN STD_LOGIC;
|
||||
RSTA : IN STD_LOGIC; --opt port
|
||||
ENA : IN STD_LOGIC; --optional port
|
||||
REGCEA : IN STD_LOGIC; --optional port
|
||||
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
|
||||
--Port B
|
||||
CLKB : IN STD_LOGIC;
|
||||
RSTB : IN STD_LOGIC; --opt port
|
||||
ENB : IN STD_LOGIC; --optional port
|
||||
REGCEB : IN STD_LOGIC; --optional port
|
||||
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
|
||||
--ECC
|
||||
INJECTSBITERR : IN STD_LOGIC; --optional port
|
||||
INJECTDBITERR : IN STD_LOGIC; --optional port
|
||||
SBITERR : OUT STD_LOGIC; --optional port
|
||||
DBITERR : OUT STD_LOGIC; --optional port
|
||||
RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); --optional port
|
||||
-- AXI BMG Input and Output Port Declarations
|
||||
|
||||
-- AXI Global Signals
|
||||
S_ACLK : IN STD_LOGIC;
|
||||
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_AWVALID : IN STD_LOGIC;
|
||||
S_AXI_AWREADY : OUT STD_LOGIC;
|
||||
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_WLAST : IN STD_LOGIC;
|
||||
S_AXI_WVALID : IN STD_LOGIC;
|
||||
S_AXI_WREADY : OUT STD_LOGIC;
|
||||
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
|
||||
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_BVALID : OUT STD_LOGIC;
|
||||
S_AXI_BREADY : IN STD_LOGIC;
|
||||
|
||||
-- AXI Full/Lite Slave Read (Write side)
|
||||
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_ARVALID : IN STD_LOGIC;
|
||||
S_AXI_ARREADY : OUT STD_LOGIC;
|
||||
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
|
||||
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_RLAST : OUT STD_LOGIC;
|
||||
S_AXI_RVALID : OUT STD_LOGIC;
|
||||
S_AXI_RREADY : IN STD_LOGIC;
|
||||
|
||||
-- AXI Full/Lite Sideband Signals
|
||||
S_AXI_INJECTSBITERR : IN STD_LOGIC;
|
||||
S_AXI_INJECTDBITERR : IN STD_LOGIC;
|
||||
S_AXI_SBITERR : OUT STD_LOGIC;
|
||||
S_AXI_DBITERR : OUT STD_LOGIC;
|
||||
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
S_ARESETN : IN STD_LOGIC
|
||||
|
||||
|
||||
);
|
||||
|
||||
END EU4Kx32_prod;
|
||||
|
||||
|
||||
ARCHITECTURE xilinx OF EU4Kx32_prod IS
|
||||
|
||||
COMPONENT EU4Kx32_exdes IS
|
||||
PORT (
|
||||
--Port A
|
||||
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
|
||||
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
|
||||
CLKA : IN STD_LOGIC
|
||||
|
||||
|
||||
|
||||
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
|
||||
bmg0 : EU4Kx32_exdes
|
||||
PORT MAP (
|
||||
--Port A
|
||||
ADDRA => ADDRA,
|
||||
|
||||
DOUTA => DOUTA,
|
||||
|
||||
CLKA => CLKA
|
||||
|
||||
|
||||
|
||||
);
|
||||
END xilinx;
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
rem Clean up the results directory
|
||||
rmdir /S /Q results
|
||||
mkdir results
|
||||
|
||||
rem Synthesize the VHDL Wrapper Files
|
||||
|
||||
|
||||
echo 'Synthesizing example design with XST';
|
||||
xst -ifn xst.scr
|
||||
copy EU4Kx32_exdes.ngc .\results\
|
||||
|
||||
|
||||
rem Copy the netlist generated by Coregen
|
||||
echo 'Copying files from the netlist directory to the results directory'
|
||||
copy ..\..\EU4Kx32.ngc results\
|
||||
|
||||
|
||||
rem Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
copy ..\example_design\EU4Kx32_exdes.ucf results\
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
ngdbuild -p xc6slx9-tqg144-2 EU4Kx32_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map EU4Kx32_exdes -o mapped.ncd -pr i
|
||||
|
||||
echo 'Running par'
|
||||
par mapped.ncd routed.ncd
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed.ncd mapped.pcf -o routed
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed
|
||||
|
||||
echo 'Running netgen to create gate level Verilog model'
|
||||
netgen -ofmt verilog -sim -tm EU4Kx32_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#!/bin/sh
|
||||
|
||||
# Clean up the results directory
|
||||
rm -rf results
|
||||
mkdir results
|
||||
|
||||
#Synthesize the Wrapper Files
|
||||
|
||||
echo 'Synthesizing example design with XST';
|
||||
xst -ifn xst.scr
|
||||
cp EU4Kx32_exdes.ngc ./results/
|
||||
|
||||
|
||||
# Copy the netlist generated by Coregen
|
||||
echo 'Copying files from the netlist directory to the results directory'
|
||||
cp ../../EU4Kx32.ngc results/
|
||||
|
||||
# Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
cp ../example_design/EU4Kx32_exdes.ucf results/
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
ngdbuild -p xc6slx9-tqg144-2 EU4Kx32_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map EU4Kx32_exdes -o mapped.ncd -pr i
|
||||
|
||||
echo 'Running par'
|
||||
par mapped.ncd routed.ncd
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed.ncd mapped.pcf -o routed
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed
|
||||
|
||||
echo 'Running netgen to create gate level Verilog model'
|
||||
netgen -ofmt verilog -sim -tm EU4Kx32_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
#!/bin/sh
|
||||
rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
rem
|
||||
rem This file contains confidential and proprietary information
|
||||
rem of Xilinx, Inc. and is protected under U.S. and
|
||||
rem international copyright and other intellectual property
|
||||
rem laws.
|
||||
rem
|
||||
rem DISCLAIMER
|
||||
rem This disclaimer is not a license and does not grant any
|
||||
rem rights to the materials distributed herewith. Except as
|
||||
rem otherwise provided in a valid license issued to you by
|
||||
rem Xilinx, and to the maximum extent permitted by applicable
|
||||
rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
rem (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
rem including negligence, or under any other theory of
|
||||
rem liability) for any loss or damage of any kind or nature
|
||||
rem related to, arising under or in connection with these
|
||||
rem materials, including for any direct, or any indirect,
|
||||
rem special, incidental, or consequential loss or damage
|
||||
rem (including loss of data, profits, goodwill, or any type of
|
||||
rem loss or damage suffered as a result of any action brought
|
||||
rem by a third party) even if such damage or loss was
|
||||
rem reasonably foreseeable or Xilinx had been advised of the
|
||||
rem possibility of the same.
|
||||
rem
|
||||
rem CRITICAL APPLICATIONS
|
||||
rem Xilinx products are not designed or intended to be fail-
|
||||
rem safe, or for use in any application requiring fail-safe
|
||||
rem performance, such as life-support or safety devices or
|
||||
rem systems, Class III medical devices, nuclear facilities,
|
||||
rem applications related to the deployment of airbags, or any
|
||||
rem other applications that could lead to death, personal
|
||||
rem injury, or severe property or environmental damage
|
||||
rem (individually and collectively, "Critical
|
||||
rem Applications"). Customer assumes the sole risk and
|
||||
rem liability of any use of Xilinx products in Critical
|
||||
rem Applications, subject only to applicable laws and
|
||||
rem regulations governing limitations on product liability.
|
||||
rem
|
||||
rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
rem PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
rem -----------------------------------------------------------------------------
|
||||
rem Script to synthesize and implement the Coregen FIFO Generator
|
||||
rem -----------------------------------------------------------------------------
|
||||
rmdir /S /Q results
|
||||
mkdir results
|
||||
cd results
|
||||
copy ..\..\..\EU4Kx32.ngc .
|
||||
planAhead -mode batch -source ..\planAhead_ise.tcl
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Script to synthesize and implement the Coregen FIFO Generator
|
||||
#-----------------------------------------------------------------------------
|
||||
rm -rf results
|
||||
mkdir results
|
||||
cd results
|
||||
cp ../../../EU4Kx32.ngc .
|
||||
planAhead -mode batch -source ../planAhead_ise.tcl
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
|
||||
set device xc6slx9tqg144-2
|
||||
set projName EU4Kx32
|
||||
set design EU4Kx32
|
||||
set projDir [file dirname [info script]]
|
||||
create_project $projName $projDir/results/$projName -part $device -force
|
||||
set_property design_mode RTL [current_fileset -srcset]
|
||||
set top_module EU4Kx32_exdes
|
||||
add_files -norecurse {../../example_design/EU4Kx32_exdes.vhd}
|
||||
add_files -norecurse {./EU4Kx32.ngc}
|
||||
import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/EU4Kx32_exdes.xdc}
|
||||
set_property top EU4Kx32_exdes [get_property srcset [current_run]]
|
||||
synth_design
|
||||
opt_design
|
||||
place_design
|
||||
route_design
|
||||
write_sdf -rename_top_module EU4Kx32_exdes -file routed.sdf
|
||||
write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module EU4Kx32_exdes routed.v
|
||||
report_timing -nworst 30 -path_type full -file routed.twr
|
||||
report_drc -file report.drc
|
||||
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}
|
||||
|
|
@ -0,0 +1 @@
|
|||
work ../example_design/EU4Kx32_exdes.vhd
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
run
|
||||
-ifmt VHDL
|
||||
-ent EU4Kx32_exdes
|
||||
-p xc6slx9-tqg144-2
|
||||
-ifn xst.prj
|
||||
-write_timing_constraints No
|
||||
-iobuf YES
|
||||
-max_fanout 100
|
||||
-ofn EU4Kx32_exdes
|
||||
-ofmt NGC
|
||||
-bus_delimiter ()
|
||||
-hierarchy_separator /
|
||||
-case Maintain
|
||||
|
|
@ -0,0 +1,255 @@
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: EU4Kx32_synth.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Synthesizable Testbench
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
USE IEEE.STD_LOGIC_MISC.ALL;
|
||||
|
||||
LIBRARY STD;
|
||||
USE STD.TEXTIO.ALL;
|
||||
|
||||
--LIBRARY unisim;
|
||||
--USE unisim.vcomponents.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.ALL;
|
||||
USE work.BMG_TB_PKG.ALL;
|
||||
|
||||
ENTITY EU4Kx32_synth IS
|
||||
GENERIC (
|
||||
C_ROM_SYNTH : INTEGER := 1
|
||||
);
|
||||
PORT(
|
||||
CLK_IN : IN STD_LOGIC;
|
||||
RESET_IN : IN STD_LOGIC;
|
||||
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
|
||||
);
|
||||
END ENTITY;
|
||||
|
||||
ARCHITECTURE EU4Kx32_synth_ARCH OF EU4Kx32_synth IS
|
||||
|
||||
|
||||
COMPONENT EU4Kx32_exdes
|
||||
PORT (
|
||||
--Inputs - Port A
|
||||
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
CLKA : IN STD_LOGIC
|
||||
|
||||
|
||||
);
|
||||
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
SIGNAL CLKA: STD_LOGIC := '0';
|
||||
SIGNAL RSTA: STD_LOGIC := '0';
|
||||
SIGNAL ADDRA: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
SIGNAL CHECKER_EN : STD_LOGIC:='0';
|
||||
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
|
||||
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
|
||||
SIGNAL clk_in_i: STD_LOGIC;
|
||||
|
||||
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
|
||||
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
|
||||
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
|
||||
|
||||
SIGNAL ITER_R0 : STD_LOGIC := '0';
|
||||
SIGNAL ITER_R1 : STD_LOGIC := '0';
|
||||
SIGNAL ITER_R2 : STD_LOGIC := '0';
|
||||
|
||||
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
|
||||
BEGIN
|
||||
|
||||
-- clk_buf: bufg
|
||||
-- PORT map(
|
||||
-- i => CLK_IN,
|
||||
-- o => clk_in_i
|
||||
-- );
|
||||
clk_in_i <= CLK_IN;
|
||||
CLKA <= clk_in_i;
|
||||
|
||||
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
|
||||
|
||||
|
||||
PROCESS(clk_in_i)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(clk_in_i)) THEN
|
||||
RESET_SYNC_R1 <= RESET_IN;
|
||||
RESET_SYNC_R2 <= RESET_SYNC_R1;
|
||||
RESET_SYNC_R3 <= RESET_SYNC_R2;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(RESET_SYNC_R3='1') THEN
|
||||
ISSUE_FLAG_STATUS<= (OTHERS => '0');
|
||||
ELSE
|
||||
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
|
||||
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
|
||||
)
|
||||
|
||||
PORT MAP(
|
||||
CLK => clk_in_i,
|
||||
RST => RSTA,
|
||||
ADDRA => ADDRA,
|
||||
DATA_IN => DOUTA,
|
||||
STATUS => ISSUE_FLAG(0)
|
||||
);
|
||||
|
||||
PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(RESET_SYNC_R3='1') THEN
|
||||
STATUS(8) <= '0';
|
||||
iter_r2 <= '0';
|
||||
iter_r1 <= '0';
|
||||
iter_r0 <= '0';
|
||||
ELSE
|
||||
STATUS(8) <= iter_r2;
|
||||
iter_r2 <= iter_r1;
|
||||
iter_r1 <= iter_r0;
|
||||
iter_r0 <= STIMULUS_FLOW(8);
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(RESET_SYNC_R3='1') THEN
|
||||
STIMULUS_FLOW <= (OTHERS => '0');
|
||||
ELSIF(ADDRA(0)='1') THEN
|
||||
STIMULUS_FLOW <= STIMULUS_FLOW+1;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(RESET_SYNC_R3='1') THEN
|
||||
|
||||
|
||||
ELSE
|
||||
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(RESET_SYNC_R3='1') THEN
|
||||
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
|
||||
ELSE
|
||||
ADDRA_R <= ADDRA AFTER 50 ns;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
BMG_PORT: EU4Kx32_exdes PORT MAP (
|
||||
--Port A
|
||||
ADDRA => ADDRA_R,
|
||||
DOUTA => DOUTA,
|
||||
CLKA => CLKA
|
||||
|
||||
);
|
||||
END ARCHITECTURE;
|
||||
|
|
@ -0,0 +1,135 @@
|
|||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Filename: EU4Kx32_tb.vhd
|
||||
-- Description:
|
||||
-- Testbench Top
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.ALL;
|
||||
|
||||
ENTITY EU4Kx32_tb IS
|
||||
END ENTITY;
|
||||
|
||||
|
||||
ARCHITECTURE EU4Kx32_tb_ARCH OF EU4Kx32_tb IS
|
||||
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
SIGNAL CLK : STD_LOGIC := '1';
|
||||
SIGNAL RESET : STD_LOGIC;
|
||||
|
||||
BEGIN
|
||||
|
||||
|
||||
CLK_GEN: PROCESS BEGIN
|
||||
CLK <= NOT CLK;
|
||||
WAIT FOR 100 NS;
|
||||
CLK <= NOT CLK;
|
||||
WAIT FOR 100 NS;
|
||||
END PROCESS;
|
||||
|
||||
RST_GEN: PROCESS BEGIN
|
||||
RESET <= '1';
|
||||
WAIT FOR 1000 NS;
|
||||
RESET <= '0';
|
||||
WAIT;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
--STOP_SIM: PROCESS BEGIN
|
||||
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
|
||||
-- ASSERT FALSE
|
||||
-- REPORT "END SIMULATION TIME REACHED"
|
||||
-- SEVERITY FAILURE;
|
||||
--END PROCESS;
|
||||
--
|
||||
PROCESS BEGIN
|
||||
WAIT UNTIL STATUS(8)='1';
|
||||
IF( STATUS(7 downto 0)/="0") THEN
|
||||
ASSERT false
|
||||
REPORT "Test Completed Successfully"
|
||||
SEVERITY NOTE;
|
||||
REPORT "Simulation Failed"
|
||||
SEVERITY FAILURE;
|
||||
ELSE
|
||||
ASSERT false
|
||||
REPORT "TEST PASS"
|
||||
SEVERITY NOTE;
|
||||
REPORT "Test Completed Successfully"
|
||||
SEVERITY FAILURE;
|
||||
END IF;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
EU4Kx32_synth_inst:ENTITY work.EU4Kx32_synth
|
||||
GENERIC MAP (C_ROM_SYNTH => 0)
|
||||
PORT MAP(
|
||||
CLK_IN => CLK,
|
||||
RESET_IN => RESET,
|
||||
STATUS => STATUS
|
||||
);
|
||||
|
||||
END ARCHITECTURE;
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Address Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: addr_gen.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Address Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.ALL;
|
||||
|
||||
ENTITY ADDR_GEN IS
|
||||
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
|
||||
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
|
||||
RST_INC : INTEGER := 0);
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RST : IN STD_LOGIC;
|
||||
EN : IN STD_LOGIC;
|
||||
LOAD :IN STD_LOGIC;
|
||||
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
|
||||
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
|
||||
);
|
||||
END ADDR_GEN;
|
||||
|
||||
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
|
||||
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
|
||||
BEGIN
|
||||
ADDR_OUT <= ADDR_TEMP;
|
||||
PROCESS(CLK)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLK)) THEN
|
||||
IF(RST='1') THEN
|
||||
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
|
||||
ELSE
|
||||
IF(EN='1') THEN
|
||||
IF(LOAD='1') THEN
|
||||
ADDR_TEMP <=LOAD_VALUE;
|
||||
ELSE
|
||||
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
|
||||
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
|
||||
ELSE
|
||||
ADDR_TEMP <= ADDR_TEMP + '1';
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
END ARCHITECTURE;
|
||||
|
|
@ -0,0 +1,426 @@
|
|||
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: bmg_stim_gen.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Stimulus Generation For SROM
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
USE IEEE.STD_LOGIC_MISC.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.ALL;
|
||||
USE work.BMG_TB_PKG.ALL;
|
||||
|
||||
|
||||
ENTITY REGISTER_LOGIC_SROM IS
|
||||
PORT(
|
||||
Q : OUT STD_LOGIC;
|
||||
CLK : IN STD_LOGIC;
|
||||
RST : IN STD_LOGIC;
|
||||
D : IN STD_LOGIC
|
||||
);
|
||||
END REGISTER_LOGIC_SROM;
|
||||
|
||||
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
|
||||
SIGNAL Q_O : STD_LOGIC :='0';
|
||||
BEGIN
|
||||
Q <= Q_O;
|
||||
FF_BEH: PROCESS(CLK)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLK)) THEN
|
||||
IF(RST /= '0' ) THEN
|
||||
Q_O <= '0';
|
||||
ELSE
|
||||
Q_O <= D;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
END REGISTER_ARCH;
|
||||
|
||||
LIBRARY STD;
|
||||
USE STD.TEXTIO.ALL;
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
--USE IEEE.NUMERIC_STD.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
USE IEEE.STD_LOGIC_MISC.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.ALL;
|
||||
USE work.BMG_TB_PKG.ALL;
|
||||
|
||||
|
||||
ENTITY BMG_STIM_GEN IS
|
||||
GENERIC ( C_ROM_SYNTH : INTEGER := 0
|
||||
);
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RST : IN STD_LOGIC;
|
||||
ADDRA: OUT STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
|
||||
DATA_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0); --OUTPUT VECTOR
|
||||
STATUS : OUT STD_LOGIC:= '0'
|
||||
);
|
||||
END BMG_STIM_GEN;
|
||||
|
||||
|
||||
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
|
||||
|
||||
FUNCTION hex_to_std_logic_vector(
|
||||
hex_str : STRING;
|
||||
return_width : INTEGER)
|
||||
RETURN STD_LOGIC_VECTOR IS
|
||||
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
|
||||
DOWNTO 0);
|
||||
|
||||
BEGIN
|
||||
tmp := (OTHERS => '0');
|
||||
FOR i IN 1 TO hex_str'LENGTH LOOP
|
||||
CASE hex_str((hex_str'LENGTH+1)-i) IS
|
||||
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
|
||||
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
|
||||
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
|
||||
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
|
||||
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
|
||||
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
|
||||
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
|
||||
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
|
||||
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
|
||||
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
|
||||
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
|
||||
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
|
||||
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
|
||||
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
|
||||
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
|
||||
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
|
||||
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
|
||||
END CASE;
|
||||
END LOOP;
|
||||
RETURN tmp(return_width-1 DOWNTO 0);
|
||||
END hex_to_std_logic_vector;
|
||||
|
||||
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DO_READ : STD_LOGIC := '0';
|
||||
SIGNAL CHECK_DATA : STD_LOGIC := '0';
|
||||
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
|
||||
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
|
||||
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
|
||||
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0):= hex_to_std_logic_vector("0",32);
|
||||
|
||||
BEGIN
|
||||
|
||||
|
||||
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
|
||||
|
||||
type mem_type is array (4095 downto 0) of std_logic_vector(31 downto 0);
|
||||
|
||||
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
|
||||
VARIABLE temp_return : STD_LOGIC;
|
||||
BEGIN
|
||||
IF (input = '0') THEN
|
||||
temp_return := '0';
|
||||
ELSE
|
||||
temp_return := '1';
|
||||
END IF;
|
||||
RETURN temp_return;
|
||||
END bit_to_sl;
|
||||
|
||||
function char_to_std_logic (
|
||||
char : in character)
|
||||
return std_logic is
|
||||
|
||||
variable data : std_logic;
|
||||
|
||||
begin
|
||||
if char = '0' then
|
||||
data := '0';
|
||||
|
||||
elsif char = '1' then
|
||||
data := '1';
|
||||
|
||||
elsif char = 'X' then
|
||||
data := 'X';
|
||||
|
||||
else
|
||||
assert false
|
||||
report "character which is not '0', '1' or 'X'."
|
||||
severity warning;
|
||||
|
||||
data := 'U';
|
||||
end if;
|
||||
|
||||
return data;
|
||||
|
||||
end char_to_std_logic;
|
||||
|
||||
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
|
||||
C_LOAD_INIT_FILE : INTEGER ;
|
||||
C_INIT_FILE_NAME : STRING ;
|
||||
DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
width : INTEGER;
|
||||
depth : INTEGER)
|
||||
RETURN mem_type IS
|
||||
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
|
||||
FILE init_file : TEXT;
|
||||
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
|
||||
VARIABLE bitline : LINE;
|
||||
variable bitsgood : boolean := true;
|
||||
variable bitchar : character;
|
||||
VARIABLE i : INTEGER;
|
||||
VARIABLE j : INTEGER;
|
||||
BEGIN
|
||||
|
||||
--Display output message indicating that the behavioral model is being
|
||||
--initialized
|
||||
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
|
||||
|
||||
-- Setup the default data
|
||||
-- Default data is with respect to write_port_A and may be wider
|
||||
-- or narrower than init_return width. The following loops map
|
||||
-- default data into the memory
|
||||
IF (C_USE_DEFAULT_DATA=1) THEN
|
||||
FOR i IN 0 TO depth-1 LOOP
|
||||
init_return(i) := DEFAULT_DATA;
|
||||
END LOOP;
|
||||
END IF;
|
||||
|
||||
-- Read in the .mif file
|
||||
-- The init data is formatted with respect to write port A dimensions.
|
||||
-- The init_return vector is formatted with respect to minimum width and
|
||||
-- maximum depth; the following loops map the .mif file into the memory
|
||||
IF (C_LOAD_INIT_FILE=1) THEN
|
||||
file_open(init_file, C_INIT_FILE_NAME, read_mode);
|
||||
i := 0;
|
||||
WHILE (i < depth AND NOT endfile(init_file)) LOOP
|
||||
mem_vector := (OTHERS => '0');
|
||||
readline(init_file, bitline);
|
||||
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
|
||||
|
||||
FOR j IN 0 TO width-1 LOOP
|
||||
read(bitline,bitchar,bitsgood);
|
||||
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
|
||||
END LOOP;
|
||||
i := i + 1;
|
||||
END LOOP;
|
||||
file_close(init_file);
|
||||
END IF;
|
||||
RETURN init_return;
|
||||
|
||||
END FUNCTION;
|
||||
|
||||
|
||||
--***************************************************************
|
||||
-- convert bit to STD_LOGIC
|
||||
--***************************************************************
|
||||
|
||||
constant c_init : mem_type := init_memory(0,
|
||||
1,
|
||||
"EU4Kx32.mif",
|
||||
DEFAULT_DATA,
|
||||
32,
|
||||
4096);
|
||||
|
||||
|
||||
constant rom : mem_type := c_init;
|
||||
BEGIN
|
||||
|
||||
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
|
||||
|
||||
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
|
||||
GENERIC MAP( C_MAX_DEPTH =>4096 )
|
||||
|
||||
PORT MAP(
|
||||
CLK => CLK,
|
||||
RST => RST,
|
||||
EN => CHECK_DATA_2R,
|
||||
LOAD => '0',
|
||||
LOAD_VALUE => ZERO,
|
||||
ADDR_OUT => CHECK_READ_ADDR
|
||||
);
|
||||
|
||||
|
||||
PROCESS(CLK)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLK)) THEN
|
||||
IF(CHECK_DATA_2R ='1') THEN
|
||||
IF(EXPECTED_DATA = DATA_IN) THEN
|
||||
STATUS<='0';
|
||||
ELSE
|
||||
STATUS <= '1';
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
END GENERATE;
|
||||
-- Simulatable ROM
|
||||
|
||||
--Synthesizable ROM
|
||||
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
|
||||
PROCESS(CLK)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLK)) THEN
|
||||
IF(CHECK_DATA_2R='1') THEN
|
||||
IF(DATA_IN=DEFAULT_DATA) THEN
|
||||
STATUS <= '0';
|
||||
ELSE
|
||||
STATUS <= '1';
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
END GENERATE;
|
||||
|
||||
|
||||
READ_ADDR_INT(11 DOWNTO 0) <= READ_ADDR(11 DOWNTO 0);
|
||||
ADDRA <= READ_ADDR_INT ;
|
||||
|
||||
CHECK_DATA <= DO_READ;
|
||||
|
||||
|
||||
|
||||
|
||||
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
|
||||
GENERIC MAP( C_MAX_DEPTH => 4096 )
|
||||
|
||||
PORT MAP(
|
||||
CLK => CLK,
|
||||
RST => RST,
|
||||
EN => DO_READ,
|
||||
LOAD => '0',
|
||||
LOAD_VALUE => ZERO,
|
||||
ADDR_OUT => READ_ADDR
|
||||
);
|
||||
|
||||
RD_PROCESS: PROCESS (CLK)
|
||||
BEGIN
|
||||
IF (RISING_EDGE(CLK)) THEN
|
||||
IF(RST='1') THEN
|
||||
DO_READ <= '0';
|
||||
ELSE
|
||||
DO_READ <= '1';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
|
||||
BEGIN
|
||||
DFF_RIGHT: IF I=0 GENERATE
|
||||
BEGIN
|
||||
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
|
||||
PORT MAP(
|
||||
Q => DO_READ_REG(0),
|
||||
CLK =>CLK,
|
||||
RST=>RST,
|
||||
D =>DO_READ
|
||||
);
|
||||
END GENERATE DFF_RIGHT;
|
||||
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
|
||||
BEGIN
|
||||
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
|
||||
PORT MAP(
|
||||
Q => DO_READ_REG(I),
|
||||
CLK =>CLK,
|
||||
RST=>RST,
|
||||
D =>DO_READ_REG(I-1)
|
||||
);
|
||||
END GENERATE DFF_OTHERS;
|
||||
END GENERATE BEGIN_SHIFT_REG;
|
||||
|
||||
|
||||
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
|
||||
PORT MAP(
|
||||
Q => CHECK_DATA_2R,
|
||||
CLK =>CLK,
|
||||
RST=>RST,
|
||||
D =>CHECK_DATA_R
|
||||
);
|
||||
|
||||
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
|
||||
PORT MAP(
|
||||
Q => CHECK_DATA_R,
|
||||
CLK =>CLK,
|
||||
RST=>RST,
|
||||
D =>CHECK_DATA
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
END ARCHITECTURE;
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,200 @@
|
|||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Testbench Package
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: bmg_tb_pkg.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- BMG Testbench Package files
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
PACKAGE BMG_TB_PKG IS
|
||||
|
||||
FUNCTION DIVROUNDUP (
|
||||
DATA_VALUE : INTEGER;
|
||||
DIVISOR : INTEGER)
|
||||
RETURN INTEGER;
|
||||
------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STD_LOGIC_VECTOR;
|
||||
FALSE_CASE : STD_LOGIC_VECTOR)
|
||||
RETURN STD_LOGIC_VECTOR;
|
||||
------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STRING;
|
||||
FALSE_CASE :STRING)
|
||||
RETURN STRING;
|
||||
------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STD_LOGIC;
|
||||
FALSE_CASE :STD_LOGIC)
|
||||
RETURN STD_LOGIC;
|
||||
------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : INTEGER;
|
||||
FALSE_CASE : INTEGER)
|
||||
RETURN INTEGER;
|
||||
------------------------
|
||||
FUNCTION LOG2ROUNDUP (
|
||||
DATA_VALUE : INTEGER)
|
||||
RETURN INTEGER;
|
||||
|
||||
END BMG_TB_PKG;
|
||||
|
||||
PACKAGE BODY BMG_TB_PKG IS
|
||||
|
||||
FUNCTION DIVROUNDUP (
|
||||
DATA_VALUE : INTEGER;
|
||||
DIVISOR : INTEGER)
|
||||
RETURN INTEGER IS
|
||||
VARIABLE DIV : INTEGER;
|
||||
BEGIN
|
||||
DIV := DATA_VALUE/DIVISOR;
|
||||
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
|
||||
DIV := DIV+1;
|
||||
END IF;
|
||||
RETURN DIV;
|
||||
END DIVROUNDUP;
|
||||
---------------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STD_LOGIC_VECTOR;
|
||||
FALSE_CASE : STD_LOGIC_VECTOR)
|
||||
RETURN STD_LOGIC_VECTOR IS
|
||||
BEGIN
|
||||
IF NOT CONDITION THEN
|
||||
RETURN FALSE_CASE;
|
||||
ELSE
|
||||
RETURN TRUE_CASE;
|
||||
END IF;
|
||||
END IF_THEN_ELSE;
|
||||
---------------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STD_LOGIC;
|
||||
FALSE_CASE : STD_LOGIC)
|
||||
RETURN STD_LOGIC IS
|
||||
BEGIN
|
||||
IF NOT CONDITION THEN
|
||||
RETURN FALSE_CASE;
|
||||
ELSE
|
||||
RETURN TRUE_CASE;
|
||||
END IF;
|
||||
END IF_THEN_ELSE;
|
||||
---------------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : INTEGER;
|
||||
FALSE_CASE : INTEGER)
|
||||
RETURN INTEGER IS
|
||||
VARIABLE RETVAL : INTEGER := 0;
|
||||
BEGIN
|
||||
IF CONDITION=FALSE THEN
|
||||
RETVAL:=FALSE_CASE;
|
||||
ELSE
|
||||
RETVAL:=TRUE_CASE;
|
||||
END IF;
|
||||
RETURN RETVAL;
|
||||
END IF_THEN_ELSE;
|
||||
---------------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STRING;
|
||||
FALSE_CASE : STRING)
|
||||
RETURN STRING IS
|
||||
BEGIN
|
||||
IF NOT CONDITION THEN
|
||||
RETURN FALSE_CASE;
|
||||
ELSE
|
||||
RETURN TRUE_CASE;
|
||||
END IF;
|
||||
END IF_THEN_ELSE;
|
||||
-------------------------------
|
||||
FUNCTION LOG2ROUNDUP (
|
||||
DATA_VALUE : INTEGER)
|
||||
RETURN INTEGER IS
|
||||
VARIABLE WIDTH : INTEGER := 0;
|
||||
VARIABLE CNT : INTEGER := 1;
|
||||
BEGIN
|
||||
IF (DATA_VALUE <= 1) THEN
|
||||
WIDTH := 1;
|
||||
ELSE
|
||||
WHILE (CNT < DATA_VALUE) LOOP
|
||||
WIDTH := WIDTH + 1;
|
||||
CNT := CNT *2;
|
||||
END LOOP;
|
||||
END IF;
|
||||
RETURN WIDTH;
|
||||
END LOG2ROUNDUP;
|
||||
|
||||
END BMG_TB_PKG;
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wcfg new
|
||||
isim set radix hex
|
||||
wave add /EU4Kx32_tb/status
|
||||
wave add /EU4Kx32_tb/EU4Kx32_synth_inst/BMG_PORT/CLKA
|
||||
wave add /EU4Kx32_tb/EU4Kx32_synth_inst/BMG_PORT/ADDRA
|
||||
wave add /EU4Kx32_tb/EU4Kx32_synth_inst/BMG_PORT/DOUTA
|
||||
run all
|
||||
quit
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
::
|
||||
:: This file contains confidential and proprietary information
|
||||
:: of Xilinx, Inc. and is protected under U.S. and
|
||||
:: international copyright and other intellectual property
|
||||
:: laws.
|
||||
::
|
||||
:: DISCLAIMER
|
||||
:: This disclaimer is not a license and does not grant any
|
||||
:: rights to the materials distributed herewith. Except as
|
||||
:: otherwise provided in a valid license issued to you by
|
||||
:: Xilinx, and to the maximum extent permitted by applicable
|
||||
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
:: (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
:: including negligence, or under any other theory of
|
||||
:: liability) for any loss or damage of any kind or nature
|
||||
:: related to, arising under or in connection with these
|
||||
:: materials, including for any direct, or any indirect,
|
||||
:: special, incidental, or consequential loss or damage
|
||||
:: (including loss of data, profits, goodwill, or any type of
|
||||
:: loss or damage suffered as a result of any action brought
|
||||
:: by a third party) even if such damage or loss was
|
||||
:: reasonably foreseeable or Xilinx had been advised of the
|
||||
:: possibility of the same.
|
||||
::
|
||||
:: CRITICAL APPLICATIONS
|
||||
:: Xilinx products are not designed or intended to be fail-
|
||||
:: safe, or for use in any application requiring fail-safe
|
||||
:: performance, such as life-support or safety devices or
|
||||
:: systems, Class III medical devices, nuclear facilities,
|
||||
:: applications related to the deployment of airbags, or any
|
||||
:: other applications that could lead to death, personal
|
||||
:: injury, or severe property or environmental damage
|
||||
:: (individually and collectively, "Critical
|
||||
:: Applications"). Customer assumes the sole risk and
|
||||
:: liability of any use of Xilinx products in Critical
|
||||
:: Applications, subject only to applicable laws and
|
||||
:: regulations governing limitations on product liability.
|
||||
::
|
||||
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
:: PART OF THIS FILE AT ALL TIMES.
|
||||
::--------------------------------------------------------------------------------
|
||||
|
||||
cp ..\..\..\EU4Kx32.mif .
|
||||
|
||||
|
||||
echo "Compiling Core Verilog UNISIM/Behavioral model"
|
||||
vlogcomp -work work ..\..\..\EU4Kx32.v
|
||||
vhpcomp -work work ..\..\example_design\EU4Kx32_exdes.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
|
||||
vhpcomp -work work ..\bmg_tb_pkg.vhd
|
||||
vhpcomp -work work ..\addr_gen.vhd
|
||||
vhpcomp -work work ..\bmg_stim_gen.vhd
|
||||
vhpcomp -work work ..\EU4Kx32_synth.vhd
|
||||
vhpcomp -work work ..\EU4Kx32_tb.vhd
|
||||
|
||||
|
||||
vlogcomp -work work $XILINX\verilog\src\glbl.v
|
||||
fuse work.EU4Kx32_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o EU4Kx32_tb.exe
|
||||
|
||||
.\EU4Kx32_tb.exe -gui -tclbatch simcmds.tcl
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
#--------------------------------------------------------------------------------
|
||||
|
||||
vsim -c -do simulate_mti.do
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
cp ../../../EU4Kx32.mif .
|
||||
vlib work
|
||||
vmap work work
|
||||
|
||||
echo "Compiling Core Verilog UNISIM/Behavioral model"
|
||||
vlog -work work ../../../EU4Kx32.v
|
||||
vcom -work work ../../example_design/EU4Kx32_exdes.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
|
||||
vcom -work work ../bmg_tb_pkg.vhd
|
||||
vcom -work work ../addr_gen.vhd
|
||||
vcom -work work ../bmg_stim_gen.vhd
|
||||
vcom -work work ../EU4Kx32_synth.vhd
|
||||
vcom -work work ../EU4Kx32_tb.vhd
|
||||
|
||||
|
||||
vlog -work work $env(XILINX)/verilog/src/glbl.v
|
||||
vsim -novopt -t ps -L XilinxCoreLib_ver -L unisims_ver glbl work.EU4Kx32_tb
|
||||
|
||||
#Disabled waveform to save the disk space
|
||||
add log -r /*
|
||||
#Ignore integer warnings at time 0
|
||||
set StdArithNoWarnings 1
|
||||
run 0
|
||||
set StdArithNoWarnings 0
|
||||
|
||||
run -all
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
#--------------------------------------------------------------------------------
|
||||
|
||||
vsim -c -do simulate_mti.do
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
cp ../../../EU4Kx32.mif .
|
||||
|
||||
|
||||
mkdir work
|
||||
echo "Compiling Core Verilog UNISIM/Behavioral model"
|
||||
ncvlog -work work ../../../EU4Kx32.v
|
||||
ncvhdl -v93 -work work ../../example_design/EU4Kx32_exdes.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
|
||||
ncvhdl -v93 -work work ../bmg_tb_pkg.vhd
|
||||
ncvhdl -v93 -work work ../addr_gen.vhd
|
||||
ncvhdl -v93 -work work ../bmg_stim_gen.vhd
|
||||
ncvhdl -v93 -work work ../EU4Kx32_synth.vhd
|
||||
ncvhdl -v93 -work work ../EU4Kx32_tb.vhd
|
||||
|
||||
echo "Elaborating Design"
|
||||
ncvlog -work work $XILINX/verilog/src/glbl.v
|
||||
ncelab -access +rwc glbl work.EU4Kx32_tb
|
||||
|
||||
echo "Simulating Design"
|
||||
ncsim -gui -input @"simvision -input wave_ncsim.sv" work.EU4Kx32_tb
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
#!/bin/sh
|
||||
cp ../../../EU4Kx32.mif .
|
||||
rm -rf simv* csrc DVEfiles AN.DB
|
||||
|
||||
echo "Compiling Core Verilog UNISIM/Behavioral model"
|
||||
vlogan +v2k ../../../EU4Kx32.v
|
||||
vhdlan ../../example_design/EU4Kx32_exdes.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
vhdlan ../bmg_tb_pkg.vhd
|
||||
vhdlan ../addr_gen.vhd
|
||||
vhdlan ../bmg_stim_gen.vhd
|
||||
vhdlan ../EU4Kx32_synth.vhd
|
||||
vhdlan ../EU4Kx32_tb.vhd
|
||||
|
||||
echo "Elaborating Design"
|
||||
vlogan +v2k $XILINX/verilog/src/glbl.v
|
||||
vcs +vcs+lic+wait -debug EU4Kx32_tb glbl
|
||||
|
||||
echo "Simulating Design"
|
||||
./simv -ucli -i ucli_commands.key
|
||||
dve -session vcs_session.tcl
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
dump -file bmg_vcs.vpd -type VPD
|
||||
dump -add EU4Kx32_tb
|
||||
run
|
||||
quit
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#--------------------------------------------------------------------------------
|
||||
#--
|
||||
#-- BMG core Demo Testbench
|
||||
#--
|
||||
#--------------------------------------------------------------------------------
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
# Filename: vcs_session.tcl
|
||||
#
|
||||
# Description:
|
||||
# This is the VCS wave form file.
|
||||
#
|
||||
#--------------------------------------------------------------------------------
|
||||
if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } {
|
||||
gui_open_db -design V1 -file bmg_vcs.vpd -nosource
|
||||
}
|
||||
gui_set_precision 1ps
|
||||
gui_set_time_units 1ps
|
||||
|
||||
gui_open_window Wave
|
||||
gui_sg_create EU4Kx32_Group
|
||||
gui_list_add_group -id Wave.1 {EU4Kx32_Group}
|
||||
|
||||
gui_sg_addsignal -group EU4Kx32_Group /EU4Kx32_tb/status
|
||||
gui_sg_addsignal -group EU4Kx32_Group /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/CLKA
|
||||
gui_sg_addsignal -group EU4Kx32_Group /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/ADDRA
|
||||
gui_sg_addsignal -group EU4Kx32_Group /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/DOUTA
|
||||
|
||||
gui_zoom -window Wave.1 -full
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
|
||||
add wave -noupdate /EU4Kx32_tb/status
|
||||
add wave -noupdate /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/CLKA
|
||||
add wave -noupdate /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/ADDRA
|
||||
add wave -noupdate /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/DOUTA
|
||||
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
|
||||
configure wave -namecolwidth 197
|
||||
configure wave -valuecolwidth 106
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ps
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {9464063 ps}
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
window new WaveWindow -name "Waves for BMG Example Design"
|
||||
waveform using "Waves for BMG Example Design"
|
||||
|
||||
waveform add -signals /EU4Kx32_tb/status
|
||||
waveform add -signals /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/CLKA
|
||||
waveform add -signals /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/ADDRA
|
||||
waveform add -signals /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/DOUTA
|
||||
|
||||
console submit -using simulator -wait no "run"
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Random Number Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: random.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Random Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
|
||||
ENTITY RANDOM IS
|
||||
GENERIC ( WIDTH : INTEGER := 32;
|
||||
SEED : INTEGER :=2
|
||||
);
|
||||
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RST : IN STD_LOGIC;
|
||||
EN : IN STD_LOGIC;
|
||||
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
|
||||
);
|
||||
END RANDOM;
|
||||
|
||||
ARCHITECTURE BEHAVIORAL OF RANDOM IS
|
||||
BEGIN
|
||||
PROCESS(CLK)
|
||||
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
|
||||
VARIABLE TEMP : STD_LOGIC := '0';
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLK)) THEN
|
||||
IF(RST='1') THEN
|
||||
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
|
||||
ELSE
|
||||
IF(EN = '1') THEN
|
||||
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
|
||||
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
|
||||
RAND_TEMP(0) := TEMP;
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
RANDOM_NUM <= RAND_TEMP;
|
||||
END PROCESS;
|
||||
END ARCHITECTURE;
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wcfg new
|
||||
isim set radix hex
|
||||
wave add /EU4Kx32_tb/status
|
||||
wave add /EU4Kx32_tb/EU4Kx32_synth_inst/BMG_PORT/CLKA
|
||||
wave add /EU4Kx32_tb/EU4Kx32_synth_inst/BMG_PORT/ADDRA
|
||||
wave add /EU4Kx32_tb/EU4Kx32_synth_inst/BMG_PORT/DOUTA
|
||||
run all
|
||||
quit
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
::
|
||||
:: This file contains confidential and proprietary information
|
||||
:: of Xilinx, Inc. and is protected under U.S. and
|
||||
:: international copyright and other intellectual property
|
||||
:: laws.
|
||||
::
|
||||
:: DISCLAIMER
|
||||
:: This disclaimer is not a license and does not grant any
|
||||
:: rights to the materials distributed herewith. Except as
|
||||
:: otherwise provided in a valid license issued to you by
|
||||
:: Xilinx, and to the maximum extent permitted by applicable
|
||||
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
:: (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
:: including negligence, or under any other theory of
|
||||
:: liability) for any loss or damage of any kind or nature
|
||||
:: related to, arising under or in connection with these
|
||||
:: materials, including for any direct, or any indirect,
|
||||
:: special, incidental, or consequential loss or damage
|
||||
:: (including loss of data, profits, goodwill, or any type of
|
||||
:: loss or damage suffered as a result of any action brought
|
||||
:: by a third party) even if such damage or loss was
|
||||
:: reasonably foreseeable or Xilinx had been advised of the
|
||||
:: possibility of the same.
|
||||
::
|
||||
:: CRITICAL APPLICATIONS
|
||||
:: Xilinx products are not designed or intended to be fail-
|
||||
:: safe, or for use in any application requiring fail-safe
|
||||
:: performance, such as life-support or safety devices or
|
||||
:: systems, Class III medical devices, nuclear facilities,
|
||||
:: applications related to the deployment of airbags, or any
|
||||
:: other applications that could lead to death, personal
|
||||
:: injury, or severe property or environmental damage
|
||||
:: (individually and collectively, "Critical
|
||||
:: Applications"). Customer assumes the sole risk and
|
||||
:: liability of any use of Xilinx products in Critical
|
||||
:: Applications, subject only to applicable laws and
|
||||
:: regulations governing limitations on product liability.
|
||||
::
|
||||
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
:: PART OF THIS FILE AT ALL TIMES.
|
||||
::--------------------------------------------------------------------------------
|
||||
|
||||
cp ..\..\..\EU4Kx32.mif .
|
||||
|
||||
|
||||
vlogcomp -work work ..\..\implement\results\routed.v
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
|
||||
vhpcomp -work work ..\bmg_tb_pkg.vhd
|
||||
vhpcomp -work work ..\addr_gen.vhd
|
||||
vhpcomp -work work ..\bmg_stim_gen.vhd
|
||||
vhpcomp -work work ..\EU4Kx32_synth.vhd
|
||||
vhpcomp -work work ..\EU4Kx32_tb.vhd
|
||||
|
||||
fuse -L simprims_ver work.EU4Kx32_tb work.glbl -o EU4Kx32_tb.exe
|
||||
|
||||
.\EU4Kx32_tb.exe -sdftyp /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port=..\..\implement\results\routed.sdf -gui -tclbatch simcmds.tcl
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
#--------------------------------------------------------------------------------
|
||||
|
||||
vsim -c -do simulate_mti.do
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
set work work
|
||||
#--------------------------------------------------------------------------------
|
||||
cp ../../../EU4Kx32.mif .
|
||||
|
||||
vlib work
|
||||
vmap work work
|
||||
|
||||
echo "Compiling Core Verilog UNISIM/Behavioral model"
|
||||
vlog -work work ../../implement/results/routed.v
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
|
||||
vcom -work work ../bmg_tb_pkg.vhd
|
||||
vcom -work work ../addr_gen.vhd
|
||||
vcom -work work ../bmg_stim_gen.vhd
|
||||
vcom -work work ../EU4Kx32_synth.vhd
|
||||
vcom -work work ../EU4Kx32_tb.vhd
|
||||
|
||||
vsim -novopt -t ps -L simprims_ver +transport_int_delays -sdftyp /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port=../../implement/results/routed.sdf $work.EU4Kx32_tb $work.glbl -novopt
|
||||
|
||||
#Disabled waveform to save the disk space
|
||||
add log -r /*
|
||||
#Ignore integer warnings at time 0
|
||||
set StdArithNoWarnings 1
|
||||
run 0
|
||||
set StdArithNoWarnings 0
|
||||
|
||||
run -all
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
#--------------------------------------------------------------------------------
|
||||
|
||||
vsim -c -do simulate_mti.do
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
set work work
|
||||
#--------------------------------------------------------------------------------
|
||||
cp ../../../EU4Kx32.mif .
|
||||
mkdir work
|
||||
|
||||
|
||||
ncvlog -work work ../../implement/results/routed.v
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
|
||||
ncvhdl -v93 -work work ../bmg_tb_pkg.vhd
|
||||
ncvhdl -v93 -work work ../addr_gen.vhd
|
||||
ncvhdl -v93 -work work ../bmg_stim_gen.vhd
|
||||
ncvhdl -v93 -work work ../EU4Kx32_synth.vhd
|
||||
ncvhdl -v93 -work work ../EU4Kx32_tb.vhd
|
||||
|
||||
echo "Compiling SDF file"
|
||||
ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X
|
||||
|
||||
echo "Generating SDF command file"
|
||||
echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd
|
||||
echo 'SCOPE = :EU4Kx32_synth_inst:BMG_PORT,' >> sdf.cmd
|
||||
echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd
|
||||
|
||||
|
||||
echo "Elaborating Design"
|
||||
ncelab -access +rwc glbl -sdf_cmd_file sdf.cmd $work.EU4Kx32_tb
|
||||
|
||||
echo "Simulating Design"
|
||||
ncsim -gui -input @"simvision -input wave_ncsim.sv" $work.EU4Kx32_tb
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
#!/bin/sh
|
||||
cp ../../../EU4Kx32.mif .
|
||||
|
||||
rm -rf simv* csrc DVEfiles AN.DB
|
||||
|
||||
echo "Compiling Core Verilog UNISIM/Behavioral model"
|
||||
vlogan +v2k ../../implement/results/routed.v
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
vhdlan ../bmg_tb_pkg.vhd
|
||||
vhdlan ../addr_gen.vhd
|
||||
vhdlan ../bmg_stim_gen.vhd
|
||||
vhdlan ../EU4Kx32_synth.vhd
|
||||
vhdlan ../EU4Kx32_tb.vhd
|
||||
|
||||
|
||||
echo "Elaborating Design"
|
||||
vcs +neg_tchk +vcs+lic+wait -debug EU4Kx32_tb glbl
|
||||
|
||||
echo "Simulating Design"
|
||||
./simv -ucli -i ucli_commands.key
|
||||
dve -session vcs_session.tcl
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
dump -file bmg_vcs.vpd -type VPD
|
||||
dump -add EU4Kx32_tb
|
||||
run
|
||||
quit
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue