diff --git a/MCL64/PCB/65xx.dcm b/MCL64/PCB/65xx.dcm
new file mode 100644
index 0000000..bf567ce
--- /dev/null
+++ b/MCL64/PCB/65xx.dcm
@@ -0,0 +1,294 @@
+EESchema-DOCLIB  Version 2.0
+#
+$CMP 6502
+D 6502 8-bit NMOS Microprocessor, 64K, DIP-40
+K 6502 CPU uP
+F http://www.6502.org/documents/datasheets/mos/mos_6500_mpu_mar_1980.pdf
+$ENDCMP
+#
+$CMP 6503
+D 6503 8-bit NMOS Microprocessor, 4K, DIP-28
+K 6502 6503 CPU uP
+F http://www.6502.org/documents/datasheets/mos/mos_6500_mpu_mar_1980.pdf
+$ENDCMP
+#
+$CMP 6504
+D 6504 8-bit NMOS Microprocessor, 8K, DIP-28
+K 6502 6504 CPU uP
+F http://www.6502.org/documents/datasheets/mos/mos_6500_mpu_mar_1980.pdf
+$ENDCMP
+#
+$CMP 6505
+D 6505 8-bit NMOS Microprocessor, 4K, DIP-28
+K 6502 6505 CPU uP
+F http://www.6502.org/documents/datasheets/mos/mos_6500_mpu_mar_1980.pdf
+$ENDCMP
+#
+$CMP 6506
+D 6506 8-bit NMOS Microprocessor, 4K, DIP-28
+K 6502 6506 CPU uP
+F http://www.6502.org/documents/datasheets/mos/mos_6500_mpu_mar_1980.pdf
+$ENDCMP
+#
+$CMP 6507
+D 6507 8-bit NMOS Microprocessor, 8K, DIP-28
+K 6502 6507 CPU uP
+F http://www.6502.org/documents/datasheets/mos/mos_6500_mpu_mar_1980.pdf
+$ENDCMP
+#
+$CMP 6508
+D 6508 8-bit NMOS Microprocessor, 64K, 8-bit I/O Port, 256 Byte RAM, DIP-40
+K 6502 6508 CPU uP
+F http://www.6502.org/documents/datasheets/mos/mos_6508_mpu.pdf
+$ENDCMP
+#
+$CMP 6509
+D 6509 8-bit NMOS Microprocessor, 16x64K, DIP-40
+K 6502 6509 CPU uP
+F http://www.6502.org/documents/datasheets/mos/mos_6509_mpu.pdf
+$ENDCMP
+#
+$CMP 6510
+D 6510 8-bit NMOS Microprocessor, 64K, 6-bit I/O Port, DIP-40
+K 6502 6510 CPU uP
+F http://www.6502.org/documents/datasheets/mos/mos_6510_mpu.pdf
+$ENDCMP
+#
+$CMP 6510-1
+D 6510-1 8-bit NMOS/HMOS Microprocessor, 64K, 8-bit I/O Port, 2ϕ Clock, DIP-40
+K 6502 6510-1 CPU uP
+F http://www.6502.org/documents/datasheets/mos/mos_6510_mpu.pdf
+$ENDCMP
+#
+$CMP 6510-2
+D 6510-2 8-bit NMOS/HMOS Microprocessor, 64K, 8-bit I/O Port, DIP-40
+K 6502 6510-2 CPU uP
+F http://www.6502.org/documents/datasheets/mos/mos_6510_mpu.pdf
+$ENDCMP
+#
+$CMP 6510T
+D 6510T 8-bit NMOS/HMOS Microprocessor, 64K, 8-bit I/O Port, DIP-40
+K 6502 6510T CPU uP
+F http://www.6502.org/documents/datasheets/mos/mos_6510_mpu.pdf
+$ENDCMP
+#
+$CMP 6512
+D 6512 8-bit NMOS Microprocessor, 64K, 2ϕ Clock, DIP-40
+K 6502 6512 CPU uP
+F http://www.6502.org/documents/datasheets/mos/mos_6500_mpu_mar_1980.pdf
+$ENDCMP
+#
+$CMP 6513
+D 6513 8-bit NMOS Microprocessor, 4K, 2ϕ Clock, DIP-28
+K 6502 6513 CPU uP
+F http://www.6502.org/documents/datasheets/mos/mos_6500_mpu_mar_1980.pdf
+$ENDCMP
+#
+$CMP 6514
+D 6514 8-bit NMOS Microprocessor, 8K, 2ϕ Clock, DIP-28
+K 6502 6514 CPU uP
+F http://www.6502.org/documents/datasheets/mos/mos_6500_mpu_mar_1980.pdf
+$ENDCMP
+#
+$CMP 6515
+D 6515 8-bit NMOS Microprocessor, 4K, 2ϕ Clock, DIP-28
+K 6502 6515 CPU uP
+F http://www.6502.org/documents/datasheets/mos/mos_6500_mpu_mar_1980.pdf
+$ENDCMP
+#
+$CMP 6520
+D 6520 NMOS Peripheral Interface Adapter (PIA), 20-pin I/O, DIP-40
+K 6502 6520 PIA I/O
+F http://www.6502.org/documents/datasheets/mos/mos_6520.pdf
+$ENDCMP
+#
+$CMP 6522
+D 6522 NMOS Versatile Interface Adapter (VIA), 20-pin I/O, 2 Timer/Counters, DIP-40
+K 6502 6522 VIA I/O
+F http://www.6502.org/documents/datasheets/mos/mos_6522_preliminary_nov_1977.pdf
+$ENDCMP
+#
+$CMP 6523
+D 6523 NMOS Tri-Port Interface (TPI), 24-pin I/O, DIP-40
+K 6502 6523 TPI I/O
+F http://www.6502.org/documents/datasheets/mos/mos_6523_tpi_preliminary_nov_1980.pdf
+$ENDCMP
+#
+$CMP 6525
+D 6525 NMOS Tri-Port Interface (TPI), 24-pin I/O, DIP-40
+K 6502 6525 TPI I/O
+F http://www.6502.org/documents/datasheets/mos/mos_6525_tpi_preliminary.pdf
+$ENDCMP
+#
+$CMP 6526
+D 6526 NMOS Complex Interface Adapter (CIA), 20-pin I/O, 2 Timer/Counters, RTC, DIP-40
+K 6502 6526 CIA I/O
+F http://www.6502.org/documents/datasheets/mos/mos_6526_cia_preliminary_nov_1981.pdf
+$ENDCMP
+#
+$CMP 6529
+D 6529 NMOS Single Port Interface (SPI), 8-pin I/O, DIP-20
+K 6502 6529 SPI I/O
+F http://www.6502.org/documents/datasheets/mos/mos_6529_spi.pdf
+$ENDCMP
+#
+$CMP 6532
+D 6532 NMOS Memory, I/O and Timer Array (RIOT), 16-pin I/O, 1 Timer/Counter, 128-byte SRAM, DIP-40
+K 6502 6532 RIOT I/O RAM
+F http://www.6502.org/documents/datasheets/mos/mos_6532_riot.pdf
+$ENDCMP
+#
+$CMP 6545
+D 6545 NMOS CRT Controller (CRTC), DIP-40
+K 6502 6545 CRTC Video
+F http://www.6502.org/documents/datasheets/mos/mos_6545-1_crtc.pdf
+$ENDCMP
+#
+$CMP 6551
+D 6551 NMOS Asynchronous Communication Interface Adapter (ACIA), Serial UART, DIP-28
+K 6502 6551 ACIA UART
+F http://www.6502.org/documents/datasheets/mos/mos_6551_acia.pdf
+$ENDCMP
+#
+$CMP 6581
+D 6581 NMOS Sound Interface Device (SID), 3-Voice Sound Synthesizer, DIP-28
+K 6502 6581 SID Sound
+F http://www.6502.org/documents/datasheets/mos/mos_6581_sid.pdf
+$ENDCMP
+#
+$CMP 6582
+D 6582 NMOS Sound Interface Device (SID), 3-Voice Sound Synthesizer, DIP-28
+K 6502 6582 SID Sound
+F http://www.6502.org/documents/datasheets/mos/mos_6582_sid.pdf
+$ENDCMP
+#
+$CMP 65CE02
+D 65CE02 8-bit CMOS Microprocessor, 64K, DIP-40
+K 6502 65CE02 CPU uP
+F http://www.6502.org/documents/datasheets/mos/mos_65ce02_mpu.pdf
+$ENDCMP
+#
+$CMP 8500
+D 8500 8-bit HMOS Microprocessor, 64K, 6-bit I/O Port, DIP-40
+K 6502 8500 CPU uP
+$ENDCMP
+#
+$CMP 8502
+D 8502 8-bit HMOS Microprocessor, 64K, 7-bit I/O Port, DIP-40
+K 6502 8502 CPU uP
+$ENDCMP
+#
+$CMP 8580
+D 8580 HMOS Sound Interface Device (SID), 3-Voice Sound Synthesizer, DIP-28
+K 6502 8580 SID Sound
+$ENDCMP
+#
+$CMP W65C02SxP
+D W65C02S 8-bit CMOS General Purpose Microprocessor, DIP-40
+K 6502 CPU uP
+F http://www.westerndesigncenter.com/wdc/documentation/w65c02s.pdf
+$ENDCMP
+#
+$CMP W65C02SxPL
+D W65C02S 8-bit CMOS General Purpose Microprocessor, PLCC-44
+K 6502 CPU uP
+F http://www.westerndesigncenter.com/wdc/documentation/w65c02s.pdf
+$ENDCMP
+#
+$CMP W65C02SxQ
+D W65C02S 8-bit CMOS General Purpose Microprocessor, PQFP-44
+K 6502 CPU uP
+F http://www.westerndesigncenter.com/wdc/documentation/w65c02s.pdf
+$ENDCMP
+#
+$CMP W65C21NxP
+D W65C21N CMOS Peripheral Interface Adapter (PIA), 20-pin I/O, NMOS-Compatible, DIP-40
+K 6502 6521 PIA I/O
+F http://www.westerndesigncenter.com/wdc/documentation/w65c21.pdf
+$ENDCMP
+#
+$CMP W65C21NxPL
+D W65C21N CMOS Peripheral Interface Adapter (PIA), 20-pin I/O, NMOS-Compatible, PLCC-44
+K 6502 6521 PIA I/O
+F http://www.westerndesigncenter.com/wdc/documentation/w65c21.pdf
+$ENDCMP
+#
+$CMP W65C21SxP
+D W65C21S CMOS Peripheral Interface Adapter (PIA), 20-pin I/O, DIP-40
+K 6502 6521 PIA I/O
+F http://www.westerndesigncenter.com/wdc/documentation/w65c21.pdf
+$ENDCMP
+#
+$CMP W65C21SxPL
+D W65C21S CMOS Peripheral Interface Adapter (PIA), 20-pin I/O, PLCC-44
+K 6502 6521 PIA I/O
+F http://www.westerndesigncenter.com/wdc/documentation/w65c21.pdf
+$ENDCMP
+#
+$CMP W65C22NxP
+D W65C22N CMOS Versatile Interface Adapter (VIA), 20-pin I/O, 2 Timer/Counters, NMOS-Compatible, DIP-40
+K 6502 6522 VIA I/O
+F http://www.westerndesigncenter.com/wdc/documentation/w65c22.pdf
+$ENDCMP
+#
+$CMP W65C22NxPL
+D W65C22N CMOS Versatile Interface Adapter (VIA), 20-pin I/O, 2 Timer/Counters, NMOS-Compatible, PLCC-44
+K 6502 6522 VIA I/O
+F http://www.westerndesigncenter.com/wdc/documentation/w65c22.pdf
+$ENDCMP
+#
+$CMP W65C22SxP
+D W65C22S CMOS Versatile Interface Adapter (VIA), 20-pin I/O, 2 Timer/Counters, DIP-40
+K 6502 6522 VIA I/O
+F http://www.westerndesigncenter.com/wdc/documentation/w65c22.pdf
+$ENDCMP
+#
+$CMP W65C22SxPL
+D W65C22S CMOS Versatile Interface Adapter (VIA), 20-pin I/O, 2 Timer/Counters, PLCC-44
+K 6502 6522 VIA I/O
+F http://www.westerndesigncenter.com/wdc/documentation/w65c22.pdf
+$ENDCMP
+#
+$CMP W65C22SxQ
+D W65C22S CMOS Versatile Interface Adapter (VIA), 20-pin I/O, 2 Timer/Counters, PQFP-44
+K 6502 6522 VIA I/O
+F http://www.westerndesigncenter.com/wdc/documentation/w65c22.pdf
+$ENDCMP
+#
+$CMP W65C51NxP
+D W65C51N CMOS Asynchronous Communication Interface Adapter (ACIA), Serial UART, DIP-28
+K 6502 6551 ACIA UART
+F http://www.westerndesigncenter.com/wdc/documentation/w65c51n.pdf
+$ENDCMP
+#
+$CMP W65C51NxPL
+D W65C51N CMOS Asynchronous Communication Interface Adapter (ACIA), Serial UART, PLCC-28
+K 6502 6551 ACIA UART
+F http://www.6502.org/documents/datasheets/mos/mos_6551_acia.pdf
+$ENDCMP
+#
+$CMP W65C51NxQ
+D W65C51N CMOS Asynchronous Communication Interface Adapter (ACIA), Serial UART, PQFP-32
+K 6502 6551 ACIA UART
+F http://www.westerndesigncenter.com/wdc/documentation/w65c51n.pdf
+$ENDCMP
+#
+$CMP W65C816SxP
+D W65C816S 8/16-bit CMOS General Purpose Microprocessor, DIP-40
+K 6502 65816 CPU uP
+F http://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf
+$ENDCMP
+#
+$CMP W65C816SxPL
+D W65C816S 8/16-bit CMOS General Purpose Microprocessor, PLCC-44
+K 6502 65816 CPU uP
+F http://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf
+$ENDCMP
+#
+$CMP W65C816SxQ
+D W65C02S 8/16-bit CMOS General Purpose Microprocessor, PQFP-44
+K 6502 65816 CPU uP
+F http://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf
+$ENDCMP
+#
+#End Doc Library
\ No newline at end of file
diff --git a/MCL64/PCB/65xx.lib b/MCL64/PCB/65xx.lib
new file mode 100644
index 0000000..0436caa
--- /dev/null
+++ b/MCL64/PCB/65xx.lib
@@ -0,0 +1,1921 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# 6502
+#
+DEF 6502 U 0 40 Y Y 1 F N
+F0 "U" -400 1400 50 H V L CNN
+F1 "6502" 0 0 50 V V C CIB
+F2 "" 0 2000 50 H I C CNN
+F3 "" 0 1900 50 H I C CNN
+ALIAS 65CE02
+$FPLIST
+ DIP-40_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1350 400 -1350 0 1 0 f
+X VSS 1 -100 -1550 200 U 50 50 1 1 W
+X A1 10 600 1100 200 L 50 50 1 1 O
+X A2 11 600 1000 200 L 50 50 1 1 O
+X A3 12 600 900 200 L 50 50 1 1 O
+X A4 13 600 800 200 L 50 50 1 1 O
+X A5 14 600 700 200 L 50 50 1 1 O
+X A6 15 600 600 200 L 50 50 1 1 O
+X A7 16 600 500 200 L 50 50 1 1 O
+X A8 17 600 400 200 L 50 50 1 1 O
+X A9 18 600 300 200 L 50 50 1 1 O
+X A10 19 600 200 200 L 50 50 1 1 O
+X RDY 2 -600 -300 200 R 50 50 1 1 I
+X A11 20 600 100 200 L 50 50 1 1 O
+X VSS 21 0 -1550 200 U 50 50 1 1 W
+X A12 22 600 0 200 L 50 50 1 1 O
+X A13 23 600 -100 200 L 50 50 1 1 O
+X A14 24 600 -200 200 L 50 50 1 1 O
+X A15 25 600 -300 200 L 50 50 1 1 O
+X D7 26 600 -1200 200 L 50 50 1 1 B
+X D6 27 600 -1100 200 L 50 50 1 1 B
+X D5 28 600 -1000 200 L 50 50 1 1 B
+X D4 29 600 -900 200 L 50 50 1 1 B
+X ϕ1 3 -600 800 200 R 50 50 1 1 O
+X D3 30 600 -800 200 L 50 50 1 1 B
+X D2 31 600 -700 200 L 50 50 1 1 B
+X D1 32 600 -600 200 L 50 50 1 1 B
+X D0 33 600 -500 200 L 50 50 1 1 B
+X R/~W 34 -600 0 200 R 50 50 1 1 O
+X nc 35 -400 -1000 100 R 50 50 1 1 N NX
+X nc 36 -400 -1100 100 R 50 50 1 1 N NX
+X ϕ0 37 -600 900 200 R 50 50 1 1 I C
+X ~SO 38 -600 -1200 200 R 50 50 1 1 I L
+X ϕ2 39 -600 700 200 R 50 50 1 1 O
+X ~IRQ 4 -600 400 200 R 50 50 1 1 I L
+X ~RES 40 -600 1200 200 R 50 50 1 1 I L
+X nc 5 -400 -900 101 R 50 50 1 1 N NX
+X ~NMI 6 -600 300 200 R 50 50 1 1 I L
+X SYNC 7 -600 -700 200 R 50 50 1 1 O
+X VCC 8 0 1550 200 D 50 50 1 1 W
+X A0 9 600 1200 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 6503
+#
+DEF 6503 U 0 40 Y Y 1 F N
+F0 "U" -400 1400 50 H V L CNN
+F1 "6503" 0 0 50 V V C CIB
+F2 "" 0 2000 50 H I C CNN
+F3 "" 0 1900 50 H I C CNN
+$FPLIST
+ DIP-28_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1350 400 -1350 0 1 0 f
+X ~RES 1 -600 1200 200 R 50 50 1 1 I L
+X A4 10 600 800 200 L 50 50 1 1 O
+X A5 11 600 700 200 L 50 50 1 1 O
+X A6 12 600 600 200 L 50 50 1 1 O
+X A7 13 600 500 200 L 50 50 1 1 O
+X A8 14 600 400 200 L 50 50 1 1 O
+X A9 15 600 300 200 L 50 50 1 1 O
+X A10 16 600 200 200 L 50 50 1 1 O
+X A11 17 600 100 200 L 50 50 1 1 O
+X D7 18 600 -1200 200 L 50 50 1 1 B
+X D6 19 600 -1100 200 L 50 50 1 1 B
+X VSS 2 0 -1550 200 U 50 50 1 1 W
+X D5 20 600 -1000 200 L 50 50 1 1 B
+X D4 21 600 -900 200 L 50 50 1 1 B
+X D3 22 600 -800 200 L 50 50 1 1 B
+X D2 23 600 -700 200 L 50 50 1 1 B
+X D1 24 600 -600 200 L 50 50 1 1 B
+X D0 25 600 -500 200 L 50 50 1 1 B
+X R/~W 26 -600 0 200 R 50 50 1 1 O
+X ϕ0 27 -600 900 200 R 50 50 1 1 I C
+X ϕ2 28 -600 700 200 R 50 50 1 1 O
+X ~IRQ 3 -600 400 200 R 50 50 1 1 I L
+X ~NMI 4 -600 300 200 R 50 50 1 1 I L
+X VCC 5 0 1550 200 D 50 50 1 1 W
+X A0 6 600 1200 200 L 50 50 1 1 O
+X A1 7 600 1100 200 L 50 50 1 1 O
+X A2 8 600 1000 200 L 50 50 1 1 O
+X A3 9 600 900 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 6504
+#
+DEF 6504 U 0 40 Y Y 1 F N
+F0 "U" -400 1400 50 H V L CNN
+F1 "6504" 0 0 50 V V C CIB
+F2 "" 0 2000 50 H I C CNN
+F3 "" 0 1900 50 H I C CNN
+$FPLIST
+ DIP-28_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1350 400 -1350 0 1 0 f
+X ~RES 1 -600 1200 200 R 50 50 1 1 I L
+X A5 10 600 700 200 L 50 50 1 1 O
+X A6 11 600 600 200 L 50 50 1 1 O
+X A7 12 600 500 200 L 50 50 1 1 O
+X A8 13 600 400 200 L 50 50 1 1 O
+X A9 14 600 300 200 L 50 50 1 1 O
+X A10 15 600 200 200 L 50 50 1 1 O
+X A11 16 600 100 200 L 50 50 1 1 O
+X A12 17 600 0 200 L 50 50 1 1 O
+X D7 18 600 -1200 200 L 50 50 1 1 B
+X D6 19 600 -1100 200 L 50 50 1 1 B
+X VSS 2 0 -1550 200 U 50 50 1 1 W
+X D5 20 600 -1000 200 L 50 50 1 1 B
+X D4 21 600 -900 200 L 50 50 1 1 B
+X D3 22 600 -800 200 L 50 50 1 1 B
+X D2 23 600 -700 200 L 50 50 1 1 B
+X D1 24 600 -600 200 L 50 50 1 1 B
+X D0 25 600 -500 200 L 50 50 1 1 B
+X R/~W 26 -600 0 200 R 50 50 1 1 O
+X ϕ0 27 -600 900 200 R 50 50 1 1 I C
+X ϕ2 28 -600 700 200 R 50 50 1 1 O
+X ~IRQ 3 -600 400 200 R 50 50 1 1 I L
+X VCC 4 0 1550 200 D 50 50 1 1 W
+X A0 5 600 1200 200 L 50 50 1 1 O
+X A1 6 600 1100 200 L 50 50 1 1 O
+X A2 7 600 1000 200 L 50 50 1 1 O
+X A3 8 600 900 200 L 50 50 1 1 O
+X A4 9 600 800 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 6505
+#
+DEF 6505 U 0 40 Y Y 1 F N
+F0 "U" -400 1400 50 H V L CNN
+F1 "6505" 0 0 50 V V C CIB
+F2 "" 0 2000 50 H I C CNN
+F3 "" 0 1900 50 H I C CNN
+$FPLIST
+ DIP-28_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1350 400 -1350 0 1 0 f
+X ~RES 1 -600 1200 200 R 50 50 1 1 I L
+X A4 10 600 800 200 L 50 50 1 1 O
+X A5 11 600 700 200 L 50 50 1 1 O
+X A6 12 600 600 200 L 50 50 1 1 O
+X A7 13 600 500 200 L 50 50 1 1 O
+X A8 14 600 400 200 L 50 50 1 1 O
+X A9 15 600 300 200 L 50 50 1 1 O
+X A10 16 600 200 200 L 50 50 1 1 O
+X A11 17 600 100 200 L 50 50 1 1 O
+X D7 18 600 -1200 200 L 50 50 1 1 B
+X D6 19 600 -1100 200 L 50 50 1 1 B
+X VSS 2 0 -1550 200 U 50 50 1 1 W
+X D5 20 600 -1000 200 L 50 50 1 1 B
+X D4 21 600 -900 200 L 50 50 1 1 B
+X D3 22 600 -800 200 L 50 50 1 1 B
+X D2 23 600 -700 200 L 50 50 1 1 B
+X D1 24 600 -600 200 L 50 50 1 1 B
+X D0 25 600 -500 200 L 50 50 1 1 B
+X R/~W 26 -600 0 200 R 50 50 1 1 O
+X ϕ0 27 -600 900 200 R 50 50 1 1 I C
+X ϕ2 28 -600 700 200 R 50 50 1 1 O
+X RDY 3 -600 -300 200 R 50 50 1 1 I
+X ~IRQ 4 -600 400 200 R 50 50 1 1 I L
+X VCC 5 0 1550 200 D 50 50 1 1 W
+X A0 6 600 1200 200 L 50 50 1 1 O
+X A1 7 600 1100 200 L 50 50 1 1 O
+X A2 8 600 1000 200 L 50 50 1 1 O
+X A3 9 600 900 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 6506
+#
+DEF 6506 U 0 40 Y Y 1 F N
+F0 "U" -400 1400 50 H V L CNN
+F1 "6506" 0 0 50 V V C CIB
+F2 "" 0 2000 50 H I C CNN
+F3 "" 0 1900 50 H I C CNN
+$FPLIST
+ DIP-28_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1350 400 -1350 0 1 0 f
+X ~RES 1 -600 1200 200 R 50 50 1 1 I L
+X A4 10 600 800 200 L 50 50 1 1 O
+X A5 11 600 700 200 L 50 50 1 1 O
+X A6 12 600 600 200 L 50 50 1 1 O
+X A7 13 600 500 200 L 50 50 1 1 O
+X A8 14 600 400 200 L 50 50 1 1 O
+X A9 15 600 300 200 L 50 50 1 1 O
+X A10 16 600 200 200 L 50 50 1 1 O
+X A11 17 600 100 200 L 50 50 1 1 O
+X D7 18 600 -1200 200 L 50 50 1 1 B
+X D6 19 600 -1100 200 L 50 50 1 1 B
+X VSS 2 0 -1550 200 U 50 50 1 1 W
+X D5 20 600 -1000 200 L 50 50 1 1 B
+X D4 21 600 -900 200 L 50 50 1 1 B
+X D3 22 600 -800 200 L 50 50 1 1 B
+X D2 23 600 -700 200 L 50 50 1 1 B
+X D1 24 600 -600 200 L 50 50 1 1 B
+X D0 25 600 -500 200 L 50 50 1 1 B
+X R/~W 26 -600 0 200 R 50 50 1 1 O
+X ϕ0 27 -600 900 200 R 50 50 1 1 I C
+X ϕ2 28 -600 700 200 R 50 50 1 1 O
+X ϕ1 3 -600 800 200 R 50 50 1 1 O
+X ~IRQ 4 -600 400 200 R 50 50 1 1 I L
+X VCC 5 0 1550 200 D 50 50 1 1 W
+X A0 6 600 1200 200 L 50 50 1 1 O
+X A1 7 600 1100 200 L 50 50 1 1 O
+X A2 8 600 1000 200 L 50 50 1 1 O
+X A3 9 600 900 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 6507
+#
+DEF 6507 U 0 40 Y Y 1 F N
+F0 "U" -400 1400 50 H V L CNN
+F1 "6507" 0 0 50 V V C CIB
+F2 "" 0 2000 50 H I C CNN
+F3 "" 0 1900 50 H I C CNN
+$FPLIST
+ DIP-28_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1350 400 -1350 0 1 0 f
+X ~RES 1 -600 1200 200 R 50 50 1 1 I L
+X A5 10 600 700 200 L 50 50 1 1 O
+X A6 11 600 600 200 L 50 50 1 1 O
+X A7 12 600 500 200 L 50 50 1 1 O
+X A8 13 600 400 200 L 50 50 1 1 O
+X A9 14 600 300 200 L 50 50 1 1 O
+X A10 15 600 200 200 L 50 50 1 1 O
+X A11 16 600 100 200 L 50 50 1 1 O
+X A12 17 600 0 200 L 50 50 1 1 O
+X D7 18 600 -1200 200 L 50 50 1 1 B
+X D6 19 600 -1100 200 L 50 50 1 1 B
+X VSS 2 0 -1550 200 U 50 50 1 1 W
+X D5 20 600 -1000 200 L 50 50 1 1 B
+X D4 21 600 -900 200 L 50 50 1 1 B
+X D3 22 600 -800 200 L 50 50 1 1 B
+X D2 23 600 -700 200 L 50 50 1 1 B
+X D1 24 600 -600 200 L 50 50 1 1 B
+X D0 25 600 -500 200 L 50 50 1 1 B
+X R/~W 26 -600 0 200 R 50 50 1 1 O
+X ϕ0 27 -600 900 200 R 50 50 1 1 I C
+X ϕ2 28 -600 700 200 R 50 50 1 1 O
+X RDY 3 -600 -300 200 R 50 50 1 1 I
+X VCC 4 0 1550 200 D 50 50 1 1 W
+X A0 5 600 1200 200 L 50 50 1 1 O
+X A1 6 600 1100 200 L 50 50 1 1 O
+X A2 7 600 1000 200 L 50 50 1 1 O
+X A3 8 600 900 200 L 50 50 1 1 O
+X A4 9 600 800 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 6509
+#
+DEF 6509 U 0 40 Y Y 1 F N
+F0 "U" -400 1650 50 H V L CNN
+F1 "6509" 0 0 50 V V C CNN
+F2 "" 0 2450 50 H I C CNN
+F3 "" 0 2350 50 H I C CNN
+$FPLIST
+ DIP-40_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1600 400 -1600 0 1 0 f
+X RDY 1 -600 -50 200 R 50 50 1 1 I
+X A3 10 600 1150 200 L 50 50 1 1 T
+X A4 11 600 1050 200 L 50 50 1 1 T
+X A5 12 600 950 200 L 50 50 1 1 T
+X A6 13 600 850 200 L 50 50 1 1 T
+X A7 14 600 750 200 L 50 50 1 1 T
+X A8 15 600 650 200 L 50 50 1 1 T
+X A9 16 600 550 200 L 50 50 1 1 T
+X A10 17 600 450 200 L 50 50 1 1 T
+X A11 18 600 350 200 L 50 50 1 1 T
+X A12 19 600 250 200 L 50 50 1 1 T
+X ~IRQ 2 -600 650 200 R 50 50 1 1 I L
+X A13 20 600 150 200 L 50 50 1 1 T
+X VSS 21 0 -1800 200 U 50 50 1 1 W
+X A14 22 600 50 200 L 50 50 1 1 T
+X A15 23 600 -50 200 L 50 50 1 1 T
+X P3 24 600 -1450 200 L 50 50 1 1 O
+X P2 25 600 -1350 200 L 50 50 1 1 O
+X P1 26 600 -1250 200 L 50 50 1 1 O
+X P0 27 600 -1150 200 L 50 50 1 1 O
+X ~SO 28 -600 -950 200 R 50 50 1 1 I L
+X D7 29 600 -950 200 L 50 50 1 1 B
+X SYNC 3 -600 -450 200 R 50 50 1 1 O
+X D6 30 600 -850 200 L 50 50 1 1 B
+X D5 31 600 -750 200 L 50 50 1 1 B
+X D4 32 600 -650 200 L 50 50 1 1 B
+X D3 33 600 -550 200 L 50 50 1 1 B
+X D2 34 600 -450 200 L 50 50 1 1 B
+X D1 35 600 -350 200 L 50 50 1 1 B
+X D0 36 600 -250 200 L 50 50 1 1 B
+X R/~W 37 -600 250 200 R 50 50 1 1 T
+X ϕ0 38 -600 1150 200 R 50 50 1 1 I C
+X ~RES 39 -600 1450 200 R 50 50 1 1 I L
+X ~NMI 4 -600 550 200 R 50 50 1 1 I L
+X ϕ1 40 -600 1250 200 R 50 50 1 1 I C
+X AEC 5 -600 -150 200 R 50 50 1 1 I
+X VDD 6 0 1800 200 D 50 50 1 1 W
+X A0 7 600 1450 200 L 50 50 1 1 T
+X A1 8 600 1350 200 L 50 50 1 1 T
+X A2 9 600 1250 200 L 50 50 1 1 T
+ENDDRAW
+ENDDEF
+#
+# 6510
+#
+DEF 6510 U 0 40 Y Y 1 F N
+F0 "U" -400 1850 50 H V L CNN
+F1 "6510" 0 0 50 V V C CIB
+F2 "" 0 2450 50 H I C CNN
+F3 "" 0 2350 50 H I C CNN
+ALIAS 8500
+$FPLIST
+ DIP-40_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1800 400 -1800 0 1 0 f
+X ϕ0 1 -600 1350 200 R 50 50 1 1 I C
+X A3 10 600 1350 200 L 50 50 1 1 T
+X A4 11 600 1250 200 L 50 50 1 1 T
+X A5 12 600 1150 200 L 50 50 1 1 T
+X A6 13 600 1050 200 L 50 50 1 1 T
+X A7 14 600 950 200 L 50 50 1 1 T
+X A8 15 600 850 200 L 50 50 1 1 T
+X A9 16 600 750 200 L 50 50 1 1 T
+X A10 17 600 650 200 L 50 50 1 1 T
+X A11 18 600 550 200 L 50 50 1 1 T
+X A12 19 600 450 200 L 50 50 1 1 T
+X RDY 2 -600 150 200 R 50 50 1 1 I
+X A13 20 600 350 200 L 50 50 1 1 T
+X VSS 21 0 -2000 200 U 50 50 1 1 W
+X A14 22 600 250 200 L 50 50 1 1 T
+X A15 23 600 150 200 L 50 50 1 1 T
+X P5 24 600 -1450 200 L 50 50 1 1 B
+X P4 25 600 -1350 200 L 50 50 1 1 B
+X P3 26 600 -1250 200 L 50 50 1 1 B
+X P2 27 600 -1150 200 L 50 50 1 1 B
+X P1 28 600 -1050 200 L 50 50 1 1 B
+X P0 29 600 -950 200 L 50 50 1 1 B
+X ~IRQ 3 -600 850 200 R 50 50 1 1 I L
+X D7 30 600 -750 200 L 50 50 1 1 B
+X D6 31 600 -650 200 L 50 50 1 1 B
+X D5 32 600 -550 200 L 50 50 1 1 B
+X D4 33 600 -450 200 L 50 50 1 1 B
+X D3 34 600 -350 200 L 50 50 1 1 B
+X D2 35 600 -250 200 L 50 50 1 1 B
+X D1 36 600 -150 200 L 50 50 1 1 B
+X D0 37 600 -50 200 L 50 50 1 1 B
+X R/~W 38 -600 450 200 R 50 50 1 1 T
+X ϕ2 39 -600 1150 200 R 50 50 1 1 O
+X ~NMI 4 -600 750 200 R 50 50 1 1 I L
+X ~RES 40 -600 1650 200 R 50 50 1 1 I L
+X AEC 5 -600 50 200 R 50 50 1 1 I
+X VCC 6 0 2000 200 D 50 50 1 1 W
+X A0 7 600 1650 200 L 50 50 1 1 T
+X A1 8 600 1550 200 L 50 50 1 1 T
+X A2 9 600 1450 200 L 50 50 1 1 T
+ENDDRAW
+ENDDEF
+#
+# 6510-1
+#
+DEF 6510-1 U 0 40 Y Y 1 F N
+F0 "U" -400 1850 50 H V L CNN
+F1 "6510-1" 0 0 50 V V C CIB
+F2 "" 0 2450 50 H I C CNN
+F3 "" 0 2350 50 H I C CNN
+$FPLIST
+ DIP-40_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1800 400 -1800 0 1 0 f
+X ~RES 1 -600 1650 200 R 50 50 1 1 I L
+X A4 10 600 1250 200 L 50 50 1 1 T
+X A5 11 600 1150 200 L 50 50 1 1 T
+X A6 12 600 1050 200 L 50 50 1 1 T
+X A7 13 600 950 200 L 50 50 1 1 T
+X A8 14 600 850 200 L 50 50 1 1 T
+X A9 15 600 750 200 L 50 50 1 1 T
+X A10 16 600 650 200 L 50 50 1 1 T
+X A11 17 600 550 200 L 50 50 1 1 T
+X A12 18 600 450 200 L 50 50 1 1 T
+X A13 19 600 350 200 L 50 50 1 1 T
+X ϕ1 2 -600 1450 200 R 50 50 1 1 I C
+X VSS 20 0 -2000 200 U 50 50 1 1 W
+X A14 21 600 250 200 L 50 50 1 1 T
+X A15 22 600 150 200 L 50 50 1 1 T
+X P7 23 600 -1650 200 L 50 50 1 1 B
+X P6 24 600 -1550 200 L 50 50 1 1 B
+X P5 25 600 -1450 200 L 50 50 1 1 B
+X P4 26 600 -1350 200 L 50 50 1 1 B
+X P3 27 600 -1250 200 L 50 50 1 1 B
+X P2 28 600 -1150 200 L 50 50 1 1 B
+X P1 29 600 -1050 200 L 50 50 1 1 B
+X ~IRQ 3 -600 850 200 R 50 50 1 1 I L
+X P0 30 600 -950 200 L 50 50 1 1 B
+X D7 31 600 -750 200 L 50 50 1 1 B
+X D6 32 600 -650 200 L 50 50 1 1 B
+X D5 33 600 -550 200 L 50 50 1 1 B
+X D4 34 600 -450 200 L 50 50 1 1 B
+X D3 35 600 -350 200 L 50 50 1 1 B
+X D2 36 600 -250 200 L 50 50 1 1 B
+X D1 37 600 -150 200 L 50 50 1 1 B
+X D0 38 600 -50 200 L 50 50 1 1 B
+X R/~W 39 -600 450 200 R 50 50 1 1 T
+X AEC 4 -600 50 200 R 50 50 1 1 I
+X ϕ0 40 -600 1350 200 R 50 50 1 1 I C
+X VCC 5 0 2000 200 D 50 50 1 1 W
+X A0 6 600 1650 200 L 50 50 1 1 T
+X A1 7 600 1550 200 L 50 50 1 1 T
+X A2 8 600 1450 200 L 50 50 1 1 T
+X A3 9 600 1350 200 L 50 50 1 1 T
+ENDDRAW
+ENDDEF
+#
+# 6510-2
+#
+DEF 6510-2 U 0 40 Y Y 1 F N
+F0 "U" -400 1850 50 H V L CNN
+F1 "6510-2" 0 0 50 V V C CIB
+F2 "" 0 2450 50 H I C CNN
+F3 "" 0 2350 50 H I C CNN
+ALIAS 6510T 6508
+$FPLIST
+ DIP-40_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1800 400 -1800 0 1 0 f
+X ~RES 1 -600 1650 200 R 50 50 1 1 I L
+X A4 10 600 1250 200 L 50 50 1 1 T
+X A5 11 600 1150 200 L 50 50 1 1 T
+X A6 12 600 1050 200 L 50 50 1 1 T
+X A7 13 600 950 200 L 50 50 1 1 T
+X A8 14 600 850 200 L 50 50 1 1 T
+X A9 15 600 750 200 L 50 50 1 1 T
+X A10 16 600 650 200 L 50 50 1 1 T
+X A11 17 600 550 200 L 50 50 1 1 T
+X A12 18 600 450 200 L 50 50 1 1 T
+X A13 19 600 350 200 L 50 50 1 1 T
+X ϕ0 2 -600 1350 200 R 50 50 1 1 I C
+X VSS 20 0 -2000 200 U 50 50 1 1 W
+X A14 21 600 250 200 L 50 50 1 1 T
+X A15 22 600 150 200 L 50 50 1 1 T
+X P7 23 600 -1650 200 L 50 50 1 1 B
+X P6 24 600 -1550 200 L 50 50 1 1 B
+X P5 25 600 -1450 200 L 50 50 1 1 B
+X P4 26 600 -1350 200 L 50 50 1 1 B
+X P3 27 600 -1250 200 L 50 50 1 1 B
+X P2 28 600 -1150 200 L 50 50 1 1 B
+X P1 29 600 -1050 200 L 50 50 1 1 B
+X ~IRQ 3 -600 850 200 R 50 50 1 1 I L
+X P0 30 600 -950 200 L 50 50 1 1 B
+X D7 31 600 -750 200 L 50 50 1 1 B
+X D6 32 600 -650 200 L 50 50 1 1 B
+X D5 33 600 -550 200 L 50 50 1 1 B
+X D4 34 600 -450 200 L 50 50 1 1 B
+X D3 35 600 -350 200 L 50 50 1 1 B
+X D2 36 600 -250 200 L 50 50 1 1 B
+X D1 37 600 -150 200 L 50 50 1 1 B
+X D0 38 600 -50 200 L 50 50 1 1 B
+X R/~W 39 -600 450 200 R 50 50 1 1 T
+X AEC 4 -600 50 200 R 50 50 1 1 I
+X ϕ2 40 -600 1150 200 R 50 50 1 1 O
+X VCC 5 0 2000 200 D 50 50 1 1 W
+X A0 6 600 1650 200 L 50 50 1 1 T
+X A1 7 600 1550 200 L 50 50 1 1 T
+X A2 8 600 1450 200 L 50 50 1 1 T
+X A3 9 600 1350 200 L 50 50 1 1 T
+ENDDRAW
+ENDDEF
+#
+# 6512
+#
+DEF 6512 U 0 40 Y Y 1 F N
+F0 "U" -400 1400 50 H V L CNN
+F1 "6512" 0 0 50 V V C CIB
+F2 "" 0 2000 50 H I C CNN
+F3 "" 0 1900 50 H I C CNN
+$FPLIST
+ DIP-40_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1350 400 -1350 0 1 0 f
+X VSS 1 -100 -1550 200 U 50 50 1 1 W
+X A1 10 600 1100 200 L 50 50 1 1 O
+X A2 11 600 1000 200 L 50 50 1 1 O
+X A3 12 600 900 200 L 50 50 1 1 O
+X A4 13 600 800 200 L 50 50 1 1 O
+X A5 14 600 700 200 L 50 50 1 1 O
+X A6 15 600 600 200 L 50 50 1 1 O
+X A7 16 600 500 200 L 50 50 1 1 O
+X A8 17 600 400 200 L 50 50 1 1 O
+X A9 18 600 300 200 L 50 50 1 1 O
+X A10 19 600 200 200 L 50 50 1 1 O
+X RDY 2 -600 -300 200 R 50 50 1 1 I
+X A11 20 600 100 200 L 50 50 1 1 O
+X VSS 21 100 -1550 200 U 50 50 1 1 W
+X A12 22 600 0 200 L 50 50 1 1 O
+X A13 23 600 -100 200 L 50 50 1 1 O
+X A14 24 600 -200 200 L 50 50 1 1 O
+X A15 25 600 -300 200 L 50 50 1 1 O
+X D7 26 600 -1200 200 L 50 50 1 1 B
+X D6 27 600 -1100 200 L 50 50 1 1 B
+X D5 28 600 -1000 200 L 50 50 1 1 B
+X D4 29 600 -900 200 L 50 50 1 1 B
+X ϕ1 3 -600 1000 200 R 50 50 1 1 I C
+X D3 30 600 -800 200 L 50 50 1 1 B
+X D2 31 600 -700 200 L 50 50 1 1 B
+X D1 32 600 -600 200 L 50 50 1 1 B
+X D0 33 600 -500 200 L 50 50 1 1 B
+X R/~W 34 -600 0 200 R 50 50 1 1 O
+X nc 35 -400 -1100 100 R 50 50 1 1 N NX
+X DBE 36 -600 -1000 200 R 50 50 1 1 I
+X ϕ0 37 -600 900 200 R 50 50 1 1 I C
+X ~SO 38 -600 -1200 200 R 50 50 1 1 I L
+X ϕ2 39 -600 700 200 R 50 50 1 1 O
+X ~IRQ 4 -600 400 200 R 50 50 1 1 I L
+X ~RES 40 -600 1200 200 R 50 50 1 1 I L
+X VSS 5 0 -1550 200 U 50 50 1 1 W
+X ~NMI 6 -600 300 200 R 50 50 1 1 I L
+X SYNC 7 -600 -700 200 R 50 50 1 1 O
+X VCC 8 0 1550 200 D 50 50 1 1 W
+X A0 9 600 1200 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 6513
+#
+DEF 6513 U 0 40 Y Y 1 F N
+F0 "U" -400 1400 50 H V L CNN
+F1 "6513" 0 0 50 V V C CIB
+F2 "" 0 2000 50 H I C CNN
+F3 "" 0 1900 50 H I C CNN
+$FPLIST
+ DIP-28_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1350 400 -1350 0 1 0 f
+X VSS 1 0 -1550 200 U 50 50 1 1 W
+X A4 10 600 800 200 L 50 50 1 1 O
+X A5 11 600 700 200 L 50 50 1 1 O
+X A6 12 600 600 200 L 50 50 1 1 O
+X A7 13 600 500 200 L 50 50 1 1 O
+X A8 14 600 400 200 L 50 50 1 1 O
+X A9 15 600 300 200 L 50 50 1 1 O
+X A10 16 600 200 200 L 50 50 1 1 O
+X A11 17 600 100 200 L 50 50 1 1 O
+X D7 18 600 -1200 200 L 50 50 1 1 B
+X D6 19 600 -1100 200 L 50 50 1 1 B
+X ϕ1 2 -600 1000 200 R 50 50 1 1 I C
+X D5 20 600 -1000 200 L 50 50 1 1 B
+X D4 21 600 -900 200 L 50 50 1 1 B
+X D3 22 600 -800 200 L 50 50 1 1 B
+X D2 23 600 -700 200 L 50 50 1 1 B
+X D1 24 600 -600 200 L 50 50 1 1 B
+X D0 25 600 -500 200 L 50 50 1 1 B
+X R/~W 26 -600 0 200 R 50 50 1 1 O
+X ϕ0 27 -600 900 200 R 50 50 1 1 I C
+X ~RES 28 -600 1200 200 R 50 50 1 1 I L
+X ~IRQ 3 -600 400 200 R 50 50 1 1 I L
+X ~NMI 4 -600 300 200 R 50 50 1 1 I L
+X VCC 5 0 1550 200 D 50 50 1 1 W
+X A0 6 600 1200 200 L 50 50 1 1 O
+X A1 7 600 1100 200 L 50 50 1 1 O
+X A2 8 600 1000 200 L 50 50 1 1 O
+X A3 9 600 900 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 6514
+#
+DEF 6514 U 0 40 Y Y 1 F N
+F0 "U" -400 1400 50 H V L CNN
+F1 "6514" 0 0 50 V V C CIB
+F2 "" 0 2000 50 H I C CNN
+F3 "" 0 1900 50 H I C CNN
+$FPLIST
+ DIP-28_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1350 400 -1350 0 1 0 f
+X VSS 1 0 -1550 200 U 50 50 1 1 W
+X A5 10 600 700 200 L 50 50 1 1 O
+X A6 11 600 600 200 L 50 50 1 1 O
+X A7 12 600 500 200 L 50 50 1 1 O
+X A8 13 600 400 200 L 50 50 1 1 O
+X A9 14 600 300 200 L 50 50 1 1 O
+X A10 15 600 200 200 L 50 50 1 1 O
+X A11 16 600 100 200 L 50 50 1 1 O
+X A12 17 600 0 200 L 50 50 1 1 O
+X D7 18 600 -1200 200 L 50 50 1 1 B
+X D6 19 600 -1100 200 L 50 50 1 1 B
+X ϕ1 2 -600 1000 200 R 50 50 1 1 I C
+X D5 20 600 -1000 200 L 50 50 1 1 B
+X D4 21 600 -900 200 L 50 50 1 1 B
+X D3 22 600 -800 200 L 50 50 1 1 B
+X D2 23 600 -700 200 L 50 50 1 1 B
+X D1 24 600 -600 200 L 50 50 1 1 B
+X D0 25 600 -500 200 L 50 50 1 1 B
+X R/~W 26 -600 0 200 R 50 50 1 1 O
+X ϕ0 27 -600 900 200 R 50 50 1 1 I C
+X ~RES 28 -600 1200 200 R 50 50 1 1 I L
+X ~IRQ 3 -600 400 200 R 50 50 1 1 I L
+X VCC 4 0 1550 200 D 50 50 1 1 W
+X A0 5 600 1200 200 L 50 50 1 1 O
+X A1 6 600 1100 200 L 50 50 1 1 O
+X A2 7 600 1000 200 L 50 50 1 1 O
+X A3 8 600 900 200 L 50 50 1 1 O
+X A4 9 600 800 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 6515
+#
+DEF 6515 U 0 40 Y Y 1 F N
+F0 "U" -400 1400 50 H V L CNN
+F1 "6515" 0 0 50 V V C CIB
+F2 "" 0 2000 50 H I C CNN
+F3 "" 0 1900 50 H I C CNN
+$FPLIST
+ DIP-28_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1350 400 -1350 0 1 0 f
+X VSS 1 0 -1550 200 U 50 50 1 1 W
+X A4 10 600 800 200 L 50 50 1 1 O
+X A5 11 600 700 200 L 50 50 1 1 O
+X A6 12 600 600 200 L 50 50 1 1 O
+X A7 13 600 500 200 L 50 50 1 1 O
+X A8 14 600 400 200 L 50 50 1 1 O
+X A9 15 600 300 200 L 50 50 1 1 O
+X A10 16 600 200 200 L 50 50 1 1 O
+X A11 17 600 100 200 L 50 50 1 1 O
+X D7 18 600 -1200 200 L 50 50 1 1 B
+X D6 19 600 -1100 200 L 50 50 1 1 B
+X RDY 2 -600 -300 200 R 50 50 1 1 I
+X D5 20 600 -1000 200 L 50 50 1 1 B
+X D4 21 600 -900 200 L 50 50 1 1 B
+X D3 22 600 -800 200 L 50 50 1 1 B
+X D2 23 600 -700 200 L 50 50 1 1 B
+X D1 24 600 -600 200 L 50 50 1 1 B
+X D0 25 600 -500 200 L 50 50 1 1 B
+X R/~W 26 -600 0 200 R 50 50 1 1 O
+X ϕ0 27 -600 900 200 R 50 50 1 1 I C
+X ~RES 28 -600 1200 200 R 50 50 1 1 I L
+X ϕ1 3 -600 1000 200 R 50 50 1 1 I C
+X ~IRQ 4 -600 400 200 R 50 50 1 1 I L
+X VCC 5 0 1550 200 D 50 50 1 1 W
+X A0 6 600 1200 200 L 50 50 1 1 O
+X A1 7 600 1100 200 L 50 50 1 1 O
+X A2 8 600 1000 200 L 50 50 1 1 O
+X A3 9 600 900 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 6520
+#
+DEF 6520 U 0 40 Y Y 1 F N
+F0 "U" -400 1300 50 H V L CNN
+F1 "6520" 0 0 50 V V C CIB
+F2 "" 0 150 50 H I C CNN
+F3 "" 0 150 50 H I C CNN
+ALIAS W65C21NxP W65C21SxP
+$FPLIST
+ DIP-40_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1250 400 -1250 0 1 0 f
+X VSS 1 0 -1450 200 U 50 50 1 1 W
+X PB0 10 600 -100 200 L 50 50 1 1 B
+X PB1 11 600 -200 200 L 50 50 1 1 B
+X PB2 12 600 -300 200 L 50 50 1 1 B
+X PB3 13 600 -400 200 L 50 50 1 1 B
+X PB4 14 600 -500 200 L 50 50 1 1 B
+X PB5 15 600 -600 200 L 50 50 1 1 B
+X PB6 16 600 -700 200 L 50 50 1 1 B
+X PB7 17 600 -800 200 L 50 50 1 1 B
+X CB1 18 600 -1000 200 L 50 50 1 1 I
+X CB2 19 600 -1100 200 L 50 50 1 1 B
+X PA0 2 600 1100 200 L 50 50 1 1 B
+X VCC 20 0 1450 200 D 50 50 1 1 W
+X R/~W 21 -600 -200 200 R 50 50 1 1 I
+X CS0 22 -600 500 200 R 50 50 1 1 I
+X ~CS2 23 -600 300 200 R 50 50 1 1 I L
+X CS1 24 -600 400 200 R 50 50 1 1 I
+X ϕ2 25 -600 1000 200 R 50 50 1 1 I C
+X D7 26 -600 -1100 200 R 50 50 1 1 B
+X D6 27 -600 -1000 200 R 50 50 1 1 B
+X D5 28 -600 -900 200 R 50 50 1 1 B
+X D4 29 -600 -800 200 R 50 50 1 1 B
+X PA1 3 600 1000 200 L 50 50 1 1 B
+X D3 30 -600 -700 200 R 50 50 1 1 B
+X D2 31 -600 -600 200 R 50 50 1 1 B
+X D1 32 -600 -500 200 R 50 50 1 1 B
+X D0 33 -600 -400 200 R 50 50 1 1 B
+X ~RES 34 -600 1100 200 R 50 50 1 1 I L
+X RS1 35 -600 0 200 R 50 50 1 1 I
+X RS0 36 -600 100 200 R 50 50 1 1 I
+X ~IRQB 37 -600 800 200 R 50 50 1 1 C V
+X ~IRQA 38 -600 700 200 R 50 50 1 1 C V
+X CA2 39 600 100 200 L 50 50 1 1 B
+X PA2 4 600 900 200 L 50 50 1 1 B
+X CA1 40 600 200 200 L 50 50 1 1 I
+X PA3 5 600 800 200 L 50 50 1 1 B
+X PA4 6 600 700 200 L 50 50 1 1 B
+X PA5 7 600 600 200 L 50 50 1 1 B
+X PA6 8 600 500 200 L 50 50 1 1 B
+X PA7 9 600 400 200 L 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# 6522
+#
+DEF 6522 U 0 40 Y Y 1 F N
+F0 "U" -400 1300 50 H V L CNN
+F1 "6522" 0 0 50 V V C CIB
+F2 "" 0 150 50 H I C CNN
+F3 "" 0 150 50 H I C CNN
+ALIAS W65C22NxP
+$FPLIST
+ DIP-40_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1250 400 -1250 0 1 0 f
+X VSS 1 0 -1450 200 U 50 50 1 1 W
+X PB0 10 600 -100 200 L 50 50 1 1 B
+X PB1 11 600 -200 200 L 50 50 1 1 B
+X PB2 12 600 -300 200 L 50 50 1 1 B
+X PB3 13 600 -400 200 L 50 50 1 1 B
+X PB4 14 600 -500 200 L 50 50 1 1 B
+X PB5 15 600 -600 200 L 50 50 1 1 B
+X PB6 16 600 -700 200 L 50 50 1 1 B
+X PB7 17 600 -800 200 L 50 50 1 1 B
+X CB1 18 600 -1000 200 L 50 50 1 1 I
+X CB2 19 600 -1100 200 L 50 50 1 1 B
+X PA0 2 600 1100 200 L 50 50 1 1 B
+X VCC 20 0 1450 200 D 50 50 1 1 W
+X ~IRQ 21 -600 800 200 R 50 50 1 1 C V
+X R/~W 22 -600 -200 200 R 50 50 1 1 I
+X ~CS2 23 -600 500 200 R 50 50 1 1 I L
+X CS1 24 -600 600 200 R 50 50 1 1 I
+X ϕ2 25 -600 1000 200 R 50 50 1 1 I C
+X D7 26 -600 -1100 200 R 50 50 1 1 B
+X D6 27 -600 -1000 200 R 50 50 1 1 B
+X D5 28 -600 -900 200 R 50 50 1 1 B
+X D4 29 -600 -800 200 R 50 50 1 1 B
+X PA1 3 600 1000 200 L 50 50 1 1 B
+X D3 30 -600 -700 200 R 50 50 1 1 B
+X D2 31 -600 -600 200 R 50 50 1 1 B
+X D1 32 -600 -500 200 R 50 50 1 1 B
+X D0 33 -600 -400 200 R 50 50 1 1 B
+X ~RES 34 -600 1100 200 R 50 50 1 1 I L
+X RS3 35 -600 0 200 R 50 50 1 1 I
+X RS2 36 -600 100 200 R 50 50 1 1 I
+X RS1 37 -600 200 200 R 50 50 1 1 I
+X RS0 38 -600 300 200 R 50 50 1 1 I
+X CA2 39 600 100 200 L 50 50 1 1 B
+X PA2 4 600 900 200 L 50 50 1 1 B
+X CA1 40 600 200 200 L 50 50 1 1 I
+X PA3 5 600 800 200 L 50 50 1 1 B
+X PA4 6 600 700 200 L 50 50 1 1 B
+X PA5 7 600 600 200 L 50 50 1 1 B
+X PA6 8 600 500 200 L 50 50 1 1 B
+X PA7 9 600 400 200 L 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# 6523
+#
+DEF 6523 U 0 40 Y Y 1 F N
+F0 "U" -400 1300 50 H V L CNN
+F1 "6523" 0 0 50 V V C CIB
+F2 "" 0 150 50 H I C CNN
+F3 "" 0 150 50 H I C CNN
+ALIAS 6525
+$FPLIST
+ DIP-40_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1250 400 -1250 0 1 0 f
+X VSS 1 0 -1450 200 U 50 50 1 1 W
+X PB0 10 600 350 200 L 50 50 1 1 B
+X PB1 11 600 250 200 L 50 50 1 1 B
+X PB2 12 600 150 200 L 50 50 1 1 B
+X PB3 13 600 50 200 L 50 50 1 1 B
+X PB4 14 600 -50 200 L 50 50 1 1 B
+X PB5 15 600 -150 200 L 50 50 1 1 B
+X PB6 16 600 -250 200 L 50 50 1 1 B
+X PB7 17 600 -350 200 L 50 50 1 1 B
+X ~CS 18 -600 500 200 R 50 50 1 1 I L
+X R/~W 19 -600 -200 200 R 50 50 1 1 I
+X PA0 2 600 1150 200 L 50 50 1 1 B
+X VDD 20 0 1450 200 D 50 50 1 1 W
+X ~RST 21 -600 1100 200 R 50 50 1 1 I L
+X RS2 22 -600 100 200 R 50 50 1 1 I
+X RS1 23 -600 200 200 R 50 50 1 1 I
+X RS0 24 -600 300 200 R 50 50 1 1 I
+X PC0 25 600 -450 200 L 50 50 1 1 B
+X PC1 26 600 -550 200 L 50 50 1 1 B
+X PC2 27 600 -650 200 L 50 50 1 1 B
+X PC3 28 600 -750 200 L 50 50 1 1 B
+X PC4 29 600 -850 200 L 50 50 1 1 B
+X PA1 3 600 1050 200 L 50 50 1 1 B
+X PC5 30 600 -950 200 L 50 50 1 1 B
+X PC6 31 600 -1050 200 L 50 50 1 1 B
+X PC7 32 600 -1150 200 L 50 50 1 1 B
+X D0 33 -600 -400 200 R 50 50 1 1 B
+X D1 34 -600 -500 200 R 50 50 1 1 B
+X D2 35 -600 -600 200 R 50 50 1 1 B
+X D3 36 -600 -700 200 R 50 50 1 1 B
+X D4 37 -600 -800 200 R 50 50 1 1 B
+X D5 38 -600 -900 200 R 50 50 1 1 B
+X D6 39 -600 -1000 200 R 50 50 1 1 B
+X PA2 4 600 950 200 L 50 50 1 1 B
+X D7 40 -600 -1100 200 R 50 50 1 1 B
+X PA3 5 600 850 200 L 50 50 1 1 B
+X PA4 6 600 750 200 L 50 50 1 1 B
+X PA5 7 600 650 200 L 50 50 1 1 B
+X PA6 8 600 550 200 L 50 50 1 1 B
+X PA7 9 600 450 200 L 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# 6526
+#
+DEF 6526 U 0 40 Y Y 1 F N
+F0 "U" -400 1300 50 H V L CNN
+F1 "6526" 0 0 50 V V C CIB
+F2 "" 0 150 50 H I C CNN
+F3 "" 0 150 50 H I C CNN
+$FPLIST
+ DIP-40_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1250 400 -1250 0 1 0 f
+X VSS 1 0 -1450 200 U 50 50 1 1 W
+X PB0 10 600 200 200 L 50 50 1 1 B
+X PB1 11 600 100 200 L 50 50 1 1 B
+X PB2 12 600 0 200 L 50 50 1 1 B
+X PB3 13 600 -100 200 L 50 50 1 1 B
+X PB4 14 600 -200 200 L 50 50 1 1 B
+X PB5 15 600 -300 200 L 50 50 1 1 B
+X PB6 16 600 -400 200 L 50 50 1 1 B
+X PB7 17 600 -500 200 L 50 50 1 1 B
+X ~PC 18 600 -800 200 L 50 50 1 1 O V
+X TOD 19 -600 900 200 R 50 50 1 1 I C
+X PA0 2 600 1100 200 L 50 50 1 1 B
+X VCC 20 0 1450 200 D 50 50 1 1 W
+X ~IRQ 21 -600 700 200 R 50 50 1 1 C V
+X R/~W 22 -600 -200 200 R 50 50 1 1 I
+X ~CS 23 -600 500 200 R 50 50 1 1 I L
+X ~FLAG 24 600 -700 200 L 50 50 1 1 I L
+X ϕ2 25 -600 1000 200 R 50 50 1 1 I C
+X D7 26 -600 -1100 200 R 50 50 1 1 B
+X D6 27 -600 -1000 200 R 50 50 1 1 B
+X D5 28 -600 -900 200 R 50 50 1 1 B
+X D4 29 -600 -800 200 R 50 50 1 1 B
+X PA1 3 600 1000 200 L 50 50 1 1 B
+X D3 30 -600 -700 200 R 50 50 1 1 B
+X D2 31 -600 -600 200 R 50 50 1 1 B
+X D1 32 -600 -500 200 R 50 50 1 1 B
+X D0 33 -600 -400 200 R 50 50 1 1 B
+X ~RES 34 -600 1100 200 R 50 50 1 1 I L
+X RS3 35 -600 0 200 R 50 50 1 1 I
+X RS2 36 -600 100 200 R 50 50 1 1 I
+X RS1 37 -600 200 200 R 50 50 1 1 I
+X RS0 38 -600 300 200 R 50 50 1 1 I
+X SP 39 600 -1100 200 L 50 50 1 1 B
+X PA2 4 600 900 200 L 50 50 1 1 B
+X CNT 40 600 -1000 200 L 50 50 1 1 B C
+X PA3 5 600 800 200 L 50 50 1 1 B
+X PA4 6 600 700 200 L 50 50 1 1 B
+X PA5 7 600 600 200 L 50 50 1 1 B
+X PA6 8 600 500 200 L 50 50 1 1 B
+X PA7 9 600 400 200 L 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# 6529
+#
+DEF 6529 U 0 40 Y Y 1 F N
+F0 "U" -400 700 50 H V L CNN
+F1 "6529" 0 0 50 V V C CIB
+F2 "" 0 -450 50 H I C CNN
+F3 "" 0 -450 50 H I C CNN
+$FPLIST
+ DIP-20_W7.62mm*
+$ENDFPLIST
+DRAW
+S -400 650 400 -650 0 1 0 f
+X R/~W 1 -600 -500 200 R 50 50 1 1 I
+X VSS 10 0 -850 200 U 50 50 1 1 W
+X D7 11 -600 -200 200 R 50 50 1 1 B
+X D6 12 -600 -100 200 R 50 50 1 1 B
+X D5 13 -600 0 200 R 50 50 1 1 B
+X D4 14 -600 100 200 R 50 50 1 1 B
+X D3 15 -600 200 200 R 50 50 1 1 B
+X D2 16 -600 300 200 R 50 50 1 1 B
+X D1 17 -600 400 200 R 50 50 1 1 B
+X D0 18 -600 500 200 R 50 50 1 1 B
+X ~CS 19 -600 -400 200 R 50 50 1 1 I L
+X P0 2 600 500 200 L 50 50 1 1 B
+X VDD 20 0 850 200 D 50 50 1 1 W
+X P1 3 600 400 200 L 50 50 1 1 B
+X P2 4 600 300 200 L 50 50 1 1 B
+X P3 5 600 200 200 L 50 50 1 1 B
+X P4 6 600 100 200 L 50 50 1 1 B
+X P5 7 600 0 200 L 50 50 1 1 B
+X P6 8 600 -100 200 L 50 50 1 1 B
+X P7 9 600 -200 200 L 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# 6532
+#
+DEF 6532 U 0 40 Y Y 1 F N
+F0 "U" -400 1500 50 H V L CNN
+F1 "6532" 0 0 50 V V C CIB
+F2 "" 0 350 50 H I C CNN
+F3 "" 0 350 50 H I C CNN
+$FPLIST
+ DIP-40_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 -1450 400 1450 1 1 0 f
+X VSS 1 0 -1650 200 U 50 50 1 1 W
+X PA2 10 600 1100 200 L 50 50 1 1 B
+X PA3 11 600 1000 200 L 50 50 1 1 B
+X PA4 12 600 900 200 L 50 50 1 1 B
+X PA5 13 600 800 200 L 50 50 1 1 B
+X PA6 14 600 700 200 L 50 50 1 1 B
+X PA7 15 600 600 200 L 50 50 1 1 B
+X PB7 16 600 -600 200 L 50 50 1 1 B
+X PB6 17 600 -500 200 L 50 50 1 1 B
+X PB5 18 600 -400 200 L 50 50 1 1 B
+X PB4 19 600 -300 200 L 50 50 1 1 B
+X A5 2 -600 0 200 R 50 50 1 1 I
+X VCC 20 0 1650 200 D 50 50 1 1 W
+X PB3 21 600 -200 200 L 50 50 1 1 B
+X PB2 22 600 -100 200 L 50 50 1 1 B
+X PB1 23 600 0 200 L 50 50 1 1 B
+X PB0 24 600 100 200 L 50 50 1 1 B
+X ~IRQ 25 -600 1000 200 R 50 50 1 1 C V
+X D7 26 -600 -1300 200 R 50 50 1 1 B
+X D6 27 -600 -1200 200 R 50 50 1 1 B
+X D5 28 -600 -1100 200 R 50 50 1 1 B
+X D4 29 -600 -1000 200 R 50 50 1 1 B
+X A4 3 -600 100 200 R 50 50 1 1 I
+X D3 30 -600 -900 200 R 50 50 1 1 B
+X D2 31 -600 -800 200 R 50 50 1 1 B
+X D1 32 -600 -700 200 R 50 50 1 1 B
+X D0 33 -600 -600 200 R 50 50 1 1 B
+X ~RES 34 -600 1300 200 R 50 50 1 1 I L
+X R/~W 35 -600 -400 200 R 50 50 1 1 I
+X ~RS 36 -600 -200 200 R 50 50 1 1 I
+X ~CS2 37 -600 700 200 R 50 50 1 1 I L
+X CS1 38 -600 800 200 R 50 50 1 1 I
+X ϕ2 39 -600 1200 200 R 50 50 1 1 I C
+X A3 4 -600 200 200 R 50 50 1 1 I
+X A6 40 -600 -100 200 R 50 50 1 1 I
+X A2 5 -600 300 200 R 50 50 1 1 I
+X A1 6 -600 400 200 R 50 50 1 1 I
+X A0 7 -600 500 200 R 50 50 1 1 I
+X PA0 8 600 1300 200 L 50 50 1 1 B
+X PA1 9 600 1200 200 L 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# 6545
+#
+DEF 6545 U 0 40 Y Y 1 F N
+F0 "U" -400 1550 50 H V L CNN
+F1 "6545" 0 0 50 V V C CIB
+F2 "" 0 400 50 H I C CNN
+F3 "" 0 400 50 H I C CNN
+$FPLIST
+ DIP-40_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1500 400 -1500 0 1 0 f
+X VSS 1 0 -1700 200 U 50 50 1 1 W
+X MA6 10 600 -50 200 L 50 50 1 1 O
+X MA7 11 600 -150 200 L 50 50 1 1 O
+X MA8 12 600 -250 200 L 50 50 1 1 O
+X MA9 13 600 -350 200 L 50 50 1 1 O
+X MA10 14 600 -450 200 L 50 50 1 1 O
+X MA11 15 600 -550 200 L 50 50 1 1 O
+X MA12 16 600 -650 200 L 50 50 1 1 O
+X MA13 17 600 -750 200 L 50 50 1 1 O
+X DSPL_EN 18 600 750 200 L 50 50 1 1 O
+X CURSOR 19 600 850 200 L 50 50 1 1 O
+X ~RES 2 -600 1350 200 R 50 50 1 1 I L
+X VCC 20 0 1700 200 D 50 50 1 1 W
+X CCLK 21 -600 1150 200 R 50 50 1 1 I C
+X R/~W 22 -600 50 200 R 50 50 1 1 I
+X ϕ2 23 -600 1250 200 R 50 50 1 1 I C
+X RS 24 -600 550 200 R 50 50 1 1 I
+X ~CS 25 -600 750 200 R 50 50 1 1 I L
+X D7 26 -600 -850 200 R 50 50 1 1 B
+X D6 27 -600 -750 200 R 50 50 1 1 B
+X D5 28 -600 -650 200 R 50 50 1 1 B
+X D4 29 -600 -550 200 R 50 50 1 1 B
+X LPEN 3 600 1350 200 L 50 50 1 1 I
+X D3 30 -600 -450 200 R 50 50 1 1 B
+X D2 31 -600 -350 200 R 50 50 1 1 B
+X D1 32 -600 -250 200 R 50 50 1 1 B
+X D0 33 -600 -150 200 R 50 50 1 1 B
+X RA4 34 600 -1350 200 L 50 50 1 1 O
+X RA3 35 600 -1250 200 L 50 50 1 1 O
+X RA2 36 600 -1150 200 L 50 50 1 1 O
+X RA1 37 600 -1050 200 L 50 50 1 1 O
+X RA0 38 600 -950 200 L 50 50 1 1 O
+X HSYNC 39 600 1150 200 L 50 50 1 1 O
+X MA0 4 600 550 200 L 50 50 1 1 O
+X VSYNC 40 600 1050 200 L 50 50 1 1 O
+X MA1 5 600 450 200 L 50 50 1 1 O
+X MA2 6 600 350 200 L 50 50 1 1 O
+X MA3 7 600 250 200 L 50 50 1 1 O
+X MA4 8 600 150 200 L 50 50 1 1 O
+X MA5 9 600 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 6551
+#
+DEF 6551 U 0 40 Y Y 1 F N
+F0 "U" -400 1300 50 H V L CNN
+F1 "6551" 0 0 50 V V C CIB
+F2 "" 0 150 50 H I C CNN
+F3 "" 0 150 50 H I C CNN
+ALIAS W65C51NxP W65C51NxPL
+$FPLIST
+ DIP-28_W15.24mm*
+ PLCC28
+$ENDFPLIST
+DRAW
+S -400 1250 400 -1250 0 1 0 f
+X VSS 1 0 -1450 200 U 50 50 1 1 W
+X TxD 10 600 300 200 L 50 50 1 1 O
+X ~DTR 11 600 -300 200 L 50 50 1 1 O V
+X RxD 12 600 200 200 L 50 50 1 1 I
+X RS0 13 -600 300 200 R 50 50 1 1 I
+X RS1 14 -600 200 200 R 50 50 1 1 I
+X VCC 15 0 1450 200 D 50 50 1 1 W
+X ~DCD 16 600 -600 200 L 50 50 1 1 I L
+X ~DSR 17 600 -400 200 L 50 50 1 1 I L
+X D0 18 -600 -400 200 R 50 50 1 1 B
+X D1 19 -600 -500 200 R 50 50 1 1 B
+X CS1 2 -600 600 200 R 50 50 1 1 I
+X D2 20 -600 -600 200 R 50 50 1 1 B
+X D3 21 -600 -700 200 R 50 50 1 1 B
+X D4 22 -600 -800 200 R 50 50 1 1 B
+X D5 23 -600 -900 200 R 50 50 1 1 B
+X D6 24 -600 -1000 200 R 50 50 1 1 B
+X D7 25 -600 -1100 200 R 50 50 1 1 B
+X ~IRQ 26 -600 800 200 R 50 50 1 1 C V
+X ϕ2 27 -600 1000 200 R 50 50 1 1 I C
+X R/~W 28 -600 -200 200 R 50 50 1 1 I
+X ~CS2 3 -600 500 200 R 50 50 1 1 I L
+X ~RES 4 -600 1100 200 R 50 50 1 1 I L
+X RxC 5 600 800 200 L 50 50 1 1 B C
+X XTAL1 6 600 1100 200 L 50 50 1 1 I C
+X XTAL2 7 600 1000 200 L 50 50 1 1 O
+X ~RTS 8 600 0 200 L 50 50 1 1 O V
+X ~CTS 9 600 -100 200 L 50 50 1 1 I L
+ENDDRAW
+ENDDEF
+#
+# 6581
+#
+DEF 6581 U 0 40 Y Y 1 F N
+F0 "U" -400 1300 50 H V L CNN
+F1 "6581" 0 0 50 V V C CIB
+F2 "" 0 150 50 H I C CNN
+F3 "" 0 150 50 H I C CNN
+$FPLIST
+ DIP-28_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1250 400 -1250 0 1 0 f
+X CAP1A 1 600 -600 200 L 50 50 1 1 P
+X A1 10 -600 300 200 R 50 50 1 1 I
+X A2 11 -600 200 200 R 50 50 1 1 I
+X A3 12 -600 100 200 R 50 50 1 1 I
+X A4 13 -600 0 200 R 50 50 1 1 I
+X GND 14 0 -1450 200 U 50 50 1 1 W
+X D0 15 -600 -400 200 R 50 50 1 1 B
+X D1 16 -600 -500 200 R 50 50 1 1 B
+X D2 17 -600 -600 200 R 50 50 1 1 B
+X D3 18 -600 -700 200 R 50 50 1 1 B
+X D4 19 -600 -800 200 R 50 50 1 1 B
+X CAP1B 2 600 -700 200 L 50 50 1 1 P
+X D5 20 -600 -900 200 R 50 50 1 1 B
+X D6 21 -600 -1000 200 R 50 50 1 1 B
+X D7 22 -600 -1100 200 R 50 50 1 1 B
+X POT_Y 23 600 0 200 L 50 50 1 1 I
+X POT_X 24 600 100 200 L 50 50 1 1 I
+X +5V 25 0 1450 200 D 50 50 1 1 W
+X EXT_IN 26 600 600 200 L 50 50 1 1 I
+X AUDIO_OUT 27 600 800 200 L 50 50 1 1 O
+X +12V 28 -100 1450 200 D 50 50 1 1 W
+X CAP2A 3 600 -1000 200 L 50 50 1 1 P
+X CAP2B 4 600 -1100 200 L 50 50 1 1 P
+X ~RES 5 -600 1100 200 R 50 50 1 1 I L
+X ϕ2 6 -600 1000 200 R 50 50 1 1 I C
+X R/~W 7 -600 -200 200 R 50 50 1 1 I
+X ~CS 8 -600 600 200 R 50 50 1 1 I L
+X A0 9 -600 400 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# 6582
+#
+DEF 6582 U 0 40 Y Y 1 F N
+F0 "U" -400 1300 50 H V L CNN
+F1 "6582" 0 0 50 V V C CIB
+F2 "" 0 150 50 H I C CNN
+F3 "" 0 150 50 H I C CNN
+ALIAS 8580
+$FPLIST
+ DIP-28_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1250 400 -1250 0 1 0 f
+X CAP1A 1 600 -600 200 L 50 50 1 1 P
+X A1 10 -600 300 200 R 50 50 1 1 I
+X A2 11 -600 200 200 R 50 50 1 1 I
+X A3 12 -600 100 200 R 50 50 1 1 I
+X A4 13 -600 0 200 R 50 50 1 1 I
+X GND 14 0 -1450 200 U 50 50 1 1 W
+X D0 15 -600 -400 200 R 50 50 1 1 B
+X D1 16 -600 -500 200 R 50 50 1 1 B
+X D2 17 -600 -600 200 R 50 50 1 1 B
+X D3 18 -600 -700 200 R 50 50 1 1 B
+X D4 19 -600 -800 200 R 50 50 1 1 B
+X CAP1B 2 600 -700 200 L 50 50 1 1 P
+X D5 20 -600 -900 200 R 50 50 1 1 B
+X D6 21 -600 -1000 200 R 50 50 1 1 B
+X D7 22 -600 -1100 200 R 50 50 1 1 B
+X POT_Y 23 600 0 200 L 50 50 1 1 I
+X POT_X 24 600 100 200 L 50 50 1 1 I
+X +5V 25 0 1450 200 D 50 50 1 1 W
+X EXT_IN 26 600 600 200 L 50 50 1 1 I
+X AUDIO_OUT 27 600 800 200 L 50 50 1 1 O
+X +9V 28 100 1450 200 D 50 50 1 1 W
+X CAP2A 3 600 -1000 200 L 50 50 1 1 P
+X CAP2B 4 600 -1100 200 L 50 50 1 1 P
+X ~RES 5 -600 1100 200 R 50 50 1 1 I L
+X ϕ2 6 -600 1000 200 R 50 50 1 1 I C
+X R/~W 7 -600 -200 200 R 50 50 1 1 I
+X ~CS 8 -600 600 200 R 50 50 1 1 I L
+X A0 9 -600 400 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# 8502
+#
+DEF 8502 U 0 40 Y Y 1 F N
+F0 "U" -400 1850 50 H V L CNN
+F1 "8502" 0 0 50 V V C CIB
+F2 "" 0 2450 50 H I C CNN
+F3 "" 0 2350 50 H I C CNN
+$FPLIST
+ DIP-40_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1800 400 -1800 0 1 0 f
+X ϕ0 1 -600 1350 200 R 50 50 1 1 I C
+X A3 10 600 1350 200 L 50 50 1 1 T
+X A4 11 600 1250 200 L 50 50 1 1 T
+X A5 12 600 1150 200 L 50 50 1 1 T
+X A6 13 600 1050 200 L 50 50 1 1 T
+X A7 14 600 950 200 L 50 50 1 1 T
+X A8 15 600 850 200 L 50 50 1 1 T
+X A9 16 600 750 200 L 50 50 1 1 T
+X A10 17 600 650 200 L 50 50 1 1 T
+X A11 18 600 550 200 L 50 50 1 1 T
+X A12 19 600 450 200 L 50 50 1 1 T
+X RDY 2 -600 150 200 R 50 50 1 1 I
+X A13 20 600 350 200 L 50 50 1 1 T
+X VSS 21 0 -2000 200 U 50 50 1 1 W
+X A14 22 600 250 200 L 50 50 1 1 T
+X A15 23 600 150 200 L 50 50 1 1 T
+X P6 24 600 -1550 200 L 50 50 1 1 W
+X P5 25 600 -1450 200 L 50 50 1 1 B
+X P4 26 600 -1350 200 L 50 50 1 1 B
+X P3 27 600 -1250 200 L 50 50 1 1 B
+X P2 28 600 -1150 200 L 50 50 1 1 B
+X P1 29 600 -1050 200 L 50 50 1 1 B
+X ~IRQ 3 -600 850 200 R 50 50 1 1 I L
+X P0 30 600 -950 200 L 50 50 1 1 B
+X D7 31 600 -750 200 L 50 50 1 1 B
+X D6 32 600 -650 200 L 50 50 1 1 B
+X D5 33 600 -550 200 L 50 50 1 1 B
+X D4 34 600 -450 200 L 50 50 1 1 B
+X D3 35 600 -350 200 L 50 50 1 1 B
+X D2 36 600 -250 200 L 50 50 1 1 B
+X D1 37 600 -150 200 L 50 50 1 1 B
+X D0 38 600 -50 200 L 50 50 1 1 B
+X R/~W 39 -600 450 200 R 50 50 1 1 T
+X ~NMI 4 -600 750 200 R 50 50 1 1 I L
+X ~RES 40 -600 1650 200 R 50 50 1 1 I L
+X AEC 5 -600 50 200 R 50 50 1 1 I
+X VDD 6 0 2000 200 D 50 50 1 1 W
+X A0 7 600 1650 200 L 50 50 1 1 T
+X A1 8 600 1550 200 L 50 50 1 1 T
+X A2 9 600 1450 200 L 50 50 1 1 T
+ENDDRAW
+ENDDEF
+#
+# W65C02SxP
+#
+DEF W65C02SxP U 0 40 Y Y 1 F N
+F0 "U" -400 1400 50 H V L CNN
+F1 "W65C02SxP" 0 0 50 V V C CIB
+F2 "" 0 2000 50 H I C CNN
+F3 "" 0 1900 50 H I C CNN
+$FPLIST
+ DIP-40_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1350 400 -1350 0 1 0 f
+X ~VP 1 -600 -800 200 R 50 50 1 1 O V
+X A1 10 600 1100 200 L 50 50 1 1 T
+X A2 11 600 1000 200 L 50 50 1 1 T
+X A3 12 600 900 200 L 50 50 1 1 T
+X A4 13 600 800 200 L 50 50 1 1 T
+X A5 14 600 700 200 L 50 50 1 1 T
+X A6 15 600 600 200 L 50 50 1 1 T
+X A7 16 600 500 200 L 50 50 1 1 T
+X A8 17 600 400 200 L 50 50 1 1 T
+X A9 18 600 300 200 L 50 50 1 1 T
+X A10 19 600 200 200 L 50 50 1 1 T
+X RDY 2 -600 -300 200 R 50 50 1 1 C
+X A11 20 600 100 200 L 50 50 1 1 T
+X VSS 21 0 -1550 200 U 50 50 1 1 W
+X A12 22 600 0 200 L 50 50 1 1 T
+X A13 23 600 -100 200 L 50 50 1 1 T
+X A14 24 600 -200 200 L 50 50 1 1 T
+X A15 25 600 -300 200 L 50 50 1 1 T
+X D7 26 600 -1200 200 L 50 50 1 1 B
+X D6 27 600 -1100 200 L 50 50 1 1 B
+X D5 28 600 -1000 200 L 50 50 1 1 B
+X D4 29 600 -900 200 L 50 50 1 1 B
+X ϕ1 3 -600 800 200 R 50 50 1 1 O
+X D3 30 600 -800 200 L 50 50 1 1 B
+X D2 31 600 -700 200 L 50 50 1 1 B
+X D1 32 600 -600 200 L 50 50 1 1 B
+X D0 33 600 -500 200 L 50 50 1 1 B
+X R/~W 34 -600 0 200 R 50 50 1 1 T
+X nc 35 -400 -1100 100 R 50 50 1 1 N NX
+X BE 36 -600 -400 200 R 50 50 1 1 I
+X ϕ0 37 -600 900 200 R 50 50 1 1 I C
+X ~SO 38 -600 -1200 200 R 50 50 1 1 I L
+X ϕ2 39 -600 700 200 R 50 50 1 1 O
+X ~IRQ 4 -600 400 200 R 50 50 1 1 I L
+X ~RES 40 -600 1200 200 R 50 50 1 1 I L
+X ~ML 5 -600 -900 200 R 50 50 1 1 O V
+X ~NMI 6 -600 300 200 R 50 50 1 1 I L
+X SYNC 7 -600 -700 200 R 50 50 1 1 O
+X VDD 8 0 1550 200 D 50 50 1 1 W
+X A0 9 600 1200 200 L 50 50 1 1 T
+ENDDRAW
+ENDDEF
+#
+# W65C02SxPL
+#
+DEF W65C02SxPL U 0 40 Y Y 1 F N
+F0 "U" -400 1400 50 H V L CNN
+F1 "W65C02SxPL" 0 0 50 V V C CIB
+F2 "" 0 2000 50 H I C CNN
+F3 "" 0 1900 50 H I C CNN
+$FPLIST
+ PLCC44
+$ENDFPLIST
+DRAW
+S -400 1350 400 -1350 0 1 0 f
+X VSS 1 -100 -1550 200 U 50 50 1 1 W
+X A0 10 600 1200 200 L 50 50 1 1 T
+X A1 11 600 1100 200 L 50 50 1 1 T
+X nc 12 -400 -1000 100 R 50 50 1 1 N NX
+X A2 13 600 1000 200 L 50 50 1 1 T
+X A3 14 600 900 200 L 50 50 1 1 T
+X A4 15 600 800 200 L 50 50 1 1 T
+X A5 16 600 700 200 L 50 50 1 1 T
+X A6 17 600 600 200 L 50 50 1 1 T
+X A7 18 600 500 200 L 50 50 1 1 T
+X A8 19 600 400 200 L 50 50 1 1 T
+X ~VP 2 -600 -800 200 R 50 50 1 1 O V
+X A9 20 600 300 200 L 50 50 1 1 T
+X A10 21 600 200 200 L 50 50 1 1 T
+X A11 22 600 100 200 L 50 50 1 1 T
+X VSS 23 0 -1550 200 U 50 50 1 1 W
+X VSS 24 100 -1550 200 U 50 50 1 1 W
+X A12 25 600 0 200 L 50 50 1 1 T
+X A13 26 600 -100 200 L 50 50 1 1 T
+X A14 27 600 -200 200 L 50 50 1 1 T
+X A15 28 600 -300 200 L 50 50 1 1 T
+X D7 29 600 -1200 200 L 50 50 1 1 B
+X RDY 3 -600 -300 200 R 50 50 1 1 C
+X D6 30 600 -1100 200 L 50 50 1 1 B
+X D5 31 600 -1000 200 L 50 50 1 1 B
+X D4 32 600 -900 200 L 50 50 1 1 B
+X D3 33 600 -800 200 L 50 50 1 1 B
+X D2 34 600 -700 200 L 50 50 1 1 B
+X D1 35 600 -600 200 L 50 50 1 1 B
+X D0 36 600 -500 200 L 50 50 1 1 B
+X VDD 37 0 1550 200 D 50 50 1 1 W
+X R/~W 38 -600 0 200 R 50 50 1 1 T
+X nc 39 -400 -1100 100 R 50 50 1 1 N NX
+X ϕ1 4 -600 800 200 R 50 50 1 1 O
+X BE 40 -600 -400 200 R 50 50 1 1 I
+X ϕ0 41 -600 900 200 R 50 50 1 1 I C
+X ~SO 42 -600 -1200 200 R 50 50 1 1 I L
+X ϕ2O 43 -600 700 200 R 50 50 1 1 O
+X ~RES 44 -600 1200 200 R 50 50 1 1 I L
+X ~IRQ 5 -600 400 200 R 50 50 1 1 I L
+X ~ML 6 -600 -900 200 R 50 50 1 1 O V
+X ~NMI 7 -600 300 200 R 50 50 1 1 I L
+X SYNC 8 -600 -700 200 R 50 50 1 1 O
+X VDD 9 -100 1550 200 D 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
+# W65C02SxQ
+#
+DEF W65C02SxQ U 0 40 Y Y 1 F N
+F0 "U" -400 1400 50 H V L CNN
+F1 "W65C02SxQ" 0 0 50 V V C CIB
+F2 "" 0 2000 50 H I C CNN
+F3 "" 0 1900 50 H I C CNN
+$FPLIST
+ PQFP-44_10x10mm_Pitch0.8mm
+$ENDFPLIST
+DRAW
+S -400 1350 400 -1350 0 1 0 f
+X ~NMI 1 -600 300 200 R 50 50 1 1 I L
+X A5 10 600 700 200 L 50 50 1 1 T
+X A6 11 600 600 200 L 50 50 1 1 T
+X A7 12 600 500 200 L 50 50 1 1 T
+X A8 13 600 400 200 L 50 50 1 1 T
+X A9 14 600 300 200 L 50 50 1 1 T
+X A10 15 600 200 200 L 50 50 1 1 T
+X A11 16 600 100 200 L 50 50 1 1 T
+X VSS 17 -100 -1550 200 U 50 50 1 1 W
+X VSS 18 0 -1550 200 U 50 50 1 1 W
+X A12 19 600 0 200 L 50 50 1 1 T
+X SYNC 2 -600 -700 200 R 50 50 1 1 O
+X A13 20 600 -100 200 L 50 50 1 1 T
+X A14 21 600 -200 200 L 50 50 1 1 T
+X A15 22 600 -300 200 L 50 50 1 1 T
+X D7 23 600 -1200 200 L 50 50 1 1 B
+X D6 24 600 -1100 200 L 50 50 1 1 B
+X D5 25 600 -1000 200 L 50 50 1 1 B
+X D4 26 600 -900 200 L 50 50 1 1 B
+X D3 27 600 -800 200 L 50 50 1 1 B
+X D2 28 600 -700 200 L 50 50 1 1 B
+X D1 29 600 -600 200 L 50 50 1 1 B
+X VDD 3 -100 1550 200 D 50 50 1 1 W
+X D0 30 600 -500 200 L 50 50 1 1 B
+X VDD 31 0 1550 200 D 50 50 1 1 W
+X R/~W 32 -600 0 200 R 50 50 1 1 T
+X nc 33 -400 -1100 100 R 50 50 1 1 N NX
+X BE 34 -600 -400 200 R 50 50 1 1 I
+X ϕ0 35 -600 900 200 R 50 50 1 1 I C
+X ~SO 36 -600 -1200 200 R 50 50 1 1 I L
+X ϕ2 37 -600 700 200 R 50 50 1 1 O
+X ~RES 38 -600 1200 200 R 50 50 1 1 I L
+X VSS 39 100 -1550 200 U 50 50 1 1 W
+X A0 4 600 1200 200 L 50 50 1 1 T
+X ~VP 40 -600 -800 200 R 50 50 1 1 O V
+X RDY 41 -600 -300 200 R 50 50 1 1 C
+X ϕ1 42 -600 800 200 R 50 50 1 1 O
+X ~IRQ 43 -600 400 200 R 50 50 1 1 I L
+X ~ML 44 -600 -900 200 R 50 50 1 1 O V
+X A1 5 600 1100 200 L 50 50 1 1 T
+X nc 6 -400 -1000 100 R 50 50 1 1 N NX
+X A2 7 600 1000 200 L 50 50 1 1 T
+X A3 8 600 900 200 L 50 50 1 1 T
+X A4 9 600 800 200 L 50 50 1 1 T
+ENDDRAW
+ENDDEF
+#
+# W65C21SxPL
+#
+DEF W65C21SxPL U 0 40 Y Y 1 F N
+F0 "U" -400 1300 50 H V L CNN
+F1 "W65C21SxPL" 0 0 50 V V C CIB
+F2 "" 0 150 50 H I C CNN
+F3 "" 0 150 50 H I C CNN
+ALIAS W65C21NxPL
+$FPLIST
+ PLCC44
+$ENDFPLIST
+DRAW
+S -400 1250 400 -1250 0 1 0 f
+X VSS 1 0 -1450 200 U 50 50 1 1 W
+X PA7 10 600 400 200 L 50 50 1 1 B
+X PB0 11 600 -100 200 L 50 50 1 1 B
+X PB1 12 600 -200 200 L 50 50 1 1 B
+X PB2 13 600 -300 200 L 50 50 1 1 B
+X PB3 14 600 -400 200 L 50 50 1 1 B
+X PB4 15 600 -500 200 L 50 50 1 1 B
+X PB5 16 600 -600 200 L 50 50 1 1 B
+X PB6 17 600 -700 200 L 50 50 1 1 B
+X PB7 18 600 -800 200 L 50 50 1 1 B
+X CB1 19 600 -1000 200 L 50 50 1 1 I
+X nc 2 -400 900 100 R 50 50 1 1 N NX
+X CB2 20 600 -1100 200 L 50 50 1 1 B
+X VCC 21 0 1450 200 D 50 50 1 1 W
+X nc 22 -400 600 100 R 50 50 1 1 N NX
+X R/~W 23 -600 -200 200 R 50 50 1 1 I
+X CS0 24 -600 500 200 R 50 50 1 1 I
+X ~CS2 25 -600 300 200 R 50 50 1 1 I L
+X CS1 26 -600 400 200 R 50 50 1 1 I
+X nc 27 -400 200 100 R 50 50 1 1 N NX
+X ϕ2 28 -600 1000 200 R 50 50 1 1 I C
+X D7 29 -600 -1100 200 R 50 50 1 1 B
+X PA0 3 600 1100 200 L 50 50 1 1 B
+X D6 30 -600 -1000 200 R 50 50 1 1 B
+X D5 31 -600 -900 200 R 50 50 1 1 B
+X D4 32 -600 -800 200 R 50 50 1 1 B
+X D3 33 -600 -700 200 R 50 50 1 1 B
+X D2 34 -600 -600 200 R 50 50 1 1 B
+X D1 35 -600 -500 200 R 50 50 1 1 B
+X D0 36 -600 -400 200 R 50 50 1 1 B
+X ~RES 37 -600 1100 200 R 50 50 1 1 I L
+X RS1 38 -600 0 200 R 50 50 1 1 I
+X RS0 39 -600 100 200 R 50 50 1 1 I
+X PA1 4 600 1000 200 L 50 50 1 1 B
+X nc 40 -400 -100 100 R 50 50 1 1 N NX
+X ~IRQB 41 -600 700 200 R 50 50 1 1 C V
+X ~IRQA 42 -600 800 200 R 50 50 1 1 C V
+X CA2 43 600 100 200 L 50 50 1 1 B
+X CA1 44 600 200 200 L 50 50 1 1 I
+X PA2 5 600 900 200 L 50 50 1 1 B
+X PA3 6 600 800 200 L 50 50 1 1 B
+X PA4 7 600 700 200 L 50 50 1 1 B
+X PA5 8 600 600 200 L 50 50 1 1 B
+X PA6 9 600 500 200 L 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# W65C22NxPL
+#
+DEF W65C22NxPL U 0 40 Y Y 1 F N
+F0 "U" -400 1300 50 H V L CNN
+F1 "W65C22NxPL" 0 0 50 V V C CIB
+F2 "" 0 150 50 H I C CNN
+F3 "" 0 150 50 H I C CNN
+$FPLIST
+ PLCC44
+$ENDFPLIST
+DRAW
+S -400 1250 400 -1250 0 1 0 f
+X VSS 1 0 -1450 200 U 50 50 1 1 W
+X PB0 10 600 -100 200 L 50 50 1 1 B
+X nc 11 -400 900 100 R 50 50 1 1 N NX
+X PB1 12 600 -200 200 L 50 50 1 1 B
+X PB2 13 600 -300 200 L 50 50 1 1 B
+X PB3 14 600 -400 200 L 50 50 1 1 B
+X PB4 15 600 -500 200 L 50 50 1 1 B
+X PB5 16 600 -600 200 L 50 50 1 1 B
+X PB6 17 600 -700 200 L 50 50 1 1 B
+X PB7 18 600 -800 200 L 50 50 1 1 B
+X CB1 19 600 -1000 200 L 50 50 1 1 I
+X PA0 2 600 1100 200 L 50 50 1 1 B
+X CB2 20 600 -1100 200 L 50 50 1 1 B
+X VDD 21 0 1450 200 D 50 50 1 1 W
+X nc 22 -400 700 100 R 50 50 1 1 N NX
+X ~IRQ 23 -600 800 200 R 50 50 1 1 C V
+X R/~W 24 -600 -200 200 R 50 50 1 1 I
+X ~CS2 25 -600 500 200 R 50 50 1 1 I L
+X CS1 26 -600 600 200 R 50 50 1 1 I
+X ϕ2 27 -600 1000 200 R 50 50 1 1 I C
+X D7 28 -600 -1100 200 R 50 50 1 1 B
+X D6 29 -600 -1000 200 R 50 50 1 1 B
+X PA1 3 600 1000 200 L 50 50 1 1 B
+X D5 30 -600 -900 200 R 50 50 1 1 B
+X D4 31 -600 -800 200 R 50 50 1 1 B
+X D3 32 -600 -700 200 R 50 50 1 1 B
+X nc 33 -400 400 100 R 50 50 1 1 N NX
+X D2 34 -600 -600 200 R 50 50 1 1 B
+X D1 35 -600 -500 200 R 50 50 1 1 B
+X D0 36 -600 -400 200 R 50 50 1 1 B
+X ~RES 37 -600 1100 200 R 50 50 1 1 I L
+X nc 38 -400 -100 100 R 50 50 1 1 N NX
+X RS3 39 -600 0 200 R 50 50 1 1 I
+X PA2 4 600 900 200 L 50 50 1 1 B
+X RS2 40 -600 100 200 R 50 50 1 1 I
+X RS1 41 -600 200 200 R 50 50 1 1 I
+X RS0 42 -600 300 200 R 50 50 1 1 I
+X CA2 43 600 100 200 L 50 50 1 1 B
+X CA1 44 600 200 200 L 50 50 1 1 I
+X PA3 5 600 800 200 L 50 50 1 1 B
+X PA4 6 600 700 200 L 50 50 1 1 B
+X PA5 7 600 600 200 L 50 50 1 1 B
+X PA6 8 600 500 200 L 50 50 1 1 B
+X PA7 9 600 400 200 L 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# W65C22SxP
+#
+DEF W65C22SxP U 0 40 Y Y 1 F N
+F0 "U" -400 1300 50 H V L CNN
+F1 "W65C22SxP" 0 0 50 V V C CIB
+F2 "" 0 150 50 H I C CNN
+F3 "" 0 150 50 H I C CNN
+$FPLIST
+ DIP-40_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1250 400 -1250 0 1 0 f
+X VSS 1 0 -1450 200 U 50 50 1 1 W
+X PB0 10 600 -100 200 L 50 50 1 1 B
+X PB1 11 600 -200 200 L 50 50 1 1 B
+X PB2 12 600 -300 200 L 50 50 1 1 B
+X PB3 13 600 -400 200 L 50 50 1 1 B
+X PB4 14 600 -500 200 L 50 50 1 1 B
+X PB5 15 600 -600 200 L 50 50 1 1 B
+X PB6 16 600 -700 200 L 50 50 1 1 B
+X PB7 17 600 -800 200 L 50 50 1 1 B
+X CB1 18 600 -1000 200 L 50 50 1 1 I
+X CB2 19 600 -1100 200 L 50 50 1 1 B
+X PA0 2 600 1100 200 L 50 50 1 1 B
+X VCC 20 0 1450 200 D 50 50 1 1 W
+X ~IRQ 21 -600 800 200 R 50 50 1 1 O V
+X R/~W 22 -600 -200 200 R 50 50 1 1 I
+X ~CS2 23 -600 500 200 R 50 50 1 1 I L
+X CS1 24 -600 600 200 R 50 50 1 1 I
+X ϕ2 25 -600 1000 200 R 50 50 1 1 I C
+X D7 26 -600 -1100 200 R 50 50 1 1 B
+X D6 27 -600 -1000 200 R 50 50 1 1 B
+X D5 28 -600 -900 200 R 50 50 1 1 B
+X D4 29 -600 -800 200 R 50 50 1 1 B
+X PA1 3 600 1000 200 L 50 50 1 1 B
+X D3 30 -600 -700 200 R 50 50 1 1 B
+X D2 31 -600 -600 200 R 50 50 1 1 B
+X D1 32 -600 -500 200 R 50 50 1 1 B
+X D0 33 -600 -400 200 R 50 50 1 1 B
+X ~RES 34 -600 1100 200 R 50 50 1 1 I L
+X RS3 35 -600 0 200 R 50 50 1 1 I
+X RS2 36 -600 100 200 R 50 50 1 1 I
+X RS1 37 -600 200 200 R 50 50 1 1 I
+X RS0 38 -600 300 200 R 50 50 1 1 I
+X CA2 39 600 100 200 L 50 50 1 1 B
+X PA2 4 600 900 200 L 50 50 1 1 B
+X CA1 40 600 200 200 L 50 50 1 1 I
+X PA3 5 600 800 200 L 50 50 1 1 B
+X PA4 6 600 700 200 L 50 50 1 1 B
+X PA5 7 600 600 200 L 50 50 1 1 B
+X PA6 8 600 500 200 L 50 50 1 1 B
+X PA7 9 600 400 200 L 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# W65C22SxPL
+#
+DEF W65C22SxPL U 0 40 Y Y 1 F N
+F0 "U" -400 1300 50 H V L CNN
+F1 "W65C22SxPL" 0 0 50 V V C CIB
+F2 "" 0 150 50 H I C CNN
+F3 "" 0 150 50 H I C CNN
+$FPLIST
+ PLCC44
+$ENDFPLIST
+DRAW
+S -400 1250 400 -1250 0 1 0 f
+X VSS 1 0 -1450 200 U 50 50 1 1 W
+X PB0 10 600 -100 200 L 50 50 1 1 B
+X nc 11 -400 900 100 R 50 50 1 1 N NX
+X PB1 12 600 -200 200 L 50 50 1 1 B
+X PB2 13 600 -300 200 L 50 50 1 1 B
+X PB3 14 600 -400 200 L 50 50 1 1 B
+X PB4 15 600 -500 200 L 50 50 1 1 B
+X PB5 16 600 -600 200 L 50 50 1 1 B
+X PB6 17 600 -700 200 L 50 50 1 1 B
+X PB7 18 600 -800 200 L 50 50 1 1 B
+X CB1 19 600 -1000 200 L 50 50 1 1 I
+X PA0 2 600 1100 200 L 50 50 1 1 B
+X CB2 20 600 -1100 200 L 50 50 1 1 B
+X VDD 21 0 1450 200 D 50 50 1 1 W
+X nc 22 -400 700 100 R 50 50 1 1 N NX
+X ~IRQ 23 -600 800 200 R 50 50 1 1 O V
+X R/~W 24 -600 -200 200 R 50 50 1 1 I
+X ~CS2 25 -600 500 200 R 50 50 1 1 I L
+X CS1 26 -600 600 200 R 50 50 1 1 I
+X ϕ2 27 -600 1000 200 R 50 50 1 1 I C
+X D7 28 -600 -1100 200 R 50 50 1 1 B
+X D6 29 -600 -1000 200 R 50 50 1 1 B
+X PA1 3 600 1000 200 L 50 50 1 1 B
+X D5 30 -600 -900 200 R 50 50 1 1 B
+X D4 31 -600 -800 200 R 50 50 1 1 B
+X D3 32 -600 -700 200 R 50 50 1 1 B
+X nc 33 -400 400 100 R 50 50 1 1 N NX
+X D2 34 -600 -600 200 R 50 50 1 1 B
+X D1 35 -600 -500 200 R 50 50 1 1 B
+X D0 36 -600 -400 200 R 50 50 1 1 B
+X ~RES 37 -600 1100 200 R 50 50 1 1 I L
+X nc 38 -400 -100 100 R 50 50 1 1 N NX
+X RS3 39 -600 0 200 R 50 50 1 1 I
+X PA2 4 600 900 200 L 50 50 1 1 B
+X RS2 40 -600 100 200 R 50 50 1 1 I
+X RS1 41 -600 200 200 R 50 50 1 1 I
+X RS0 42 -600 300 200 R 50 50 1 1 I
+X CA2 43 600 100 200 L 50 50 1 1 B
+X CA1 44 600 200 200 L 50 50 1 1 I
+X PA3 5 600 800 200 L 50 50 1 1 B
+X PA4 6 600 700 200 L 50 50 1 1 B
+X PA5 7 600 600 200 L 50 50 1 1 B
+X PA6 8 600 500 200 L 50 50 1 1 B
+X PA7 9 600 400 200 L 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# W65C22SxQ
+#
+DEF W65C22SxQ U 0 40 Y Y 1 F N
+F0 "U" -400 1300 50 H V L CNN
+F1 "W65C22SxQ" 0 0 50 V V C CIB
+F2 "" 0 150 50 H I C CNN
+F3 "" 0 150 50 H I C CNN
+$FPLIST
+ PQFP-44_10x10mm_Pitch0.8mm
+$ENDFPLIST
+DRAW
+S -400 1250 400 -1250 0 1 0 f
+X PA5 1 600 600 200 L 50 50 1 1 B
+X PB5 10 600 -600 200 L 50 50 1 1 B
+X PB6 11 600 -700 200 L 50 50 1 1 B
+X PB7 12 600 -800 200 L 50 50 1 1 B
+X CB1 13 600 -1000 200 L 50 50 1 1 I
+X CB2 14 600 -1100 200 L 50 50 1 1 B
+X VDD 15 0 1450 200 D 50 50 1 1 W
+X nc 16 -400 700 100 R 50 50 1 1 N NX
+X ~IRQ 17 -600 800 200 R 50 50 1 1 O V
+X R/~W 18 -600 -200 200 R 50 50 1 1 I
+X ~CS2 19 -600 500 200 R 50 50 1 1 I L
+X PA6 2 600 500 200 L 50 50 1 1 B
+X CS1 20 -600 600 200 R 50 50 1 1 I
+X ϕ2 21 -600 1000 200 R 50 50 1 1 I C
+X D7 22 -600 -1100 200 R 50 50 1 1 B
+X D6 23 -600 -1000 200 R 50 50 1 1 B
+X D5 24 -600 -900 200 R 50 50 1 1 B
+X D4 25 -600 -800 200 R 50 50 1 1 B
+X D3 26 -600 -700 200 R 50 50 1 1 B
+X nc 27 -400 400 100 R 50 50 1 1 N NX
+X D2 28 -600 -600 200 R 50 50 1 1 B
+X D1 29 -600 -500 200 R 50 50 1 1 B
+X PA7 3 600 400 200 L 50 50 1 1 B
+X D0 30 -600 -400 200 R 50 50 1 1 B
+X ~RES 31 -600 1100 200 R 50 50 1 1 I L
+X nc 32 -400 -100 100 R 50 50 1 1 N NX
+X RS3 33 -600 0 200 R 50 50 1 1 I
+X RS2 34 -600 100 200 R 50 50 1 1 I
+X RS1 35 -600 200 200 R 50 50 1 1 I
+X RS0 36 -600 300 200 R 50 50 1 1 I
+X CA2 37 600 100 200 L 50 50 1 1 B
+X CA1 38 600 200 200 L 50 50 1 1 I
+X VSS 39 0 -1450 200 U 50 50 1 1 W
+X PB0 4 600 -100 200 L 50 50 1 1 B
+X PA0 40 600 1100 200 L 50 50 1 1 B
+X PA1 41 600 1000 200 L 50 50 1 1 B
+X PA2 42 600 900 200 L 50 50 1 1 B
+X PA3 43 600 800 200 L 50 50 1 1 B
+X PA4 44 600 700 200 L 50 50 1 1 B
+X nc 5 -400 900 100 R 50 50 1 1 N NX
+X PB1 6 600 -200 200 L 50 50 1 1 B
+X PB2 7 600 -300 200 L 50 50 1 1 B
+X PB3 8 600 -400 200 L 50 50 1 1 B
+X PB4 9 600 -500 200 L 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# W65C51NxQ
+#
+DEF W65C51NxQ U 0 40 Y Y 1 F N
+F0 "U" -400 1300 50 H V L CNN
+F1 "W65C51NxQ" 0 0 50 V V C CIB
+F2 "" 0 150 50 H I C CNN
+F3 "" 0 150 50 H I C CNN
+$FPLIST
+ LQFP-32_7x7mm_Pitch0.8mm
+$ENDFPLIST
+DRAW
+S -400 1250 400 -1250 0 1 0 f
+X RxC 1 600 800 200 L 50 50 1 1 B C
+X RS0 10 -600 300 200 R 50 50 1 1 I
+X RS1 11 -600 200 200 R 50 50 1 1 I
+X VCC 12 -100 1450 200 D 50 50 1 1 W
+X VCC 13 0 1450 200 D 50 50 1 1 W
+X ~DCD 14 600 -600 200 L 50 50 1 1 I L
+X ~DSR 15 600 -400 200 L 50 50 1 1 I L
+X D0 16 -600 -400 200 R 50 50 1 1 B
+X D1 17 -600 -500 200 R 50 50 1 1 B
+X D2 18 -600 -600 200 R 50 50 1 1 B
+X D3 19 -600 -700 200 R 50 50 1 1 B
+X XTAL1 2 600 1100 200 L 50 50 1 1 I C
+X D4 20 -600 -800 200 R 50 50 1 1 B
+X D5 21 -600 -900 200 R 50 50 1 1 B
+X D6 22 -600 -1000 200 R 50 50 1 1 B
+X D7 23 -600 -1100 200 R 50 50 1 1 B
+X nc 24 400 -1100 101 L 50 50 1 1 N NX
+X ~IRQ 25 -600 800 200 R 50 50 1 1 C V
+X ϕ2 26 -600 1000 200 R 50 50 1 1 I C
+X R/~W 27 -600 -200 200 R 50 50 1 1 I
+X VSS 28 -100 -1450 200 U 50 50 1 1 W
+X VSS 29 0 -1450 200 U 50 50 1 1 W
+X XTAL2 3 600 1000 200 L 50 50 1 1 O
+X CS1 30 -600 600 200 R 50 50 1 1 I
+X ~CS2 31 -600 500 200 R 50 50 1 1 I L
+X ~RES 32 -600 1100 200 R 50 50 1 1 I L
+X ~RTS 4 600 0 200 L 50 50 1 1 O V
+X ~CTS 5 600 -100 200 L 50 50 1 1 I L
+X TxD 6 600 300 200 L 50 50 1 1 O
+X ~DTR 7 600 -300 200 L 50 50 1 1 O V
+X nc 8 400 -1000 101 L 50 50 1 1 N NX
+X RxD 9 600 200 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# W65C816SxP
+#
+DEF W65C816SxP U 0 40 Y Y 1 F N
+F0 "U" -400 1400 50 H V L CNN
+F1 "W65C816SxP" 0 0 50 V V C CIB
+F2 "" 0 2000 50 H I C CNN
+F3 "" 0 1900 50 H I C CNN
+$FPLIST
+ DIP-40_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1350 400 -1350 0 1 0 f
+X ~VP 1 -600 -800 200 R 50 50 1 1 O V
+X A1 10 600 1100 200 L 50 50 1 1 T
+X A2 11 600 1000 200 L 50 50 1 1 T
+X A3 12 600 900 200 L 50 50 1 1 T
+X A4 13 600 800 200 L 50 50 1 1 T
+X A5 14 600 700 200 L 50 50 1 1 T
+X A6 15 600 600 200 L 50 50 1 1 T
+X A7 16 600 500 200 L 50 50 1 1 T
+X A8 17 600 400 200 L 50 50 1 1 T
+X A9 18 600 300 200 L 50 50 1 1 T
+X A10 19 600 200 200 L 50 50 1 1 T
+X RDY 2 -600 -300 200 R 50 50 1 1 C
+X A11 20 600 100 200 L 50 50 1 1 T
+X VSS 21 0 -1550 200 U 50 50 1 1 W
+X A12 22 600 0 200 L 50 50 1 1 T
+X A13 23 600 -100 200 L 50 50 1 1 T
+X A14 24 600 -200 200 L 50 50 1 1 T
+X A15 25 600 -300 200 L 50 50 1 1 T
+X D7 26 600 -1200 200 L 50 50 1 1 B
+X D6 27 600 -1100 200 L 50 50 1 1 B
+X D5 28 600 -1000 200 L 50 50 1 1 B
+X D4 29 600 -900 200 L 50 50 1 1 B
+X ~ABORT 3 -600 500 200 R 50 50 1 1 I L
+X D3 30 600 -800 200 L 50 50 1 1 B
+X D2 31 600 -700 200 L 50 50 1 1 B
+X D1 32 600 -600 200 L 50 50 1 1 B
+X D0 33 600 -500 200 L 50 50 1 1 B
+X R/~W 34 -600 0 200 R 50 50 1 1 T
+X E 35 -600 -1100 200 R 50 50 1 1 O
+X BE 36 -600 -400 200 R 50 50 1 1 I
+X ϕ0 37 -600 900 200 R 50 50 1 1 I C
+X MX 38 -600 -1200 200 R 50 50 1 1 O
+X VDA 39 -600 -600 200 R 50 50 1 1 O
+X ~IRQ 4 -600 400 200 R 50 50 1 1 I L
+X ~RES 40 -600 1200 200 R 50 50 1 1 I L
+X ~ML 5 -600 -900 200 R 50 50 1 1 O V
+X ~NMI 6 -600 300 200 R 50 50 1 1 I L
+X VPA 7 -600 -500 200 R 50 50 1 1 O
+X VDD 8 0 1550 200 D 50 50 1 1 W
+X A0 9 600 1200 200 L 50 50 1 1 T
+ENDDRAW
+ENDDEF
+#
+# W65C816SxPL
+#
+DEF W65C816SxPL U 0 40 Y Y 1 F N
+F0 "U" -400 1400 50 H V L CNN
+F1 "W65C816SxPL" 0 0 50 V V C CIB
+F2 "" 0 2000 50 H I C CNN
+F3 "" 0 1900 50 H I C CNN
+$FPLIST
+ PLCC44
+$ENDFPLIST
+DRAW
+S -400 1350 400 -1350 0 1 0 f
+X VSS 1 -100 -1550 200 U 50 50 1 1 W
+X A0 10 600 1200 200 L 50 50 1 1 T
+X A1 11 600 1100 200 L 50 50 1 1 T
+X nc 12 -400 -1000 100 R 50 50 1 1 N NX
+X A2 13 600 1000 200 L 50 50 1 1 T
+X A3 14 600 900 200 L 50 50 1 1 T
+X A4 15 600 800 200 L 50 50 1 1 T
+X A5 16 600 700 200 L 50 50 1 1 T
+X A6 17 600 600 200 L 50 50 1 1 T
+X A7 18 600 500 200 L 50 50 1 1 T
+X A8 19 600 400 200 L 50 50 1 1 T
+X ~VP 2 -600 -800 200 R 50 50 1 1 O V
+X A9 20 600 300 200 L 50 50 1 1 T
+X A10 21 600 200 200 L 50 50 1 1 T
+X A11 22 600 100 200 L 50 50 1 1 T
+X VSS 23 0 -1550 200 U 50 50 1 1 W
+X VSS 24 100 -1550 200 U 50 50 1 1 W
+X A12 25 600 0 200 L 50 50 1 1 T
+X A13 26 600 -100 200 L 50 50 1 1 T
+X A14 27 600 -200 200 L 50 50 1 1 T
+X A15 28 600 -300 200 L 50 50 1 1 T
+X D7 29 600 -1200 200 L 50 50 1 1 B
+X RDY 3 -600 -300 200 R 50 50 1 1 C
+X D6 30 600 -1100 200 L 50 50 1 1 B
+X D5 31 600 -1000 200 L 50 50 1 1 B
+X D4 32 600 -900 200 L 50 50 1 1 B
+X D3 33 600 -800 200 L 50 50 1 1 B
+X D2 34 600 -700 200 L 50 50 1 1 B
+X D1 35 600 -600 200 L 50 50 1 1 B
+X D0 36 600 -500 200 L 50 50 1 1 B
+X VDD 37 0 1550 200 D 50 50 1 1 W
+X R/~W 38 -600 0 200 R 50 50 1 1 T
+X E 39 -600 -1100 200 R 50 50 1 1 O
+X ~ABORT 4 -600 500 200 R 50 50 1 1 I L
+X BE 40 -600 -400 200 R 50 50 1 1 I
+X ϕ0 41 -600 900 200 R 50 50 1 1 I C
+X MX 42 -600 -1200 200 R 50 50 1 1 O
+X VDA 43 -600 -600 200 R 50 50 1 1 O
+X ~RES 44 -600 1200 200 R 50 50 1 1 I L
+X ~IRQ 5 -600 400 200 R 50 50 1 1 I L
+X ~ML 6 -600 -900 200 R 50 50 1 1 O V
+X ~NMI 7 -600 300 200 R 50 50 1 1 I L
+X VPA 8 -600 -500 200 R 50 50 1 1 O
+X VDD 9 -100 1550 200 D 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
+# W65C816SxQ
+#
+DEF W65C816SxQ U 0 40 Y Y 1 F N
+F0 "U" -400 1400 50 H V L CNN
+F1 "W65C816SxQ" 0 0 50 V V C CIB
+F2 "" 0 2000 50 H I C CNN
+F3 "" 0 1900 50 H I C CNN
+$FPLIST
+ PQFP-44_10x10mm_Pitch0.8mm
+$ENDFPLIST
+DRAW
+S -400 1350 400 -1350 0 1 0 f
+X ~NMI 1 -600 300 200 R 50 50 1 1 I L
+X A5 10 600 700 200 L 50 50 1 1 T
+X A6 11 600 600 200 L 50 50 1 1 T
+X A7 12 600 500 200 L 50 50 1 1 T
+X A8 13 600 400 200 L 50 50 1 1 T
+X A9 14 600 300 200 L 50 50 1 1 T
+X A10 15 600 200 200 L 50 50 1 1 T
+X A11 16 600 100 200 L 50 50 1 1 T
+X VSS 17 -100 -1550 200 U 50 50 1 1 W
+X VSS 18 0 -1550 200 U 50 50 1 1 W
+X A12 19 600 0 200 L 50 50 1 1 T
+X VPA 2 -600 -500 200 R 50 50 1 1 O
+X A13 20 600 -100 200 L 50 50 1 1 T
+X A14 21 600 -200 200 L 50 50 1 1 T
+X A15 22 600 -300 200 L 50 50 1 1 T
+X D7 23 600 -1200 200 L 50 50 1 1 B
+X D6 24 600 -1100 200 L 50 50 1 1 B
+X D5 25 600 -1000 200 L 50 50 1 1 B
+X D4 26 600 -900 200 L 50 50 1 1 B
+X D3 27 600 -800 200 L 50 50 1 1 B
+X D2 28 600 -700 200 L 50 50 1 1 B
+X D1 29 600 -600 200 L 50 50 1 1 B
+X VDD 3 -100 1550 200 D 50 50 1 1 W
+X D0 30 600 -500 200 L 50 50 1 1 B
+X VDD 31 0 1550 200 D 50 50 1 1 W
+X R/~W 32 -600 0 200 R 50 50 1 1 T
+X E 33 -600 -1100 200 R 50 50 1 1 O
+X BE 34 -600 -400 200 R 50 50 1 1 I
+X ϕ0 35 -600 900 200 R 50 50 1 1 I C
+X MX 36 -600 -1200 200 R 50 50 1 1 O
+X VDA 37 -600 -600 200 R 50 50 1 1 O
+X ~RES 38 -600 1200 200 R 50 50 1 1 I L
+X VSS 39 100 -1550 200 U 50 50 1 1 W
+X A0 4 600 1200 200 L 50 50 1 1 T
+X ~VP 40 -600 -800 200 R 50 50 1 1 O V
+X RDY 41 -600 -300 200 R 50 50 1 1 C
+X ~ABORT 42 -600 500 200 R 50 50 1 1 I L
+X ~IRQ 43 -600 400 200 R 50 50 1 1 I L
+X ~ML 44 -600 -900 200 R 50 50 1 1 O V
+X A1 5 600 1100 200 L 50 50 1 1 T
+X nc 6 -400 -1000 100 R 50 50 1 1 N NX
+X A2 7 600 1000 200 L 50 50 1 1 T
+X A3 8 600 900 200 L 50 50 1 1 T
+X A4 9 600 800 200 L 50 50 1 1 T
+ENDDRAW
+ENDDEF
+#
+#End Library
\ No newline at end of file
diff --git a/MCL64/PCB/MCL64/BOM_MCL64.txt b/MCL64/PCB/MCL64/BOM_MCL64.txt
new file mode 100644
index 0000000..545b7fb
--- /dev/null
+++ b/MCL64/PCB/MCL64/BOM_MCL64.txt
@@ -0,0 +1,11 @@
+
+
+
+Bill of Material
+------------------
+
+ U2,U3,U4,U5 	 	Latches Tri-St Octal D-Type		$0.66	Mouser# 595-SN74LVC573ADBR	 	https://www.mouser.com/ProductDetail/Texas-Instruments/SN74LVC573ADBR?qs=w32V8uFkMxm30hcaiO0jWQ%3D%3D
+ U6 	 			Inverters Hex					$0.46	Mouser# 595-SN74LVC04ADBR		https://www.mouser.com/ProductDetail/Texas-Instruments/SN74LVC04ADBR?qs=L4Mc90zKIpizmvP8RiWNwQ%3D%3D	
+ U7 	 			Octal Buffer 					$0.41	Mouser# 595-SN74LVC244ADBR		https://www.mouser.com/ProductDetail/Texas-Instruments/SN74LVC244ADBR?qs=L5CvrNUdZirMdYFgxYlMrA%3D%3D
+ 
+ C1, U1, U8			** Dont-Stuff **
\ No newline at end of file
diff --git a/MCL64/PCB/MCL64/MCL64 b/MCL64/PCB/MCL64/MCL64
new file mode 100644
index 0000000..ef47440
--- /dev/null
+++ b/MCL64/PCB/MCL64/MCL64
@@ -0,0 +1,14 @@
+"Source:"	"F:\Latest_1_9_2021\MCL64\MCL64_PCB\MCL64\MCL64.sch"
+"Date:"	"3/16/2021 10:05:42 PM"
+"Tool:"	"Eeschema (5.1.8)-1"
+"Component Count:"	"9"
+"Ref"	"Value"	"Part"	"Footprint"	"Description"	"Vendor"
+"C1"	"10uF"	"Device:CP1"	"Capacitor_THT:C_Disc_D7.0mm_W2.5mm_P5.00mm"	"Polarized capacitor, US symbol"	""
+"U1"	"Teensy 4.1"	"teensy:Teensy4.1"	"Teensy:Teensy41_Ted_Modified"	""	""
+"U2"	"74LS573"	"74xx:74LS573"	"Package_SO:SSOP-20_5.3x7.2mm_P0.65mm"	"8-bit Latch 3-state outputs"	""
+"U3"	"74LS573"	"74xx:74LS573"	"Package_SO:SSOP-20_5.3x7.2mm_P0.65mm"	"8-bit Latch 3-state outputs"	""
+"U4"	"74LS573"	"74xx:74LS573"	"Package_SO:SSOP-20_5.3x7.2mm_P0.65mm"	"8-bit Latch 3-state outputs"	""
+"U5"	"74LS573"	"74xx:74LS573"	"Package_SO:SSOP-20_5.3x7.2mm_P0.65mm"	"8-bit Latch 3-state outputs"	""
+"U6"	"74LS04"	"74xx:74LS04"	"Package_SO:SSOP-14_5.3x6.2mm_P0.65mm"	"Hex Inverter"	""
+"U7"	"74LS244"	"74xx:74LS244"	"Package_SO:SSOP-20_5.3x7.2mm_P0.65mm"	"Octal Buffer and Line Driver With 3-State Output, active-low enables, non-inverting outputs"	""
+"U8"	"6510"	"65xx:6510"	"Package_DIP:DIP-40_W15.24mm"	"6510 8-bit NMOS Microprocessor, 64K, 6-bit I/O Port, DIP-40"	""
diff --git a/MCL64/PCB/MCL64/MCL64-cache.lib b/MCL64/PCB/MCL64/MCL64-cache.lib
new file mode 100644
index 0000000..763aa7d
--- /dev/null
+++ b/MCL64/PCB/MCL64/MCL64-cache.lib
@@ -0,0 +1,298 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# 65xx_6510
+#
+DEF 65xx_6510 U 0 40 Y Y 1 F N
+F0 "U" -400 1850 50 H V L CNN
+F1 "65xx_6510" 0 0 50 V V C CIB
+F2 "" 0 2450 50 H I C CNN
+F3 "" 0 2350 50 H I C CNN
+ALIAS 8500
+$FPLIST
+ DIP-40_W15.24mm*
+$ENDFPLIST
+DRAW
+S -400 1800 400 -1800 0 1 0 f
+X ϕ0 1 -600 1350 200 R 50 50 1 1 I C
+X A3 10 600 1350 200 L 50 50 1 1 T
+X A4 11 600 1250 200 L 50 50 1 1 T
+X A5 12 600 1150 200 L 50 50 1 1 T
+X A6 13 600 1050 200 L 50 50 1 1 T
+X A7 14 600 950 200 L 50 50 1 1 T
+X A8 15 600 850 200 L 50 50 1 1 T
+X A9 16 600 750 200 L 50 50 1 1 T
+X A10 17 600 650 200 L 50 50 1 1 T
+X A11 18 600 550 200 L 50 50 1 1 T
+X A12 19 600 450 200 L 50 50 1 1 T
+X RDY 2 -600 150 200 R 50 50 1 1 I
+X A13 20 600 350 200 L 50 50 1 1 T
+X VSS 21 0 -2000 200 U 50 50 1 1 W
+X A14 22 600 250 200 L 50 50 1 1 T
+X A15 23 600 150 200 L 50 50 1 1 T
+X P5 24 600 -1450 200 L 50 50 1 1 B
+X P4 25 600 -1350 200 L 50 50 1 1 B
+X P3 26 600 -1250 200 L 50 50 1 1 B
+X P2 27 600 -1150 200 L 50 50 1 1 B
+X P1 28 600 -1050 200 L 50 50 1 1 B
+X P0 29 600 -950 200 L 50 50 1 1 B
+X ~IRQ 3 -600 850 200 R 50 50 1 1 I L
+X D7 30 600 -750 200 L 50 50 1 1 B
+X D6 31 600 -650 200 L 50 50 1 1 B
+X D5 32 600 -550 200 L 50 50 1 1 B
+X D4 33 600 -450 200 L 50 50 1 1 B
+X D3 34 600 -350 200 L 50 50 1 1 B
+X D2 35 600 -250 200 L 50 50 1 1 B
+X D1 36 600 -150 200 L 50 50 1 1 B
+X D0 37 600 -50 200 L 50 50 1 1 B
+X R/~W 38 -600 450 200 R 50 50 1 1 T
+X ϕ2 39 -600 1150 200 R 50 50 1 1 O
+X ~NMI 4 -600 750 200 R 50 50 1 1 I L
+X ~RES 40 -600 1650 200 R 50 50 1 1 I L
+X AEC 5 -600 50 200 R 50 50 1 1 I
+X VCC 6 0 2000 200 D 50 50 1 1 W
+X A0 7 600 1650 200 L 50 50 1 1 T
+X A1 8 600 1550 200 L 50 50 1 1 T
+X A2 9 600 1450 200 L 50 50 1 1 T
+ENDDRAW
+ENDDEF
+#
+# 74xx_74LS04
+#
+DEF 74xx_74LS04 U 0 20 Y Y 7 L N
+F0 "U" 0 50 50 H V C CNN
+F1 "74xx_74LS04" 0 -50 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS 74HC04 74HCT04 74AHC04 74AHCT04
+$FPLIST
+ DIP*W7.62mm*
+ SSOP?14*
+ TSSOP?14*
+$ENDFPLIST
+DRAW
+S -200 300 200 -300 7 1 10 f
+P 4 1 0 10 -150 150 -150 -150 150 0 -150 150 f
+P 4 2 0 10 -150 150 -150 -150 150 0 -150 150 f
+P 4 3 0 10 -150 150 -150 -150 150 0 -150 150 f
+P 4 4 0 10 -150 150 -150 -150 150 0 -150 150 f
+P 4 5 0 10 -150 150 -150 -150 150 0 -150 150 f
+P 4 6 0 10 -150 150 -150 -150 150 0 -150 150 f
+X ~ 1 -300 0 150 R 50 50 1 0 I
+X ~ 2 300 0 150 L 50 50 1 0 O I
+X ~ 3 -300 0 150 R 50 50 2 0 I
+X ~ 4 300 0 150 L 50 50 2 0 O I
+X ~ 5 -300 0 150 R 50 50 3 0 I
+X ~ 6 300 0 150 L 50 50 3 0 O I
+X ~ 8 300 0 150 L 50 50 4 0 O I
+X ~ 9 -300 0 150 R 50 50 4 0 I
+X ~ 10 300 0 150 L 50 50 5 0 O I
+X ~ 11 -300 0 150 R 50 50 5 0 I
+X ~ 12 300 0 150 L 50 50 6 0 O I
+X ~ 13 -300 0 150 R 50 50 6 0 I
+X VCC 14 0 500 200 D 50 50 7 0 W
+X GND 7 0 -500 200 U 50 50 7 0 W
+ENDDRAW
+ENDDEF
+#
+# 74xx_74LS244
+#
+DEF 74xx_74LS244 U 0 40 Y Y 1 F N
+F0 "U" -300 650 50 H V C CNN
+F1 "74xx_74LS244" -300 -650 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ DIP?20*
+$ENDFPLIST
+DRAW
+S -300 600 300 -600 1 1 10 f
+P 3 1 0 0 -25 -50 -25 50 25 50 N
+P 4 1 0 0 -50 -50 25 -50 25 50 50 50 N
+X OEa 1 -500 -400 200 R 50 50 1 0 I I
+X GND 10 0 -800 200 U 50 50 1 0 W
+X I0b 11 -500 100 200 R 50 50 1 0 I
+X O3a 12 500 200 200 L 50 50 1 0 T
+X I1b 13 -500 0 200 R 50 50 1 0 I
+X O2a 14 500 300 200 L 50 50 1 0 T
+X I2b 15 -500 -100 200 R 50 50 1 0 I
+X O1a 16 500 400 200 L 50 50 1 0 T
+X I3b 17 -500 -200 200 R 50 50 1 0 I
+X O0a 18 500 500 200 L 50 50 1 0 T
+X OEb 19 -500 -500 200 R 50 50 1 0 I I
+X I0a 2 -500 500 200 R 50 50 1 0 I
+X VCC 20 0 800 200 D 50 50 1 0 W
+X O3b 3 500 -200 200 L 50 50 1 0 T
+X I1a 4 -500 400 200 R 50 50 1 0 I
+X O2b 5 500 -100 200 L 50 50 1 0 T
+X I2a 6 -500 300 200 R 50 50 1 0 I
+X O1b 7 500 0 200 L 50 50 1 0 T
+X I3a 8 -500 200 200 R 50 50 1 0 I
+X O0b 9 500 100 200 L 50 50 1 0 T
+ENDDRAW
+ENDDEF
+#
+# 74xx_74LS573
+#
+DEF 74xx_74LS573 U 0 40 Y Y 1 L N
+F0 "U" -300 650 50 H V C CNN
+F1 "74xx_74LS573" -300 -650 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ DIP?20*
+$ENDFPLIST
+DRAW
+S -300 600 300 -600 1 1 10 f
+X OE 1 -500 -500 200 R 50 50 1 0 I I
+X GND 10 0 -800 200 U 50 50 1 0 W
+X Load 11 -500 -400 200 R 50 50 1 0 I
+X Q7 12 500 -200 200 L 50 50 1 0 T
+X Q6 13 500 -100 200 L 50 50 1 0 T
+X Q5 14 500 0 200 L 50 50 1 0 T
+X Q4 15 500 100 200 L 50 50 1 0 T
+X Q3 16 500 200 200 L 50 50 1 0 T
+X Q2 17 500 300 200 L 50 50 1 0 T
+X Q1 18 500 400 200 L 50 50 1 0 T
+X Q0 19 500 500 200 L 50 50 1 0 T
+X D0 2 -500 500 200 R 50 50 1 0 I
+X VCC 20 0 800 200 D 50 50 1 0 W
+X D1 3 -500 400 200 R 50 50 1 0 I
+X D2 4 -500 300 200 R 50 50 1 0 I
+X D3 5 -500 200 200 R 50 50 1 0 I
+X D4 6 -500 100 200 R 50 50 1 0 I
+X D5 7 -500 0 200 R 50 50 1 0 I
+X D6 8 -500 -100 200 R 50 50 1 0 I
+X D7 9 -500 -200 200 R 50 50 1 0 I
+ENDDRAW
+ENDDEF
+#
+# Device_CP1
+#
+DEF Device_CP1 C 0 10 N N 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "Device_CP1" 25 -100 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ CP_*
+$ENDFPLIST
+DRAW
+A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50
+P 2 0 1 20 -80 30 80 30 N
+P 2 0 1 0 -70 90 -30 90 N
+P 2 0 1 0 -50 70 -50 110 N
+X ~ 1 0 150 110 D 50 50 1 1 P
+X ~ 2 0 -150 130 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# power_+3V3
+#
+DEF power_+3V3 #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "power_+3V3" 0 140 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS +3.3V
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +3V3 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# power_+5V
+#
+DEF power_+5V #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "power_+5V" 0 140 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +5V 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# power_GND
+#
+DEF power_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "power_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# teensy_Teensy4.1
+#
+DEF teensy_Teensy4.1 U 0 40 Y Y 1 F N
+F0 "U" 0 2550 50 H V C CNN
+F1 "teensy_Teensy4.1" 0 2450 50 H V C CNN
+F2 "" -400 400 50 H I C CNN
+F3 "" -400 400 50 H I C CNN
+DRAW
+T 0 450 1950 40 0 0 0 "(250mA max)" Normal 0 C C
+T 0 450 2150 40 0 0 0 "(3.6v to 5.5v)" Normal 0 C C
+S -900 2400 900 -1100 0 1 0 N
+S -800 -50 -800 -50 0 1 0 N
+P 2 0 0 0 -900 -250 900 -250 N
+X 8_TX2_IN1 10 -1100 1250 200 R 50 50 0 0 B
+X 9_OUT1C 11 -1100 1150 200 R 50 50 0 0 B
+X 10_CS_MQSR 12 -1100 1050 200 R 50 50 0 0 B
+X 11_MOSI_CTX1 13 -1100 950 200 R 50 50 0 0 B
+X 12_MISO_MQSL 14 -1100 850 200 R 50 50 0 0 B
+X 3V3 15 -1100 750 200 R 50 50 0 0 W
+X 24_A10_TX6_SCL2 16 -1100 650 200 R 50 50 0 0 B
+X 25_A11_RX6_SDA2 17 -1100 550 200 R 50 50 0 0 B
+X 26_A12_MOSI1 18 -1100 450 200 R 50 50 0 0 B
+X 27_A13_SCK1 19 -1100 350 200 R 50 50 0 0 B
+X 28_RX7 20 -1100 250 200 R 50 50 0 0 B
+X 29_TX7 21 -1100 150 200 R 50 50 0 0 B
+X 30_CRX3 22 -1100 50 200 R 50 50 0 0 B
+X 31_CTX3 23 -1100 -50 200 R 50 50 0 0 B
+X 32_OUT1B 24 -1100 -150 200 R 50 50 0 0 B
+X 33_MCLK2 25 1100 -150 200 L 50 50 0 0 B
+X 34_RX8 26 1100 -50 200 L 50 50 0 0 B
+X 35_TX8 27 1100 50 200 L 50 50 0 0 B
+X 36_CS 28 1100 150 200 L 50 50 0 0 B
+X 37_CS 29 1100 250 200 L 50 50 0 0 B
+X 38_CS1_IN1 30 1100 350 200 L 50 50 0 0 B
+X 39_MISO1_OUT1A 31 1100 450 200 L 50 50 0 0 B
+X 40_A16 32 1100 550 200 L 50 50 0 0 B
+X 41_A17 33 1100 650 200 L 50 50 0 0 B
+X 13_SCK_LED 35 1100 850 200 L 50 50 0 0 B
+X 14_A0_TX3_SPDIF_OUT 36 1100 950 200 L 50 50 0 0 B
+X 15_A1_RX3_SPDIF_IN 37 1100 1050 200 L 50 50 0 0 B
+X 16_A2_RX4_SCL1 38 1100 1150 200 L 50 50 0 0 B
+X 17_A3_TX4_SDA1 39 1100 1250 200 L 50 50 0 0 B
+X 18_A4_SDA 40 1100 1350 200 L 50 50 0 0 B
+X 19_A5_SCL 41 1100 1450 200 L 50 50 0 0 B
+X 20_A6_TX5_LRCLK1 42 1100 1550 200 L 50 50 0 0 B
+X 21_A7_RX5_BCLK1 43 1100 1650 200 L 50 50 0 0 B
+X 22_A8_CTX1 44 1100 1750 200 L 50 50 0 0 B
+X 23_A9_CRX1_MCLK1 45 1100 1850 200 L 50 50 0 0 B
+X 3V3 46 1100 1950 200 L 50 50 0 0 O
+X GND 47 1100 2050 200 L 50 50 0 0 O
+X VIN 48 1100 2150 200 L 50 50 0 0 W
+X 3_LRCLK2 5 -1100 1750 200 R 50 50 0 0 B
+X 4_BCLK2 6 -1100 1650 200 R 50 50 0 0 B
+X 5_IN2 7 -1100 1550 200 R 50 50 0 0 B
+X 6_OUT1D 8 -1100 1450 200 R 50 50 0 0 B
+X 7_RX2_OUT1A 9 -1100 1350 200 R 50 50 0 0 B
+X GND 1 -1100 2150 200 R 50 50 1 1 W
+X 0_RX1_CRX2_CS1 2 -1100 2050 200 R 50 50 1 1 B
+X 1_TX1_CTX2_MISO1 3 -1100 1950 200 R 50 50 1 1 B
+X GND 34 1100 750 200 L 50 50 1 1 W
+X 2_OUT2 4 -1100 1850 200 R 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/MCL64/PCB/MCL64/MCL64.kicad_pcb b/MCL64/PCB/MCL64/MCL64.kicad_pcb
new file mode 100644
index 0000000..39f3850
--- /dev/null
+++ b/MCL64/PCB/MCL64/MCL64.kicad_pcb
@@ -0,0 +1,3357 @@
+(kicad_pcb (version 20171130) (host pcbnew "(5.1.8)-1")
+
+  (general
+    (thickness 1.6)
+    (drawings 6)
+    (tracks 667)
+    (zones 0)
+    (modules 9)
+    (nets 90)
+  )
+
+  (page A4)
+  (layers
+    (0 Top.Cu signal)
+    (1 Inner1.Cu signal hide)
+    (2 Inner2.Cu signal hide)
+    (31 Bottom.Cu signal hide)
+    (32 B.Adhes user hide)
+    (33 F.Adhes user hide)
+    (34 B.Paste user hide)
+    (35 F.Paste user hide)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user hide)
+    (39 F.Mask user hide)
+    (40 Dwgs.User user hide)
+    (41 Cmts.User user hide)
+    (42 Eco1.User user hide)
+    (43 Eco2.User user hide)
+    (44 Edge.Cuts user)
+    (45 Margin user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.1778)
+    (trace_clearance 0.127)
+    (zone_clearance 0.254)
+    (zone_45_only no)
+    (trace_min 0.1778)
+    (via_size 0.6)
+    (via_drill 0.4)
+    (via_min_size 0.3556)
+    (via_min_drill 0.2794)
+    (uvia_size 0.3)
+    (uvia_drill 0.1)
+    (uvias_allowed no)
+    (uvia_min_size 0.2)
+    (uvia_min_drill 0.1)
+    (edge_width 0.05)
+    (segment_width 0.2)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.12)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 1.524 1.524)
+    (pad_drill 0.762)
+    (pad_to_mask_clearance 0)
+    (aux_axis_origin 87.48776 143.96212)
+    (grid_origin 87.48776 143.96212)
+    (visible_elements 7FFDFF7F)
+    (pcbplotparams
+      (layerselection 0x010fc_ffffffff)
+      (usegerberextensions false)
+      (usegerberattributes false)
+      (usegerberadvancedattributes false)
+      (creategerberjobfile true)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 0)
+      (scaleselection 1)
+      (outputdirectory "PCB_Products/"))
+  )
+
+  (net 0 "")
+  (net 1 "Net-(U8-Pad26)")
+  (net 2 "Net-(U8-Pad25)")
+  (net 3 +5V)
+  (net 4 GND)
+  (net 5 +3V3)
+  (net 6 CPU_CLKIN)
+  (net 7 CPU_RST_n)
+  (net 8 CPU_NMI_n)
+  (net 9 CPU_IRQ_n)
+  (net 10 CPU_READY)
+  (net 11 CPU_AEC)
+  (net 12 CPU_WR_n)
+  (net 13 CPU_CLKOUT)
+  (net 14 CPU_P0)
+  (net 15 CPU_P1)
+  (net 16 CPU_P2)
+  (net 17 CPU_A13)
+  (net 18 CPU_A12)
+  (net 19 CPU_A11)
+  (net 20 CPU_D0)
+  (net 21 CPU_A10)
+  (net 22 CPU_D1)
+  (net 23 CPU_A9)
+  (net 24 CPU_D2)
+  (net 25 CPU_A8)
+  (net 26 CPU_D3)
+  (net 27 CPU_A7)
+  (net 28 CPU_D4)
+  (net 29 CPU_A6)
+  (net 30 CPU_D5)
+  (net 31 CPU_A5)
+  (net 32 CPU_D6)
+  (net 33 CPU_A4)
+  (net 34 CPU_D7)
+  (net 35 CPU_A3)
+  (net 36 CPU_A2)
+  (net 37 CPU_A1)
+  (net 38 CPU_A0)
+  (net 39 CPU_A15)
+  (net 40 CPU_A14)
+  (net 41 TEENSY_A7)
+  (net 42 TEENSY_A6)
+  (net 43 TEENSY_A5)
+  (net 44 TEENSY_A4)
+  (net 45 TEENSY_A3)
+  (net 46 TEENSY_A2)
+  (net 47 TEENSY_A1)
+  (net 48 TEENSY_A0)
+  (net 49 CPU_AEC_n)
+  (net 50 TEENSY_A15)
+  (net 51 TEENSY_A14)
+  (net 52 TEENSY_A13)
+  (net 53 TEENSY_A12)
+  (net 54 TEENSY_A11)
+  (net 55 TEENSY_A10)
+  (net 56 TEENSY_A9)
+  (net 57 TEENSY_A8)
+  (net 58 TEENSY_CLKIN)
+  (net 59 TEENSY_P2)
+  (net 60 "Net-(U7-Pad16)")
+  (net 61 TEENSY_P1)
+  (net 62 "Net-(U7-Pad14)")
+  (net 63 TEENSY_P0)
+  (net 64 "Net-(U7-Pad12)")
+  (net 65 "Net-(U7-Pad8)")
+  (net 66 "Net-(U7-Pad6)")
+  (net 67 "Net-(U7-Pad4)")
+  (net 68 TEENSY_WR_n)
+  (net 69 TEENSY_IN_D0)
+  (net 70 TEENSY_IN_D1)
+  (net 71 TEENSY_IN_D2)
+  (net 72 TEENSY_IN_D3)
+  (net 73 TEENSY_IN_D4)
+  (net 74 TEENSY_IN_D5)
+  (net 75 TEENSY_IN_D6)
+  (net 76 TEENSY_IN_D7)
+  (net 77 TEENSY_OUT_D7)
+  (net 78 TEENSY_OUT_D6)
+  (net 79 TEENSY_OUT_D5)
+  (net 80 TEENSY_OUT_D4)
+  (net 81 TEENSY_OUT_D3)
+  (net 82 TEENSY_OUT_D2)
+  (net 83 TEENSY_OUT_D1)
+  (net 84 TEENSY_OUT_D0)
+  (net 85 TEENSY_DATA_OE_n)
+  (net 86 TEENSY_NMI)
+  (net 87 TEENSY_RST)
+  (net 88 TEENSY_READY_n)
+  (net 89 TEENSY_IRQ)
+
+  (net_class Default "This is the default net class."
+    (clearance 0.127)
+    (trace_width 0.1778)
+    (via_dia 0.6)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    (add_net +3V3)
+    (add_net +5V)
+    (add_net CPU_A0)
+    (add_net CPU_A1)
+    (add_net CPU_A10)
+    (add_net CPU_A11)
+    (add_net CPU_A12)
+    (add_net CPU_A13)
+    (add_net CPU_A14)
+    (add_net CPU_A15)
+    (add_net CPU_A2)
+    (add_net CPU_A3)
+    (add_net CPU_A4)
+    (add_net CPU_A5)
+    (add_net CPU_A6)
+    (add_net CPU_A7)
+    (add_net CPU_A8)
+    (add_net CPU_A9)
+    (add_net CPU_AEC)
+    (add_net CPU_AEC_n)
+    (add_net CPU_CLKIN)
+    (add_net CPU_CLKOUT)
+    (add_net CPU_D0)
+    (add_net CPU_D1)
+    (add_net CPU_D2)
+    (add_net CPU_D3)
+    (add_net CPU_D4)
+    (add_net CPU_D5)
+    (add_net CPU_D6)
+    (add_net CPU_D7)
+    (add_net CPU_IRQ_n)
+    (add_net CPU_NMI_n)
+    (add_net CPU_P0)
+    (add_net CPU_P1)
+    (add_net CPU_P2)
+    (add_net CPU_READY)
+    (add_net CPU_RST_n)
+    (add_net CPU_WR_n)
+    (add_net GND)
+    (add_net "Net-(U7-Pad12)")
+    (add_net "Net-(U7-Pad14)")
+    (add_net "Net-(U7-Pad16)")
+    (add_net "Net-(U7-Pad4)")
+    (add_net "Net-(U7-Pad6)")
+    (add_net "Net-(U7-Pad8)")
+    (add_net "Net-(U8-Pad25)")
+    (add_net "Net-(U8-Pad26)")
+    (add_net TEENSY_A0)
+    (add_net TEENSY_A1)
+    (add_net TEENSY_A10)
+    (add_net TEENSY_A11)
+    (add_net TEENSY_A12)
+    (add_net TEENSY_A13)
+    (add_net TEENSY_A14)
+    (add_net TEENSY_A15)
+    (add_net TEENSY_A2)
+    (add_net TEENSY_A3)
+    (add_net TEENSY_A4)
+    (add_net TEENSY_A5)
+    (add_net TEENSY_A6)
+    (add_net TEENSY_A7)
+    (add_net TEENSY_A8)
+    (add_net TEENSY_A9)
+    (add_net TEENSY_CLKIN)
+    (add_net TEENSY_DATA_OE_n)
+    (add_net TEENSY_IN_D0)
+    (add_net TEENSY_IN_D1)
+    (add_net TEENSY_IN_D2)
+    (add_net TEENSY_IN_D3)
+    (add_net TEENSY_IN_D4)
+    (add_net TEENSY_IN_D5)
+    (add_net TEENSY_IN_D6)
+    (add_net TEENSY_IN_D7)
+    (add_net TEENSY_IRQ)
+    (add_net TEENSY_NMI)
+    (add_net TEENSY_OUT_D0)
+    (add_net TEENSY_OUT_D1)
+    (add_net TEENSY_OUT_D2)
+    (add_net TEENSY_OUT_D3)
+    (add_net TEENSY_OUT_D4)
+    (add_net TEENSY_OUT_D5)
+    (add_net TEENSY_OUT_D6)
+    (add_net TEENSY_OUT_D7)
+    (add_net TEENSY_P0)
+    (add_net TEENSY_P1)
+    (add_net TEENSY_P2)
+    (add_net TEENSY_READY_n)
+    (add_net TEENSY_RST)
+    (add_net TEENSY_WR_n)
+  )
+
+  (module Capacitor_THT:C_Disc_D7.0mm_W2.5mm_P5.00mm (layer Top.Cu) (tedit 5AE50EF0) (tstamp 604ECE63)
+    (at 113.53292 136.4107)
+    (descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=7*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf")
+    (tags "C Disc series Radial pin pitch 5.00mm  diameter 7mm width 2.5mm Capacitor")
+    (path /60529805)
+    (fp_text reference C1 (at 2.5 -2.5) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 10uF (at 2.5 2.5) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 6.25 -1.5) (end -1.25 -1.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 6.25 1.5) (end 6.25 -1.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.25 1.5) (end 6.25 1.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.25 -1.5) (end -1.25 1.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 6.12 -1.37) (end 6.12 1.37) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.12 -1.37) (end -1.12 1.37) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.12 1.37) (end 6.12 1.37) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.12 -1.37) (end 6.12 -1.37) (layer F.SilkS) (width 0.12))
+    (fp_line (start 6 -1.25) (end -1 -1.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 6 1.25) (end 6 -1.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -1 1.25) (end 6 1.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -1 -1.25) (end -1 1.25) (layer F.Fab) (width 0.1))
+    (fp_text user %R (at 2.5 0) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 2 thru_hole circle (at 5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 4 GND))
+    (pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 5 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D7.0mm_W2.5mm_P5.00mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Teensy:Teensy41_Ted_Modified (layer Top.Cu) (tedit 604DAF9D) (tstamp 604C690F)
+    (at 97.46742 113.40846 90)
+    (path /604E31A7)
+    (fp_text reference U1 (at 31.46298 0.14478) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value "Teensy 4.1" (at 0 10.16 90) (layer F.Fab) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start -30.48 8.89) (end -30.48 -8.89) (layer F.SilkS) (width 0.15))
+    (fp_line (start 30.48 8.89) (end -30.48 8.89) (layer F.SilkS) (width 0.15))
+    (fp_line (start 30.48 -8.89) (end 30.48 8.89) (layer F.SilkS) (width 0.15))
+    (fp_line (start -30.48 -8.89) (end 30.48 -8.89) (layer F.SilkS) (width 0.15))
+    (fp_line (start -25.4 3.81) (end -30.48 3.81) (layer F.SilkS) (width 0.15))
+    (fp_line (start -25.4 -3.81) (end -30.48 -3.81) (layer F.SilkS) (width 0.15))
+    (fp_line (start -25.4 3.81) (end -25.4 -3.81) (layer F.SilkS) (width 0.15))
+    (fp_line (start -31.75 -3.81) (end -30.48 -3.81) (layer F.SilkS) (width 0.15))
+    (fp_line (start -31.75 3.81) (end -31.75 -3.81) (layer F.SilkS) (width 0.15))
+    (fp_line (start -30.48 3.81) (end -31.75 3.81) (layer F.SilkS) (width 0.15))
+    (fp_line (start 30.48 -6.35) (end 17.78 -6.35) (layer F.SilkS) (width 0.15))
+    (fp_line (start 17.78 -6.35) (end 17.78 6.35) (layer F.SilkS) (width 0.15))
+    (fp_line (start 17.78 6.35) (end 30.48 6.35) (layer F.SilkS) (width 0.15))
+    (fp_line (start 30.48 -5.08) (end 29.21 -5.08) (layer F.SilkS) (width 0.15))
+    (fp_line (start 29.21 -5.08) (end 29.21 5.08) (layer F.SilkS) (width 0.15))
+    (fp_line (start 29.21 5.08) (end 30.48 5.08) (layer F.SilkS) (width 0.15))
+    (fp_text user "Micro SD" (at 24.13 0 90) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user USB (at -26.67 0) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 48 thru_hole circle (at -29.21 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 3 +5V))
+    (pad 47 thru_hole circle (at -26.67 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 4 GND))
+    (pad 46 thru_hole circle (at -24.13 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 5 +3V3))
+    (pad 45 thru_hole circle (at -21.59 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 50 TEENSY_A15))
+    (pad 44 thru_hole circle (at -19.05 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 63 TEENSY_P0))
+    (pad 43 thru_hole circle (at -16.51 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 76 TEENSY_IN_D7))
+    (pad 42 thru_hole circle (at -13.97 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 75 TEENSY_IN_D6))
+    (pad 41 thru_hole circle (at -11.43 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 74 TEENSY_IN_D5))
+    (pad 40 thru_hole circle (at -8.89 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 73 TEENSY_IN_D4))
+    (pad 39 thru_hole circle (at -6.35 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 72 TEENSY_IN_D3))
+    (pad 38 thru_hole circle (at -3.81 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 71 TEENSY_IN_D2))
+    (pad 37 thru_hole circle (at -1.27 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 70 TEENSY_IN_D1))
+    (pad 36 thru_hole circle (at 1.27 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 69 TEENSY_IN_D0))
+    (pad 35 thru_hole circle (at 3.81 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 61 TEENSY_P1))
+    (pad 1 thru_hole rect (at -29.21 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 4 GND))
+    (pad 2 thru_hole circle (at -26.67 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 52 TEENSY_A13))
+    (pad 3 thru_hole circle (at -24.13 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 53 TEENSY_A12))
+    (pad 4 thru_hole circle (at -21.59 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 51 TEENSY_A14))
+    (pad 5 thru_hole circle (at -19.05 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 85 TEENSY_DATA_OE_n))
+    (pad 6 thru_hole circle (at -16.51 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 77 TEENSY_OUT_D7))
+    (pad 7 thru_hole circle (at -13.97 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 78 TEENSY_OUT_D6))
+    (pad 8 thru_hole circle (at -11.43 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 79 TEENSY_OUT_D5))
+    (pad 9 thru_hole circle (at -8.89 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 80 TEENSY_OUT_D4))
+    (pad 10 thru_hole circle (at -6.35 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 81 TEENSY_OUT_D3))
+    (pad 11 thru_hole circle (at -3.81 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 82 TEENSY_OUT_D2))
+    (pad 12 thru_hole circle (at -1.27 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 83 TEENSY_OUT_D1))
+    (pad 13 thru_hole circle (at 1.27 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 84 TEENSY_OUT_D0))
+    (pad 34 thru_hole circle (at 6.35 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 4 GND))
+    (pad 33 thru_hole circle (at 8.89 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 86 TEENSY_NMI))
+    (pad 32 thru_hole circle (at 11.43 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 87 TEENSY_RST))
+    (pad 31 thru_hole circle (at 13.97 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 59 TEENSY_P2))
+    (pad 30 thru_hole circle (at 16.51 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 47 TEENSY_A1))
+    (pad 29 thru_hole circle (at 19.05 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 45 TEENSY_A3))
+    (pad 28 thru_hole circle (at 21.59 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 43 TEENSY_A5))
+    (pad 27 thru_hole circle (at 24.13 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 41 TEENSY_A7))
+    (pad 26 thru_hole circle (at 26.67 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 56 TEENSY_A9))
+    (pad 25 thru_hole circle (at 29.21 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 54 TEENSY_A11))
+    (pad 24 thru_hole circle (at 29.21 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 55 TEENSY_A10))
+    (pad 23 thru_hole circle (at 26.67 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 57 TEENSY_A8))
+    (pad 22 thru_hole circle (at 24.13 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 42 TEENSY_A6))
+    (pad 21 thru_hole circle (at 21.59 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 44 TEENSY_A4))
+    (pad 14 thru_hole circle (at 3.81 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 68 TEENSY_WR_n))
+    (pad 15 thru_hole circle (at 6.35 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 5 +3V3))
+    (pad 16 thru_hole circle (at 8.89 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 58 TEENSY_CLKIN))
+    (pad 20 thru_hole circle (at 19.05 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 46 TEENSY_A2))
+    (pad 19 thru_hole circle (at 16.51 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 48 TEENSY_A0))
+    (pad 18 thru_hole circle (at 13.97 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 88 TEENSY_READY_n))
+    (pad 17 thru_hole circle (at 11.43 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 89 TEENSY_IRQ))
+    (model ${KICAD_USER_DIR}/teensy.pretty/Teensy_4.1_Assembly.STEP
+      (offset (xyz 0 0 0.762))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_SO:SSOP-20_5.3x7.2mm_P0.65mm (layer Top.Cu) (tedit 5D9F72B1) (tstamp 604DA3DA)
+    (at 116.01196 107.10672)
+    (descr "SSOP, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/40001800C.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py")
+    (tags "SSOP SO")
+    (path /604F92C3)
+    (attr smd)
+    (fp_text reference U7 (at 0 -4.55) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 74LS244 (at 0 4.55) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 4.7 -3.85) (end -4.7 -3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 4.7 3.85) (end 4.7 -3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -4.7 3.85) (end 4.7 3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -4.7 -3.85) (end -4.7 3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.65 -2.6) (end -1.65 -3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start -2.65 3.6) (end -2.65 -2.6) (layer F.Fab) (width 0.1))
+    (fp_line (start 2.65 3.6) (end -2.65 3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start 2.65 -3.6) (end 2.65 3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.65 -3.6) (end 2.65 -3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start -2.76 -3.435) (end -4.45 -3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.76 -3.71) (end -2.76 -3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 -3.71) (end -2.76 -3.71) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.76 -3.71) (end 2.76 -3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 -3.71) (end 2.76 -3.71) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.76 3.71) (end -2.76 3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 3.71) (end -2.76 3.71) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.76 3.71) (end 2.76 3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 3.71) (end 2.76 3.71) (layer F.SilkS) (width 0.12))
+    (fp_text user %R (at 0 0) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 20 smd roundrect (at 3.5 -2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 5 +3V3))
+    (pad 19 smd roundrect (at 3.5 -2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 GND))
+    (pad 18 smd roundrect (at 3.5 -1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 12 CPU_WR_n))
+    (pad 17 smd roundrect (at 3.5 -0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 59 TEENSY_P2))
+    (pad 16 smd roundrect (at 3.5 -0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 60 "Net-(U7-Pad16)"))
+    (pad 15 smd roundrect (at 3.5 0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 61 TEENSY_P1))
+    (pad 14 smd roundrect (at 3.5 0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 62 "Net-(U7-Pad14)"))
+    (pad 13 smd roundrect (at 3.5 1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 63 TEENSY_P0))
+    (pad 12 smd roundrect (at 3.5 2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 64 "Net-(U7-Pad12)"))
+    (pad 11 smd roundrect (at 3.5 2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 6 CPU_CLKIN))
+    (pad 10 smd roundrect (at -3.5 2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 GND))
+    (pad 9 smd roundrect (at -3.5 2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 13 CPU_CLKOUT))
+    (pad 8 smd roundrect (at -3.5 1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 65 "Net-(U7-Pad8)"))
+    (pad 7 smd roundrect (at -3.5 0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 14 CPU_P0))
+    (pad 6 smd roundrect (at -3.5 0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 66 "Net-(U7-Pad6)"))
+    (pad 5 smd roundrect (at -3.5 -0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 15 CPU_P1))
+    (pad 4 smd roundrect (at -3.5 -0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 67 "Net-(U7-Pad4)"))
+    (pad 3 smd roundrect (at -3.5 -1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 16 CPU_P2))
+    (pad 2 smd roundrect (at -3.5 -2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 68 TEENSY_WR_n))
+    (pad 1 smd roundrect (at -3.5 -2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 49 CPU_AEC_n))
+    (model ${KISYS3DMOD}/Package_SO.3dshapes/SSOP-20_5.3x7.2mm_P0.65mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_SO:SSOP-14_5.3x6.2mm_P0.65mm (layer Top.Cu) (tedit 5A02F25C) (tstamp 604DA3B3)
+    (at 116.16436 91.87942)
+    (descr "SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot337-1_po.pdf)")
+    (tags "SSOP 0.65")
+    (path /604EF080)
+    (attr smd)
+    (fp_text reference U6 (at 0 -4.2) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 74LS04 (at 0 4.2) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start -2.775 -2.475) (end -4.05 -2.475) (layer F.SilkS) (width 0.15))
+    (fp_line (start -2.775 3.275) (end 2.775 3.275) (layer F.SilkS) (width 0.15))
+    (fp_line (start -2.775 -3.275) (end 2.775 -3.275) (layer F.SilkS) (width 0.15))
+    (fp_line (start -2.775 3.275) (end -2.775 2.375) (layer F.SilkS) (width 0.15))
+    (fp_line (start 2.775 3.275) (end 2.775 2.375) (layer F.SilkS) (width 0.15))
+    (fp_line (start 2.775 -3.275) (end 2.775 -2.375) (layer F.SilkS) (width 0.15))
+    (fp_line (start -2.775 -3.275) (end -2.775 -2.475) (layer F.SilkS) (width 0.15))
+    (fp_line (start -4.3 3.45) (end 4.3 3.45) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -4.3 -3.45) (end 4.3 -3.45) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 4.3 -3.45) (end 4.3 3.45) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -4.3 -3.45) (end -4.3 3.45) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.65 -2.1) (end -1.65 -3.1) (layer F.Fab) (width 0.15))
+    (fp_line (start -2.65 3.1) (end -2.65 -2.1) (layer F.Fab) (width 0.15))
+    (fp_line (start 2.65 3.1) (end -2.65 3.1) (layer F.Fab) (width 0.15))
+    (fp_line (start 2.65 -3.1) (end 2.65 3.1) (layer F.Fab) (width 0.15))
+    (fp_line (start -1.65 -3.1) (end 2.65 -3.1) (layer F.Fab) (width 0.15))
+    (fp_text user %R (at 0 0) (layer F.Fab)
+      (effects (font (size 0.8 0.8) (thickness 0.15)))
+    )
+    (pad 14 smd rect (at 3.45 -1.95) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 5 +3V3))
+    (pad 13 smd rect (at 3.45 -1.3) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 6 CPU_CLKIN))
+    (pad 12 smd rect (at 3.45 -0.65) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 58 TEENSY_CLKIN))
+    (pad 11 smd rect (at 3.45 0) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 7 CPU_RST_n))
+    (pad 10 smd rect (at 3.45 0.65) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 87 TEENSY_RST))
+    (pad 9 smd rect (at 3.45 1.3) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 8 CPU_NMI_n))
+    (pad 8 smd rect (at 3.45 1.95) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 86 TEENSY_NMI))
+    (pad 7 smd rect (at -3.45 1.95) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 4 GND))
+    (pad 6 smd rect (at -3.45 1.3) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 89 TEENSY_IRQ))
+    (pad 5 smd rect (at -3.45 0.65) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 9 CPU_IRQ_n))
+    (pad 4 smd rect (at -3.45 0) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 88 TEENSY_READY_n))
+    (pad 3 smd rect (at -3.45 -0.65) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 10 CPU_READY))
+    (pad 2 smd rect (at -3.45 -1.3) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 49 CPU_AEC_n))
+    (pad 1 smd rect (at -3.45 -1.95) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 11 CPU_AEC))
+    (model ${KISYS3DMOD}/Package_SO.3dshapes/SSOP-14_5.3x6.2mm_P0.65mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_SO:SSOP-20_5.3x7.2mm_P0.65mm (layer Top.Cu) (tedit 5D9F72B1) (tstamp 604DAB21)
+    (at 97.74174 120.85828)
+    (descr "SSOP, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/40001800C.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py")
+    (tags "SSOP SO")
+    (path /605FE39B)
+    (attr smd)
+    (fp_text reference U5 (at 0 -4.55) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 74LS573 (at 0 4.55) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 4.7 -3.85) (end -4.7 -3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 4.7 3.85) (end 4.7 -3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -4.7 3.85) (end 4.7 3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -4.7 -3.85) (end -4.7 3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.65 -2.6) (end -1.65 -3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start -2.65 3.6) (end -2.65 -2.6) (layer F.Fab) (width 0.1))
+    (fp_line (start 2.65 3.6) (end -2.65 3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start 2.65 -3.6) (end 2.65 3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.65 -3.6) (end 2.65 -3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start -2.76 -3.435) (end -4.45 -3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.76 -3.71) (end -2.76 -3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 -3.71) (end -2.76 -3.71) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.76 -3.71) (end 2.76 -3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 -3.71) (end 2.76 -3.71) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.76 3.71) (end -2.76 3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 3.71) (end -2.76 3.71) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.76 3.71) (end 2.76 3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 3.71) (end 2.76 3.71) (layer F.SilkS) (width 0.12))
+    (fp_text user %R (at 0 0) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 20 smd roundrect (at 3.5 -2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 5 +3V3))
+    (pad 19 smd roundrect (at 3.5 -2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 20 CPU_D0))
+    (pad 18 smd roundrect (at 3.5 -1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 22 CPU_D1))
+    (pad 17 smd roundrect (at 3.5 -0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 24 CPU_D2))
+    (pad 16 smd roundrect (at 3.5 -0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 26 CPU_D3))
+    (pad 15 smd roundrect (at 3.5 0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 28 CPU_D4))
+    (pad 14 smd roundrect (at 3.5 0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 30 CPU_D5))
+    (pad 13 smd roundrect (at 3.5 1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 32 CPU_D6))
+    (pad 12 smd roundrect (at 3.5 2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 34 CPU_D7))
+    (pad 11 smd roundrect (at 3.5 2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 5 +3V3))
+    (pad 10 smd roundrect (at -3.5 2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 GND))
+    (pad 9 smd roundrect (at -3.5 2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 77 TEENSY_OUT_D7))
+    (pad 8 smd roundrect (at -3.5 1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 78 TEENSY_OUT_D6))
+    (pad 7 smd roundrect (at -3.5 0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 79 TEENSY_OUT_D5))
+    (pad 6 smd roundrect (at -3.5 0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 80 TEENSY_OUT_D4))
+    (pad 5 smd roundrect (at -3.5 -0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 81 TEENSY_OUT_D3))
+    (pad 4 smd roundrect (at -3.5 -0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 82 TEENSY_OUT_D2))
+    (pad 3 smd roundrect (at -3.5 -1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 83 TEENSY_OUT_D1))
+    (pad 2 smd roundrect (at -3.5 -2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 84 TEENSY_OUT_D0))
+    (pad 1 smd roundrect (at -3.5 -2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 85 TEENSY_DATA_OE_n))
+    (model ${KISYS3DMOD}/Package_SO.3dshapes/SSOP-20_5.3x7.2mm_P0.65mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_SO:SSOP-20_5.3x7.2mm_P0.65mm (layer Bottom.Cu) (tedit 5D9F72B1) (tstamp 604DAAF6)
+    (at 97.77476 120.82526 180)
+    (descr "SSOP, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/40001800C.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py")
+    (tags "SSOP SO")
+    (path /6058D2B5)
+    (attr smd)
+    (fp_text reference U4 (at 0 4.55) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 74LS573 (at 0 -4.55) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start 4.7 3.85) (end -4.7 3.85) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 4.7 -3.85) (end 4.7 3.85) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -4.7 -3.85) (end 4.7 -3.85) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -4.7 3.85) (end -4.7 -3.85) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -2.65 2.6) (end -1.65 3.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -2.65 -3.6) (end -2.65 2.6) (layer B.Fab) (width 0.1))
+    (fp_line (start 2.65 -3.6) (end -2.65 -3.6) (layer B.Fab) (width 0.1))
+    (fp_line (start 2.65 3.6) (end 2.65 -3.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -1.65 3.6) (end 2.65 3.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -2.76 3.435) (end -4.45 3.435) (layer B.SilkS) (width 0.12))
+    (fp_line (start -2.76 3.71) (end -2.76 3.435) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 3.71) (end -2.76 3.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start 2.76 3.71) (end 2.76 3.435) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 3.71) (end 2.76 3.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start -2.76 -3.71) (end -2.76 -3.435) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 -3.71) (end -2.76 -3.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start 2.76 -3.71) (end 2.76 -3.435) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 -3.71) (end 2.76 -3.71) (layer B.SilkS) (width 0.12))
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (pad 20 smd roundrect (at 3.5 2.925 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 5 +3V3))
+    (pad 19 smd roundrect (at 3.5 2.275 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 69 TEENSY_IN_D0))
+    (pad 18 smd roundrect (at 3.5 1.625 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 70 TEENSY_IN_D1))
+    (pad 17 smd roundrect (at 3.5 0.975 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 71 TEENSY_IN_D2))
+    (pad 16 smd roundrect (at 3.5 0.325 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 72 TEENSY_IN_D3))
+    (pad 15 smd roundrect (at 3.5 -0.325 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 73 TEENSY_IN_D4))
+    (pad 14 smd roundrect (at 3.5 -0.975 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 74 TEENSY_IN_D5))
+    (pad 13 smd roundrect (at 3.5 -1.625 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 75 TEENSY_IN_D6))
+    (pad 12 smd roundrect (at 3.5 -2.275 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 76 TEENSY_IN_D7))
+    (pad 11 smd roundrect (at 3.5 -2.925 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 6 CPU_CLKIN))
+    (pad 10 smd roundrect (at -3.5 -2.925 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 GND))
+    (pad 9 smd roundrect (at -3.5 -2.275 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 34 CPU_D7))
+    (pad 8 smd roundrect (at -3.5 -1.625 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 32 CPU_D6))
+    (pad 7 smd roundrect (at -3.5 -0.975 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 30 CPU_D5))
+    (pad 6 smd roundrect (at -3.5 -0.325 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 28 CPU_D4))
+    (pad 5 smd roundrect (at -3.5 0.325 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 26 CPU_D3))
+    (pad 4 smd roundrect (at -3.5 0.975 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 24 CPU_D2))
+    (pad 3 smd roundrect (at -3.5 1.625 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 22 CPU_D1))
+    (pad 2 smd roundrect (at -3.5 2.275 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 20 CPU_D0))
+    (pad 1 smd roundrect (at -3.5 2.925 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 GND))
+    (model ${KISYS3DMOD}/Package_SO.3dshapes/SSOP-20_5.3x7.2mm_P0.65mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_SO:SSOP-20_5.3x7.2mm_P0.65mm (layer Bottom.Cu) (tedit 5D9F72B1) (tstamp 604DA393)
+    (at 116.21516 126.2126 180)
+    (descr "SSOP, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/40001800C.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py")
+    (tags "SSOP SO")
+    (path /605D8A68)
+    (attr smd)
+    (fp_text reference U3 (at 0 4.55) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 74LS573 (at 0 -4.55) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start 4.7 3.85) (end -4.7 3.85) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 4.7 -3.85) (end 4.7 3.85) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -4.7 -3.85) (end 4.7 -3.85) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -4.7 3.85) (end -4.7 -3.85) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -2.65 2.6) (end -1.65 3.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -2.65 -3.6) (end -2.65 2.6) (layer B.Fab) (width 0.1))
+    (fp_line (start 2.65 -3.6) (end -2.65 -3.6) (layer B.Fab) (width 0.1))
+    (fp_line (start 2.65 3.6) (end 2.65 -3.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -1.65 3.6) (end 2.65 3.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -2.76 3.435) (end -4.45 3.435) (layer B.SilkS) (width 0.12))
+    (fp_line (start -2.76 3.71) (end -2.76 3.435) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 3.71) (end -2.76 3.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start 2.76 3.71) (end 2.76 3.435) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 3.71) (end 2.76 3.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start -2.76 -3.71) (end -2.76 -3.435) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 -3.71) (end -2.76 -3.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start 2.76 -3.71) (end 2.76 -3.435) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 -3.71) (end 2.76 -3.71) (layer B.SilkS) (width 0.12))
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (pad 20 smd roundrect (at 3.5 2.925 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 5 +3V3))
+    (pad 19 smd roundrect (at 3.5 2.275 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 25 CPU_A8))
+    (pad 18 smd roundrect (at 3.5 1.625 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 23 CPU_A9))
+    (pad 17 smd roundrect (at 3.5 0.975 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 21 CPU_A10))
+    (pad 16 smd roundrect (at 3.5 0.325 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 19 CPU_A11))
+    (pad 15 smd roundrect (at 3.5 -0.325 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 18 CPU_A12))
+    (pad 14 smd roundrect (at 3.5 -0.975 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 17 CPU_A13))
+    (pad 13 smd roundrect (at 3.5 -1.625 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 40 CPU_A14))
+    (pad 12 smd roundrect (at 3.5 -2.275 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 39 CPU_A15))
+    (pad 11 smd roundrect (at 3.5 -2.925 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 5 +3V3))
+    (pad 10 smd roundrect (at -3.5 -2.925 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 GND))
+    (pad 9 smd roundrect (at -3.5 -2.275 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 50 TEENSY_A15))
+    (pad 8 smd roundrect (at -3.5 -1.625 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 51 TEENSY_A14))
+    (pad 7 smd roundrect (at -3.5 -0.975 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 52 TEENSY_A13))
+    (pad 6 smd roundrect (at -3.5 -0.325 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 53 TEENSY_A12))
+    (pad 5 smd roundrect (at -3.5 0.325 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 54 TEENSY_A11))
+    (pad 4 smd roundrect (at -3.5 0.975 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 55 TEENSY_A10))
+    (pad 3 smd roundrect (at -3.5 1.625 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 56 TEENSY_A9))
+    (pad 2 smd roundrect (at -3.5 2.275 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 57 TEENSY_A8))
+    (pad 1 smd roundrect (at -3.5 2.925 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 49 CPU_AEC_n))
+    (model ${KISYS3DMOD}/Package_SO.3dshapes/SSOP-20_5.3x7.2mm_P0.65mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_SO:SSOP-20_5.3x7.2mm_P0.65mm (layer Top.Cu) (tedit 5D9F72B1) (tstamp 604DA368)
+    (at 97.33534 107.00258)
+    (descr "SSOP, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/40001800C.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py")
+    (tags "SSOP SO")
+    (path /605A5248)
+    (attr smd)
+    (fp_text reference U2 (at 0 -4.55) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 74LS573 (at 0 4.55) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 4.7 -3.85) (end -4.7 -3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 4.7 3.85) (end 4.7 -3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -4.7 3.85) (end 4.7 3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -4.7 -3.85) (end -4.7 3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.65 -2.6) (end -1.65 -3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start -2.65 3.6) (end -2.65 -2.6) (layer F.Fab) (width 0.1))
+    (fp_line (start 2.65 3.6) (end -2.65 3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start 2.65 -3.6) (end 2.65 3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.65 -3.6) (end 2.65 -3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start -2.76 -3.435) (end -4.45 -3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.76 -3.71) (end -2.76 -3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 -3.71) (end -2.76 -3.71) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.76 -3.71) (end 2.76 -3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 -3.71) (end 2.76 -3.71) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.76 3.71) (end -2.76 3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 3.71) (end -2.76 3.71) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.76 3.71) (end 2.76 3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 3.71) (end 2.76 3.71) (layer F.SilkS) (width 0.12))
+    (fp_text user %R (at 0 0) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 20 smd roundrect (at 3.5 -2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 5 +3V3))
+    (pad 19 smd roundrect (at 3.5 -2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 38 CPU_A0))
+    (pad 18 smd roundrect (at 3.5 -1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 37 CPU_A1))
+    (pad 17 smd roundrect (at 3.5 -0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 36 CPU_A2))
+    (pad 16 smd roundrect (at 3.5 -0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 35 CPU_A3))
+    (pad 15 smd roundrect (at 3.5 0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 33 CPU_A4))
+    (pad 14 smd roundrect (at 3.5 0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 31 CPU_A5))
+    (pad 13 smd roundrect (at 3.5 1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 29 CPU_A6))
+    (pad 12 smd roundrect (at 3.5 2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 27 CPU_A7))
+    (pad 11 smd roundrect (at 3.5 2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 5 +3V3))
+    (pad 10 smd roundrect (at -3.5 2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 GND))
+    (pad 9 smd roundrect (at -3.5 2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 41 TEENSY_A7))
+    (pad 8 smd roundrect (at -3.5 1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 42 TEENSY_A6))
+    (pad 7 smd roundrect (at -3.5 0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 43 TEENSY_A5))
+    (pad 6 smd roundrect (at -3.5 0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 44 TEENSY_A4))
+    (pad 5 smd roundrect (at -3.5 -0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 45 TEENSY_A3))
+    (pad 4 smd roundrect (at -3.5 -0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 46 TEENSY_A2))
+    (pad 3 smd roundrect (at -3.5 -1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 47 TEENSY_A1))
+    (pad 2 smd roundrect (at -3.5 -2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 48 TEENSY_A0))
+    (pad 1 smd roundrect (at -3.5 -2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 49 CPU_AEC_n))
+    (model ${KISYS3DMOD}/Package_SO.3dshapes/SSOP-20_5.3x7.2mm_P0.65mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_DIP:DIP-40_W15.24mm (layer Top.Cu) (tedit 5A02E8C5) (tstamp 604C633D)
+    (at 108.63326 84.2264)
+    (descr "40-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils)")
+    (tags "THT DIP DIL PDIP 2.54mm 15.24mm 600mil")
+    (path /604E276C)
+    (fp_text reference U8 (at 7.62 -2.33) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 6510 (at 7.62 50.59) (layer F.Fab) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 1.255 -1.27) (end 14.985 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 14.985 -1.27) (end 14.985 49.53) (layer F.Fab) (width 0.1))
+    (fp_line (start 14.985 49.53) (end 0.255 49.53) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.255 49.53) (end 0.255 -0.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.255 -0.27) (end 1.255 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 6.62 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.16 -1.33) (end 1.16 49.59) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.16 49.59) (end 14.08 49.59) (layer F.SilkS) (width 0.12))
+    (fp_line (start 14.08 49.59) (end 14.08 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start 14.08 -1.33) (end 8.62 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.05 -1.55) (end -1.05 49.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.05 49.8) (end 16.3 49.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 16.3 49.8) (end 16.3 -1.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 16.3 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 7.62 24.13) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_arc (start 7.62 -1.33) (end 6.62 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
+    (pad 40 thru_hole oval (at 15.24 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 7 CPU_RST_n))
+    (pad 20 thru_hole oval (at 0 48.26) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 17 CPU_A13))
+    (pad 39 thru_hole oval (at 15.24 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 13 CPU_CLKOUT))
+    (pad 19 thru_hole oval (at 0 45.72) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 18 CPU_A12))
+    (pad 38 thru_hole oval (at 15.24 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 12 CPU_WR_n))
+    (pad 18 thru_hole oval (at 0 43.18) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 19 CPU_A11))
+    (pad 37 thru_hole oval (at 15.24 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 20 CPU_D0))
+    (pad 17 thru_hole oval (at 0 40.64) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 21 CPU_A10))
+    (pad 36 thru_hole oval (at 15.24 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 22 CPU_D1))
+    (pad 16 thru_hole oval (at 0 38.1) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 23 CPU_A9))
+    (pad 35 thru_hole oval (at 15.24 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 24 CPU_D2))
+    (pad 15 thru_hole oval (at 0 35.56) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 25 CPU_A8))
+    (pad 34 thru_hole oval (at 15.24 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 26 CPU_D3))
+    (pad 14 thru_hole oval (at 0 33.02) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 27 CPU_A7))
+    (pad 33 thru_hole oval (at 15.24 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 28 CPU_D4))
+    (pad 13 thru_hole oval (at 0 30.48) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 29 CPU_A6))
+    (pad 32 thru_hole oval (at 15.24 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 30 CPU_D5))
+    (pad 12 thru_hole oval (at 0 27.94) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 31 CPU_A5))
+    (pad 31 thru_hole oval (at 15.24 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 32 CPU_D6))
+    (pad 11 thru_hole oval (at 0 25.4) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 33 CPU_A4))
+    (pad 30 thru_hole oval (at 15.24 25.4) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 34 CPU_D7))
+    (pad 10 thru_hole oval (at 0 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 35 CPU_A3))
+    (pad 29 thru_hole oval (at 15.24 27.94) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 14 CPU_P0))
+    (pad 9 thru_hole oval (at 0 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 36 CPU_A2))
+    (pad 28 thru_hole oval (at 15.24 30.48) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 15 CPU_P1))
+    (pad 8 thru_hole oval (at 0 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 37 CPU_A1))
+    (pad 27 thru_hole oval (at 15.24 33.02) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 16 CPU_P2))
+    (pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 38 CPU_A0))
+    (pad 26 thru_hole oval (at 15.24 35.56) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 1 "Net-(U8-Pad26)"))
+    (pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 3 +5V))
+    (pad 25 thru_hole oval (at 15.24 38.1) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 2 "Net-(U8-Pad25)"))
+    (pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 11 CPU_AEC))
+    (pad 24 thru_hole oval (at 15.24 40.64) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 4 GND))
+    (pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 8 CPU_NMI_n))
+    (pad 23 thru_hole oval (at 15.24 43.18) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 39 CPU_A15))
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diff --git a/MCL64/PCB/MCL64/MCL64.kicad_pcb-bak b/MCL64/PCB/MCL64/MCL64.kicad_pcb-bak
new file mode 100644
index 0000000..09f48b0
--- /dev/null
+++ b/MCL64/PCB/MCL64/MCL64.kicad_pcb-bak
@@ -0,0 +1,3357 @@
+(kicad_pcb (version 20171130) (host pcbnew "(5.1.8)-1")
+
+  (general
+    (thickness 1.6)
+    (drawings 6)
+    (tracks 667)
+    (zones 0)
+    (modules 9)
+    (nets 90)
+  )
+
+  (page A4)
+  (layers
+    (0 Top.Cu signal)
+    (1 Inner1.Cu signal hide)
+    (2 Inner2.Cu signal hide)
+    (31 Bottom.Cu signal)
+    (32 B.Adhes user hide)
+    (33 F.Adhes user hide)
+    (34 B.Paste user hide)
+    (35 F.Paste user hide)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user hide)
+    (39 F.Mask user hide)
+    (40 Dwgs.User user hide)
+    (41 Cmts.User user hide)
+    (42 Eco1.User user hide)
+    (43 Eco2.User user hide)
+    (44 Edge.Cuts user)
+    (45 Margin user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.1778)
+    (trace_clearance 0.127)
+    (zone_clearance 0.254)
+    (zone_45_only no)
+    (trace_min 0.1778)
+    (via_size 0.6)
+    (via_drill 0.4)
+    (via_min_size 0.3556)
+    (via_min_drill 0.2794)
+    (uvia_size 0.3)
+    (uvia_drill 0.1)
+    (uvias_allowed no)
+    (uvia_min_size 0.2)
+    (uvia_min_drill 0.1)
+    (edge_width 0.05)
+    (segment_width 0.2)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.12)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 1.524 1.524)
+    (pad_drill 0.762)
+    (pad_to_mask_clearance 0)
+    (aux_axis_origin 87.48776 143.96212)
+    (grid_origin 87.48776 143.96212)
+    (visible_elements 7FFDFF7F)
+    (pcbplotparams
+      (layerselection 0x010fc_ffffffff)
+      (usegerberextensions false)
+      (usegerberattributes true)
+      (usegerberadvancedattributes true)
+      (creategerberjobfile true)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 1)
+      (scaleselection 1)
+      (outputdirectory ""))
+  )
+
+  (net 0 "")
+  (net 1 "Net-(U8-Pad26)")
+  (net 2 "Net-(U8-Pad25)")
+  (net 3 +5V)
+  (net 4 GND)
+  (net 5 +3V3)
+  (net 6 CPU_CLKIN)
+  (net 7 CPU_RST_n)
+  (net 8 CPU_NMI_n)
+  (net 9 CPU_IRQ_n)
+  (net 10 CPU_READY)
+  (net 11 CPU_AEC)
+  (net 12 CPU_WR_n)
+  (net 13 CPU_CLKOUT)
+  (net 14 CPU_P0)
+  (net 15 CPU_P1)
+  (net 16 CPU_P2)
+  (net 17 CPU_A13)
+  (net 18 CPU_A12)
+  (net 19 CPU_A11)
+  (net 20 CPU_D0)
+  (net 21 CPU_A10)
+  (net 22 CPU_D1)
+  (net 23 CPU_A9)
+  (net 24 CPU_D2)
+  (net 25 CPU_A8)
+  (net 26 CPU_D3)
+  (net 27 CPU_A7)
+  (net 28 CPU_D4)
+  (net 29 CPU_A6)
+  (net 30 CPU_D5)
+  (net 31 CPU_A5)
+  (net 32 CPU_D6)
+  (net 33 CPU_A4)
+  (net 34 CPU_D7)
+  (net 35 CPU_A3)
+  (net 36 CPU_A2)
+  (net 37 CPU_A1)
+  (net 38 CPU_A0)
+  (net 39 CPU_A15)
+  (net 40 CPU_A14)
+  (net 41 TEENSY_A7)
+  (net 42 TEENSY_A6)
+  (net 43 TEENSY_A5)
+  (net 44 TEENSY_A4)
+  (net 45 TEENSY_A3)
+  (net 46 TEENSY_A2)
+  (net 47 TEENSY_A1)
+  (net 48 TEENSY_A0)
+  (net 49 CPU_AEC_n)
+  (net 50 TEENSY_A15)
+  (net 51 TEENSY_A14)
+  (net 52 TEENSY_A13)
+  (net 53 TEENSY_A12)
+  (net 54 TEENSY_A11)
+  (net 55 TEENSY_A10)
+  (net 56 TEENSY_A9)
+  (net 57 TEENSY_A8)
+  (net 58 TEENSY_CLKIN)
+  (net 59 TEENSY_P2)
+  (net 60 "Net-(U7-Pad16)")
+  (net 61 TEENSY_P1)
+  (net 62 "Net-(U7-Pad14)")
+  (net 63 TEENSY_P0)
+  (net 64 "Net-(U7-Pad12)")
+  (net 65 "Net-(U7-Pad8)")
+  (net 66 "Net-(U7-Pad6)")
+  (net 67 "Net-(U7-Pad4)")
+  (net 68 TEENSY_WR_n)
+  (net 69 TEENSY_IN_D0)
+  (net 70 TEENSY_IN_D1)
+  (net 71 TEENSY_IN_D2)
+  (net 72 TEENSY_IN_D3)
+  (net 73 TEENSY_IN_D4)
+  (net 74 TEENSY_IN_D5)
+  (net 75 TEENSY_IN_D6)
+  (net 76 TEENSY_IN_D7)
+  (net 77 TEENSY_OUT_D7)
+  (net 78 TEENSY_OUT_D6)
+  (net 79 TEENSY_OUT_D5)
+  (net 80 TEENSY_OUT_D4)
+  (net 81 TEENSY_OUT_D3)
+  (net 82 TEENSY_OUT_D2)
+  (net 83 TEENSY_OUT_D1)
+  (net 84 TEENSY_OUT_D0)
+  (net 85 TEENSY_DATA_OE_n)
+  (net 86 TEENSY_NMI)
+  (net 87 TEENSY_RST)
+  (net 88 TEENSY_READY_n)
+  (net 89 TEENSY_IRQ)
+
+  (net_class Default "This is the default net class."
+    (clearance 0.127)
+    (trace_width 0.1778)
+    (via_dia 0.6)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    (add_net +3V3)
+    (add_net +5V)
+    (add_net CPU_A0)
+    (add_net CPU_A1)
+    (add_net CPU_A10)
+    (add_net CPU_A11)
+    (add_net CPU_A12)
+    (add_net CPU_A13)
+    (add_net CPU_A14)
+    (add_net CPU_A15)
+    (add_net CPU_A2)
+    (add_net CPU_A3)
+    (add_net CPU_A4)
+    (add_net CPU_A5)
+    (add_net CPU_A6)
+    (add_net CPU_A7)
+    (add_net CPU_A8)
+    (add_net CPU_A9)
+    (add_net CPU_AEC)
+    (add_net CPU_AEC_n)
+    (add_net CPU_CLKIN)
+    (add_net CPU_CLKOUT)
+    (add_net CPU_D0)
+    (add_net CPU_D1)
+    (add_net CPU_D2)
+    (add_net CPU_D3)
+    (add_net CPU_D4)
+    (add_net CPU_D5)
+    (add_net CPU_D6)
+    (add_net CPU_D7)
+    (add_net CPU_IRQ_n)
+    (add_net CPU_NMI_n)
+    (add_net CPU_P0)
+    (add_net CPU_P1)
+    (add_net CPU_P2)
+    (add_net CPU_READY)
+    (add_net CPU_RST_n)
+    (add_net CPU_WR_n)
+    (add_net GND)
+    (add_net "Net-(U7-Pad12)")
+    (add_net "Net-(U7-Pad14)")
+    (add_net "Net-(U7-Pad16)")
+    (add_net "Net-(U7-Pad4)")
+    (add_net "Net-(U7-Pad6)")
+    (add_net "Net-(U7-Pad8)")
+    (add_net "Net-(U8-Pad25)")
+    (add_net "Net-(U8-Pad26)")
+    (add_net TEENSY_A0)
+    (add_net TEENSY_A1)
+    (add_net TEENSY_A10)
+    (add_net TEENSY_A11)
+    (add_net TEENSY_A12)
+    (add_net TEENSY_A13)
+    (add_net TEENSY_A14)
+    (add_net TEENSY_A15)
+    (add_net TEENSY_A2)
+    (add_net TEENSY_A3)
+    (add_net TEENSY_A4)
+    (add_net TEENSY_A5)
+    (add_net TEENSY_A6)
+    (add_net TEENSY_A7)
+    (add_net TEENSY_A8)
+    (add_net TEENSY_A9)
+    (add_net TEENSY_CLKIN)
+    (add_net TEENSY_DATA_OE_n)
+    (add_net TEENSY_IN_D0)
+    (add_net TEENSY_IN_D1)
+    (add_net TEENSY_IN_D2)
+    (add_net TEENSY_IN_D3)
+    (add_net TEENSY_IN_D4)
+    (add_net TEENSY_IN_D5)
+    (add_net TEENSY_IN_D6)
+    (add_net TEENSY_IN_D7)
+    (add_net TEENSY_IRQ)
+    (add_net TEENSY_NMI)
+    (add_net TEENSY_OUT_D0)
+    (add_net TEENSY_OUT_D1)
+    (add_net TEENSY_OUT_D2)
+    (add_net TEENSY_OUT_D3)
+    (add_net TEENSY_OUT_D4)
+    (add_net TEENSY_OUT_D5)
+    (add_net TEENSY_OUT_D6)
+    (add_net TEENSY_OUT_D7)
+    (add_net TEENSY_P0)
+    (add_net TEENSY_P1)
+    (add_net TEENSY_P2)
+    (add_net TEENSY_READY_n)
+    (add_net TEENSY_RST)
+    (add_net TEENSY_WR_n)
+  )
+
+  (module Capacitor_THT:C_Disc_D7.0mm_W2.5mm_P5.00mm (layer Top.Cu) (tedit 5AE50EF0) (tstamp 604ECE63)
+    (at 113.53292 136.4107)
+    (descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=7*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf")
+    (tags "C Disc series Radial pin pitch 5.00mm  diameter 7mm width 2.5mm Capacitor")
+    (path /60529805)
+    (fp_text reference C1 (at 2.5 -2.5) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 10uF (at 2.5 2.5) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 6.25 -1.5) (end -1.25 -1.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 6.25 1.5) (end 6.25 -1.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.25 1.5) (end 6.25 1.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.25 -1.5) (end -1.25 1.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 6.12 -1.37) (end 6.12 1.37) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.12 -1.37) (end -1.12 1.37) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.12 1.37) (end 6.12 1.37) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.12 -1.37) (end 6.12 -1.37) (layer F.SilkS) (width 0.12))
+    (fp_line (start 6 -1.25) (end -1 -1.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 6 1.25) (end 6 -1.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -1 1.25) (end 6 1.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -1 -1.25) (end -1 1.25) (layer F.Fab) (width 0.1))
+    (fp_text user %R (at 2.5 0) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 2 thru_hole circle (at 5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 4 GND))
+    (pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 5 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D7.0mm_W2.5mm_P5.00mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Teensy:Teensy41_Ted_Modified (layer Top.Cu) (tedit 604DAF9D) (tstamp 604C690F)
+    (at 97.46742 113.40846 90)
+    (path /604E31A7)
+    (fp_text reference U1 (at 31.46298 0.14478) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value "Teensy 4.1" (at 0 10.16 90) (layer F.Fab) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start -30.48 8.89) (end -30.48 -8.89) (layer F.SilkS) (width 0.15))
+    (fp_line (start 30.48 8.89) (end -30.48 8.89) (layer F.SilkS) (width 0.15))
+    (fp_line (start 30.48 -8.89) (end 30.48 8.89) (layer F.SilkS) (width 0.15))
+    (fp_line (start -30.48 -8.89) (end 30.48 -8.89) (layer F.SilkS) (width 0.15))
+    (fp_line (start -25.4 3.81) (end -30.48 3.81) (layer F.SilkS) (width 0.15))
+    (fp_line (start -25.4 -3.81) (end -30.48 -3.81) (layer F.SilkS) (width 0.15))
+    (fp_line (start -25.4 3.81) (end -25.4 -3.81) (layer F.SilkS) (width 0.15))
+    (fp_line (start -31.75 -3.81) (end -30.48 -3.81) (layer F.SilkS) (width 0.15))
+    (fp_line (start -31.75 3.81) (end -31.75 -3.81) (layer F.SilkS) (width 0.15))
+    (fp_line (start -30.48 3.81) (end -31.75 3.81) (layer F.SilkS) (width 0.15))
+    (fp_line (start 30.48 -6.35) (end 17.78 -6.35) (layer F.SilkS) (width 0.15))
+    (fp_line (start 17.78 -6.35) (end 17.78 6.35) (layer F.SilkS) (width 0.15))
+    (fp_line (start 17.78 6.35) (end 30.48 6.35) (layer F.SilkS) (width 0.15))
+    (fp_line (start 30.48 -5.08) (end 29.21 -5.08) (layer F.SilkS) (width 0.15))
+    (fp_line (start 29.21 -5.08) (end 29.21 5.08) (layer F.SilkS) (width 0.15))
+    (fp_line (start 29.21 5.08) (end 30.48 5.08) (layer F.SilkS) (width 0.15))
+    (fp_text user "Micro SD" (at 24.13 0 90) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user USB (at -26.67 0) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 48 thru_hole circle (at -29.21 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 3 +5V))
+    (pad 47 thru_hole circle (at -26.67 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 4 GND))
+    (pad 46 thru_hole circle (at -24.13 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 5 +3V3))
+    (pad 45 thru_hole circle (at -21.59 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 50 TEENSY_A15))
+    (pad 44 thru_hole circle (at -19.05 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 63 TEENSY_P0))
+    (pad 43 thru_hole circle (at -16.51 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 76 TEENSY_IN_D7))
+    (pad 42 thru_hole circle (at -13.97 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 75 TEENSY_IN_D6))
+    (pad 41 thru_hole circle (at -11.43 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 74 TEENSY_IN_D5))
+    (pad 40 thru_hole circle (at -8.89 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 73 TEENSY_IN_D4))
+    (pad 39 thru_hole circle (at -6.35 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 72 TEENSY_IN_D3))
+    (pad 38 thru_hole circle (at -3.81 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 71 TEENSY_IN_D2))
+    (pad 37 thru_hole circle (at -1.27 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 70 TEENSY_IN_D1))
+    (pad 36 thru_hole circle (at 1.27 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 69 TEENSY_IN_D0))
+    (pad 35 thru_hole circle (at 3.81 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 61 TEENSY_P1))
+    (pad 1 thru_hole rect (at -29.21 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 4 GND))
+    (pad 2 thru_hole circle (at -26.67 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 52 TEENSY_A13))
+    (pad 3 thru_hole circle (at -24.13 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 53 TEENSY_A12))
+    (pad 4 thru_hole circle (at -21.59 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 51 TEENSY_A14))
+    (pad 5 thru_hole circle (at -19.05 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 85 TEENSY_DATA_OE_n))
+    (pad 6 thru_hole circle (at -16.51 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 77 TEENSY_OUT_D7))
+    (pad 7 thru_hole circle (at -13.97 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 78 TEENSY_OUT_D6))
+    (pad 8 thru_hole circle (at -11.43 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 79 TEENSY_OUT_D5))
+    (pad 9 thru_hole circle (at -8.89 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 80 TEENSY_OUT_D4))
+    (pad 10 thru_hole circle (at -6.35 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 81 TEENSY_OUT_D3))
+    (pad 11 thru_hole circle (at -3.81 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 82 TEENSY_OUT_D2))
+    (pad 12 thru_hole circle (at -1.27 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 83 TEENSY_OUT_D1))
+    (pad 13 thru_hole circle (at 1.27 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 84 TEENSY_OUT_D0))
+    (pad 34 thru_hole circle (at 6.35 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 4 GND))
+    (pad 33 thru_hole circle (at 8.89 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 86 TEENSY_NMI))
+    (pad 32 thru_hole circle (at 11.43 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 87 TEENSY_RST))
+    (pad 31 thru_hole circle (at 13.97 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 59 TEENSY_P2))
+    (pad 30 thru_hole circle (at 16.51 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 47 TEENSY_A1))
+    (pad 29 thru_hole circle (at 19.05 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 45 TEENSY_A3))
+    (pad 28 thru_hole circle (at 21.59 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 43 TEENSY_A5))
+    (pad 27 thru_hole circle (at 24.13 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 41 TEENSY_A7))
+    (pad 26 thru_hole circle (at 26.67 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 56 TEENSY_A9))
+    (pad 25 thru_hole circle (at 29.21 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 54 TEENSY_A11))
+    (pad 24 thru_hole circle (at 29.21 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 55 TEENSY_A10))
+    (pad 23 thru_hole circle (at 26.67 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 57 TEENSY_A8))
+    (pad 22 thru_hole circle (at 24.13 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 42 TEENSY_A6))
+    (pad 21 thru_hole circle (at 21.59 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 44 TEENSY_A4))
+    (pad 14 thru_hole circle (at 3.81 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 68 TEENSY_WR_n))
+    (pad 15 thru_hole circle (at 6.35 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 5 +3V3))
+    (pad 16 thru_hole circle (at 8.89 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 58 TEENSY_CLKIN))
+    (pad 20 thru_hole circle (at 19.05 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 46 TEENSY_A2))
+    (pad 19 thru_hole circle (at 16.51 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 48 TEENSY_A0))
+    (pad 18 thru_hole circle (at 13.97 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 88 TEENSY_READY_n))
+    (pad 17 thru_hole circle (at 11.43 7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask)
+      (net 89 TEENSY_IRQ))
+    (model ${KICAD_USER_DIR}/teensy.pretty/Teensy_4.1_Assembly.STEP
+      (offset (xyz 0 0 0.762))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_SO:SSOP-20_5.3x7.2mm_P0.65mm (layer Top.Cu) (tedit 5D9F72B1) (tstamp 604DA3DA)
+    (at 116.01196 107.10672)
+    (descr "SSOP, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/40001800C.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py")
+    (tags "SSOP SO")
+    (path /604F92C3)
+    (attr smd)
+    (fp_text reference U7 (at 0 -4.55) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 74LS244 (at 0 4.55) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 4.7 -3.85) (end -4.7 -3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 4.7 3.85) (end 4.7 -3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -4.7 3.85) (end 4.7 3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -4.7 -3.85) (end -4.7 3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.65 -2.6) (end -1.65 -3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start -2.65 3.6) (end -2.65 -2.6) (layer F.Fab) (width 0.1))
+    (fp_line (start 2.65 3.6) (end -2.65 3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start 2.65 -3.6) (end 2.65 3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.65 -3.6) (end 2.65 -3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start -2.76 -3.435) (end -4.45 -3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.76 -3.71) (end -2.76 -3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 -3.71) (end -2.76 -3.71) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.76 -3.71) (end 2.76 -3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 -3.71) (end 2.76 -3.71) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.76 3.71) (end -2.76 3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 3.71) (end -2.76 3.71) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.76 3.71) (end 2.76 3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 3.71) (end 2.76 3.71) (layer F.SilkS) (width 0.12))
+    (fp_text user %R (at 0 0) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 20 smd roundrect (at 3.5 -2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 5 +3V3))
+    (pad 19 smd roundrect (at 3.5 -2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 GND))
+    (pad 18 smd roundrect (at 3.5 -1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 12 CPU_WR_n))
+    (pad 17 smd roundrect (at 3.5 -0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 59 TEENSY_P2))
+    (pad 16 smd roundrect (at 3.5 -0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 60 "Net-(U7-Pad16)"))
+    (pad 15 smd roundrect (at 3.5 0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 61 TEENSY_P1))
+    (pad 14 smd roundrect (at 3.5 0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 62 "Net-(U7-Pad14)"))
+    (pad 13 smd roundrect (at 3.5 1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 63 TEENSY_P0))
+    (pad 12 smd roundrect (at 3.5 2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 64 "Net-(U7-Pad12)"))
+    (pad 11 smd roundrect (at 3.5 2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 6 CPU_CLKIN))
+    (pad 10 smd roundrect (at -3.5 2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 GND))
+    (pad 9 smd roundrect (at -3.5 2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 13 CPU_CLKOUT))
+    (pad 8 smd roundrect (at -3.5 1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 65 "Net-(U7-Pad8)"))
+    (pad 7 smd roundrect (at -3.5 0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 14 CPU_P0))
+    (pad 6 smd roundrect (at -3.5 0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 66 "Net-(U7-Pad6)"))
+    (pad 5 smd roundrect (at -3.5 -0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 15 CPU_P1))
+    (pad 4 smd roundrect (at -3.5 -0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 67 "Net-(U7-Pad4)"))
+    (pad 3 smd roundrect (at -3.5 -1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 16 CPU_P2))
+    (pad 2 smd roundrect (at -3.5 -2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 68 TEENSY_WR_n))
+    (pad 1 smd roundrect (at -3.5 -2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 49 CPU_AEC_n))
+    (model ${KISYS3DMOD}/Package_SO.3dshapes/SSOP-20_5.3x7.2mm_P0.65mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_SO:SSOP-14_5.3x6.2mm_P0.65mm (layer Top.Cu) (tedit 5A02F25C) (tstamp 604DA3B3)
+    (at 116.16436 91.87942)
+    (descr "SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot337-1_po.pdf)")
+    (tags "SSOP 0.65")
+    (path /604EF080)
+    (attr smd)
+    (fp_text reference U6 (at 0 -4.2) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 74LS04 (at 0 4.2) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start -2.775 -2.475) (end -4.05 -2.475) (layer F.SilkS) (width 0.15))
+    (fp_line (start -2.775 3.275) (end 2.775 3.275) (layer F.SilkS) (width 0.15))
+    (fp_line (start -2.775 -3.275) (end 2.775 -3.275) (layer F.SilkS) (width 0.15))
+    (fp_line (start -2.775 3.275) (end -2.775 2.375) (layer F.SilkS) (width 0.15))
+    (fp_line (start 2.775 3.275) (end 2.775 2.375) (layer F.SilkS) (width 0.15))
+    (fp_line (start 2.775 -3.275) (end 2.775 -2.375) (layer F.SilkS) (width 0.15))
+    (fp_line (start -2.775 -3.275) (end -2.775 -2.475) (layer F.SilkS) (width 0.15))
+    (fp_line (start -4.3 3.45) (end 4.3 3.45) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -4.3 -3.45) (end 4.3 -3.45) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 4.3 -3.45) (end 4.3 3.45) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -4.3 -3.45) (end -4.3 3.45) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.65 -2.1) (end -1.65 -3.1) (layer F.Fab) (width 0.15))
+    (fp_line (start -2.65 3.1) (end -2.65 -2.1) (layer F.Fab) (width 0.15))
+    (fp_line (start 2.65 3.1) (end -2.65 3.1) (layer F.Fab) (width 0.15))
+    (fp_line (start 2.65 -3.1) (end 2.65 3.1) (layer F.Fab) (width 0.15))
+    (fp_line (start -1.65 -3.1) (end 2.65 -3.1) (layer F.Fab) (width 0.15))
+    (fp_text user %R (at 0 0) (layer F.Fab)
+      (effects (font (size 0.8 0.8) (thickness 0.15)))
+    )
+    (pad 14 smd rect (at 3.45 -1.95) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 5 +3V3))
+    (pad 13 smd rect (at 3.45 -1.3) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 6 CPU_CLKIN))
+    (pad 12 smd rect (at 3.45 -0.65) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 58 TEENSY_CLKIN))
+    (pad 11 smd rect (at 3.45 0) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 7 CPU_RST_n))
+    (pad 10 smd rect (at 3.45 0.65) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 87 TEENSY_RST))
+    (pad 9 smd rect (at 3.45 1.3) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 8 CPU_NMI_n))
+    (pad 8 smd rect (at 3.45 1.95) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 86 TEENSY_NMI))
+    (pad 7 smd rect (at -3.45 1.95) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 4 GND))
+    (pad 6 smd rect (at -3.45 1.3) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 89 TEENSY_IRQ))
+    (pad 5 smd rect (at -3.45 0.65) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 9 CPU_IRQ_n))
+    (pad 4 smd rect (at -3.45 0) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 88 TEENSY_READY_n))
+    (pad 3 smd rect (at -3.45 -0.65) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 10 CPU_READY))
+    (pad 2 smd rect (at -3.45 -1.3) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 49 CPU_AEC_n))
+    (pad 1 smd rect (at -3.45 -1.95) (size 1.2 0.4) (layers Top.Cu F.Paste F.Mask)
+      (net 11 CPU_AEC))
+    (model ${KISYS3DMOD}/Package_SO.3dshapes/SSOP-14_5.3x6.2mm_P0.65mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_SO:SSOP-20_5.3x7.2mm_P0.65mm (layer Top.Cu) (tedit 5D9F72B1) (tstamp 604DAB21)
+    (at 97.74174 120.85828)
+    (descr "SSOP, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/40001800C.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py")
+    (tags "SSOP SO")
+    (path /605FE39B)
+    (attr smd)
+    (fp_text reference U5 (at 0 -4.55) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 74LS573 (at 0 4.55) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 4.7 -3.85) (end -4.7 -3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 4.7 3.85) (end 4.7 -3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -4.7 3.85) (end 4.7 3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -4.7 -3.85) (end -4.7 3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.65 -2.6) (end -1.65 -3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start -2.65 3.6) (end -2.65 -2.6) (layer F.Fab) (width 0.1))
+    (fp_line (start 2.65 3.6) (end -2.65 3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start 2.65 -3.6) (end 2.65 3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.65 -3.6) (end 2.65 -3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start -2.76 -3.435) (end -4.45 -3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.76 -3.71) (end -2.76 -3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 -3.71) (end -2.76 -3.71) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.76 -3.71) (end 2.76 -3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 -3.71) (end 2.76 -3.71) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.76 3.71) (end -2.76 3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 3.71) (end -2.76 3.71) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.76 3.71) (end 2.76 3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 3.71) (end 2.76 3.71) (layer F.SilkS) (width 0.12))
+    (fp_text user %R (at 0 0) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 20 smd roundrect (at 3.5 -2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 5 +3V3))
+    (pad 19 smd roundrect (at 3.5 -2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 20 CPU_D0))
+    (pad 18 smd roundrect (at 3.5 -1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 22 CPU_D1))
+    (pad 17 smd roundrect (at 3.5 -0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 24 CPU_D2))
+    (pad 16 smd roundrect (at 3.5 -0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 26 CPU_D3))
+    (pad 15 smd roundrect (at 3.5 0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 28 CPU_D4))
+    (pad 14 smd roundrect (at 3.5 0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 30 CPU_D5))
+    (pad 13 smd roundrect (at 3.5 1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 32 CPU_D6))
+    (pad 12 smd roundrect (at 3.5 2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 34 CPU_D7))
+    (pad 11 smd roundrect (at 3.5 2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 5 +3V3))
+    (pad 10 smd roundrect (at -3.5 2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 GND))
+    (pad 9 smd roundrect (at -3.5 2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 77 TEENSY_OUT_D7))
+    (pad 8 smd roundrect (at -3.5 1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 78 TEENSY_OUT_D6))
+    (pad 7 smd roundrect (at -3.5 0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 79 TEENSY_OUT_D5))
+    (pad 6 smd roundrect (at -3.5 0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 80 TEENSY_OUT_D4))
+    (pad 5 smd roundrect (at -3.5 -0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 81 TEENSY_OUT_D3))
+    (pad 4 smd roundrect (at -3.5 -0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 82 TEENSY_OUT_D2))
+    (pad 3 smd roundrect (at -3.5 -1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 83 TEENSY_OUT_D1))
+    (pad 2 smd roundrect (at -3.5 -2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 84 TEENSY_OUT_D0))
+    (pad 1 smd roundrect (at -3.5 -2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 85 TEENSY_DATA_OE_n))
+    (model ${KISYS3DMOD}/Package_SO.3dshapes/SSOP-20_5.3x7.2mm_P0.65mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_SO:SSOP-20_5.3x7.2mm_P0.65mm (layer Bottom.Cu) (tedit 5D9F72B1) (tstamp 604DAAF6)
+    (at 97.77476 120.82526 180)
+    (descr "SSOP, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/40001800C.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py")
+    (tags "SSOP SO")
+    (path /6058D2B5)
+    (attr smd)
+    (fp_text reference U4 (at 0 4.55) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 74LS573 (at 0 -4.55) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start 4.7 3.85) (end -4.7 3.85) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 4.7 -3.85) (end 4.7 3.85) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -4.7 -3.85) (end 4.7 -3.85) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -4.7 3.85) (end -4.7 -3.85) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -2.65 2.6) (end -1.65 3.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -2.65 -3.6) (end -2.65 2.6) (layer B.Fab) (width 0.1))
+    (fp_line (start 2.65 -3.6) (end -2.65 -3.6) (layer B.Fab) (width 0.1))
+    (fp_line (start 2.65 3.6) (end 2.65 -3.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -1.65 3.6) (end 2.65 3.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -2.76 3.435) (end -4.45 3.435) (layer B.SilkS) (width 0.12))
+    (fp_line (start -2.76 3.71) (end -2.76 3.435) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 3.71) (end -2.76 3.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start 2.76 3.71) (end 2.76 3.435) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 3.71) (end 2.76 3.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start -2.76 -3.71) (end -2.76 -3.435) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 -3.71) (end -2.76 -3.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start 2.76 -3.71) (end 2.76 -3.435) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 -3.71) (end 2.76 -3.71) (layer B.SilkS) (width 0.12))
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (pad 20 smd roundrect (at 3.5 2.925 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 5 +3V3))
+    (pad 19 smd roundrect (at 3.5 2.275 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 69 TEENSY_IN_D0))
+    (pad 18 smd roundrect (at 3.5 1.625 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 70 TEENSY_IN_D1))
+    (pad 17 smd roundrect (at 3.5 0.975 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 71 TEENSY_IN_D2))
+    (pad 16 smd roundrect (at 3.5 0.325 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 72 TEENSY_IN_D3))
+    (pad 15 smd roundrect (at 3.5 -0.325 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 73 TEENSY_IN_D4))
+    (pad 14 smd roundrect (at 3.5 -0.975 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 74 TEENSY_IN_D5))
+    (pad 13 smd roundrect (at 3.5 -1.625 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 75 TEENSY_IN_D6))
+    (pad 12 smd roundrect (at 3.5 -2.275 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 76 TEENSY_IN_D7))
+    (pad 11 smd roundrect (at 3.5 -2.925 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 6 CPU_CLKIN))
+    (pad 10 smd roundrect (at -3.5 -2.925 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 GND))
+    (pad 9 smd roundrect (at -3.5 -2.275 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 34 CPU_D7))
+    (pad 8 smd roundrect (at -3.5 -1.625 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 32 CPU_D6))
+    (pad 7 smd roundrect (at -3.5 -0.975 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 30 CPU_D5))
+    (pad 6 smd roundrect (at -3.5 -0.325 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 28 CPU_D4))
+    (pad 5 smd roundrect (at -3.5 0.325 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 26 CPU_D3))
+    (pad 4 smd roundrect (at -3.5 0.975 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 24 CPU_D2))
+    (pad 3 smd roundrect (at -3.5 1.625 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 22 CPU_D1))
+    (pad 2 smd roundrect (at -3.5 2.275 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 20 CPU_D0))
+    (pad 1 smd roundrect (at -3.5 2.925 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 GND))
+    (model ${KISYS3DMOD}/Package_SO.3dshapes/SSOP-20_5.3x7.2mm_P0.65mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_SO:SSOP-20_5.3x7.2mm_P0.65mm (layer Bottom.Cu) (tedit 5D9F72B1) (tstamp 604DA393)
+    (at 116.21516 126.2126 180)
+    (descr "SSOP, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/40001800C.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py")
+    (tags "SSOP SO")
+    (path /605D8A68)
+    (attr smd)
+    (fp_text reference U3 (at 0 4.55) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 74LS573 (at 0 -4.55) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start 4.7 3.85) (end -4.7 3.85) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 4.7 -3.85) (end 4.7 3.85) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -4.7 -3.85) (end 4.7 -3.85) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -4.7 3.85) (end -4.7 -3.85) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -2.65 2.6) (end -1.65 3.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -2.65 -3.6) (end -2.65 2.6) (layer B.Fab) (width 0.1))
+    (fp_line (start 2.65 -3.6) (end -2.65 -3.6) (layer B.Fab) (width 0.1))
+    (fp_line (start 2.65 3.6) (end 2.65 -3.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -1.65 3.6) (end 2.65 3.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -2.76 3.435) (end -4.45 3.435) (layer B.SilkS) (width 0.12))
+    (fp_line (start -2.76 3.71) (end -2.76 3.435) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 3.71) (end -2.76 3.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start 2.76 3.71) (end 2.76 3.435) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 3.71) (end 2.76 3.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start -2.76 -3.71) (end -2.76 -3.435) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 -3.71) (end -2.76 -3.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start 2.76 -3.71) (end 2.76 -3.435) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 -3.71) (end 2.76 -3.71) (layer B.SilkS) (width 0.12))
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (pad 20 smd roundrect (at 3.5 2.925 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 5 +3V3))
+    (pad 19 smd roundrect (at 3.5 2.275 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 25 CPU_A8))
+    (pad 18 smd roundrect (at 3.5 1.625 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 23 CPU_A9))
+    (pad 17 smd roundrect (at 3.5 0.975 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 21 CPU_A10))
+    (pad 16 smd roundrect (at 3.5 0.325 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 19 CPU_A11))
+    (pad 15 smd roundrect (at 3.5 -0.325 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 18 CPU_A12))
+    (pad 14 smd roundrect (at 3.5 -0.975 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 17 CPU_A13))
+    (pad 13 smd roundrect (at 3.5 -1.625 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 40 CPU_A14))
+    (pad 12 smd roundrect (at 3.5 -2.275 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 39 CPU_A15))
+    (pad 11 smd roundrect (at 3.5 -2.925 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 5 +3V3))
+    (pad 10 smd roundrect (at -3.5 -2.925 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 GND))
+    (pad 9 smd roundrect (at -3.5 -2.275 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 50 TEENSY_A15))
+    (pad 8 smd roundrect (at -3.5 -1.625 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 51 TEENSY_A14))
+    (pad 7 smd roundrect (at -3.5 -0.975 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 52 TEENSY_A13))
+    (pad 6 smd roundrect (at -3.5 -0.325 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 53 TEENSY_A12))
+    (pad 5 smd roundrect (at -3.5 0.325 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 54 TEENSY_A11))
+    (pad 4 smd roundrect (at -3.5 0.975 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 55 TEENSY_A10))
+    (pad 3 smd roundrect (at -3.5 1.625 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 56 TEENSY_A9))
+    (pad 2 smd roundrect (at -3.5 2.275 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 57 TEENSY_A8))
+    (pad 1 smd roundrect (at -3.5 2.925 180) (size 1.9 0.5) (layers Bottom.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 49 CPU_AEC_n))
+    (model ${KISYS3DMOD}/Package_SO.3dshapes/SSOP-20_5.3x7.2mm_P0.65mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_SO:SSOP-20_5.3x7.2mm_P0.65mm (layer Top.Cu) (tedit 5D9F72B1) (tstamp 604DA368)
+    (at 97.33534 107.00258)
+    (descr "SSOP, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/40001800C.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py")
+    (tags "SSOP SO")
+    (path /605A5248)
+    (attr smd)
+    (fp_text reference U2 (at 0 -4.55) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 74LS573 (at 0 4.55) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 4.7 -3.85) (end -4.7 -3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 4.7 3.85) (end 4.7 -3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -4.7 3.85) (end 4.7 3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -4.7 -3.85) (end -4.7 3.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.65 -2.6) (end -1.65 -3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start -2.65 3.6) (end -2.65 -2.6) (layer F.Fab) (width 0.1))
+    (fp_line (start 2.65 3.6) (end -2.65 3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start 2.65 -3.6) (end 2.65 3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.65 -3.6) (end 2.65 -3.6) (layer F.Fab) (width 0.1))
+    (fp_line (start -2.76 -3.435) (end -4.45 -3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.76 -3.71) (end -2.76 -3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 -3.71) (end -2.76 -3.71) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.76 -3.71) (end 2.76 -3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 -3.71) (end 2.76 -3.71) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.76 3.71) (end -2.76 3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 3.71) (end -2.76 3.71) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.76 3.71) (end 2.76 3.435) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 3.71) (end 2.76 3.71) (layer F.SilkS) (width 0.12))
+    (fp_text user %R (at 0 0) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 20 smd roundrect (at 3.5 -2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 5 +3V3))
+    (pad 19 smd roundrect (at 3.5 -2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 38 CPU_A0))
+    (pad 18 smd roundrect (at 3.5 -1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 37 CPU_A1))
+    (pad 17 smd roundrect (at 3.5 -0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 36 CPU_A2))
+    (pad 16 smd roundrect (at 3.5 -0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 35 CPU_A3))
+    (pad 15 smd roundrect (at 3.5 0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 33 CPU_A4))
+    (pad 14 smd roundrect (at 3.5 0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 31 CPU_A5))
+    (pad 13 smd roundrect (at 3.5 1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 29 CPU_A6))
+    (pad 12 smd roundrect (at 3.5 2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 27 CPU_A7))
+    (pad 11 smd roundrect (at 3.5 2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 5 +3V3))
+    (pad 10 smd roundrect (at -3.5 2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 GND))
+    (pad 9 smd roundrect (at -3.5 2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 41 TEENSY_A7))
+    (pad 8 smd roundrect (at -3.5 1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 42 TEENSY_A6))
+    (pad 7 smd roundrect (at -3.5 0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 43 TEENSY_A5))
+    (pad 6 smd roundrect (at -3.5 0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 44 TEENSY_A4))
+    (pad 5 smd roundrect (at -3.5 -0.325) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 45 TEENSY_A3))
+    (pad 4 smd roundrect (at -3.5 -0.975) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 46 TEENSY_A2))
+    (pad 3 smd roundrect (at -3.5 -1.625) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 47 TEENSY_A1))
+    (pad 2 smd roundrect (at -3.5 -2.275) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 48 TEENSY_A0))
+    (pad 1 smd roundrect (at -3.5 -2.925) (size 1.9 0.5) (layers Top.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 49 CPU_AEC_n))
+    (model ${KISYS3DMOD}/Package_SO.3dshapes/SSOP-20_5.3x7.2mm_P0.65mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_DIP:DIP-40_W15.24mm (layer Top.Cu) (tedit 5A02E8C5) (tstamp 604C633D)
+    (at 108.63326 84.2264)
+    (descr "40-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils)")
+    (tags "THT DIP DIL PDIP 2.54mm 15.24mm 600mil")
+    (path /604E276C)
+    (fp_text reference U8 (at 7.62 -2.33) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 6510 (at 7.62 50.59) (layer F.Fab) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 1.255 -1.27) (end 14.985 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 14.985 -1.27) (end 14.985 49.53) (layer F.Fab) (width 0.1))
+    (fp_line (start 14.985 49.53) (end 0.255 49.53) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.255 49.53) (end 0.255 -0.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.255 -0.27) (end 1.255 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 6.62 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.16 -1.33) (end 1.16 49.59) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.16 49.59) (end 14.08 49.59) (layer F.SilkS) (width 0.12))
+    (fp_line (start 14.08 49.59) (end 14.08 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start 14.08 -1.33) (end 8.62 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.05 -1.55) (end -1.05 49.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.05 49.8) (end 16.3 49.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 16.3 49.8) (end 16.3 -1.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 16.3 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 7.62 24.13) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_arc (start 7.62 -1.33) (end 6.62 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
+    (pad 40 thru_hole oval (at 15.24 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 7 CPU_RST_n))
+    (pad 20 thru_hole oval (at 0 48.26) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 17 CPU_A13))
+    (pad 39 thru_hole oval (at 15.24 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 13 CPU_CLKOUT))
+    (pad 19 thru_hole oval (at 0 45.72) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 18 CPU_A12))
+    (pad 38 thru_hole oval (at 15.24 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 12 CPU_WR_n))
+    (pad 18 thru_hole oval (at 0 43.18) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 19 CPU_A11))
+    (pad 37 thru_hole oval (at 15.24 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 20 CPU_D0))
+    (pad 17 thru_hole oval (at 0 40.64) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 21 CPU_A10))
+    (pad 36 thru_hole oval (at 15.24 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 22 CPU_D1))
+    (pad 16 thru_hole oval (at 0 38.1) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 23 CPU_A9))
+    (pad 35 thru_hole oval (at 15.24 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 24 CPU_D2))
+    (pad 15 thru_hole oval (at 0 35.56) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 25 CPU_A8))
+    (pad 34 thru_hole oval (at 15.24 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 26 CPU_D3))
+    (pad 14 thru_hole oval (at 0 33.02) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 27 CPU_A7))
+    (pad 33 thru_hole oval (at 15.24 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 28 CPU_D4))
+    (pad 13 thru_hole oval (at 0 30.48) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 29 CPU_A6))
+    (pad 32 thru_hole oval (at 15.24 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 30 CPU_D5))
+    (pad 12 thru_hole oval (at 0 27.94) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 31 CPU_A5))
+    (pad 31 thru_hole oval (at 15.24 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 32 CPU_D6))
+    (pad 11 thru_hole oval (at 0 25.4) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 33 CPU_A4))
+    (pad 30 thru_hole oval (at 15.24 25.4) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 34 CPU_D7))
+    (pad 10 thru_hole oval (at 0 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 35 CPU_A3))
+    (pad 29 thru_hole oval (at 15.24 27.94) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 14 CPU_P0))
+    (pad 9 thru_hole oval (at 0 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 36 CPU_A2))
+    (pad 28 thru_hole oval (at 15.24 30.48) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 15 CPU_P1))
+    (pad 8 thru_hole oval (at 0 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 37 CPU_A1))
+    (pad 27 thru_hole oval (at 15.24 33.02) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 16 CPU_P2))
+    (pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 38 CPU_A0))
+    (pad 26 thru_hole oval (at 15.24 35.56) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 1 "Net-(U8-Pad26)"))
+    (pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 3 +5V))
+    (pad 25 thru_hole oval (at 15.24 38.1) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 2 "Net-(U8-Pad25)"))
+    (pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 11 CPU_AEC))
+    (pad 24 thru_hole oval (at 15.24 40.64) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 4 GND))
+    (pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 8 CPU_NMI_n))
+    (pad 23 thru_hole oval (at 15.24 43.18) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 39 CPU_A15))
+    (pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 9 CPU_IRQ_n))
+    (pad 22 thru_hole oval (at 15.24 45.72) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 40 CPU_A14))
+    (pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 10 CPU_READY))
+    (pad 21 thru_hole oval (at 15.24 48.26) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 4 GND))
+    (pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 6 CPU_CLKIN))
+  )
+
+  (gr_text "MicroCore Labs\n MCL64" (at 116.30406 141.17574) (layer F.SilkS)
+    (effects (font (size 1 1) (thickness 0.15)))
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+)
diff --git a/MCL64/PCB/MCL64/MCL64.net b/MCL64/PCB/MCL64/MCL64.net
new file mode 100644
index 0000000..b8ed541
--- /dev/null
+++ b/MCL64/PCB/MCL64/MCL64.net
@@ -0,0 +1,648 @@
+(export (version D)
+  (design
+    (source F:\Latest_1_9_2021\MCL64\MCL64_PCB\MCL64\MCL64.sch)
+    (date "3/12/2021 10:20:31 PM")
+    (tool "Eeschema (5.1.8)-1")
+    (sheet (number 1) (name /) (tstamps /)
+      (title_block
+        (title)
+        (company)
+        (rev)
+        (date)
+        (source MCL64.sch)
+        (comment (number 1) (value ""))
+        (comment (number 2) (value ""))
+        (comment (number 3) (value ""))
+        (comment (number 4) (value "")))))
+  (components
+    (comp (ref U8)
+      (value 74LS04)
+      (footprint Package_DIP:DIP-40_W15.24mm)
+      (datasheet http://www.ti.com/lit/gpn/sn74LS04)
+      (libsource (lib 65xx) (part 6510) (description "6510 8-bit NMOS Microprocessor, 64K, 6-bit I/O Port, DIP-40"))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 604E276C))
+    (comp (ref U1)
+      (value 74LS04)
+      (datasheet http://www.ti.com/lit/gpn/sn74LS04)
+      (libsource (lib teensy) (part Teensy4.1) (description ""))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 604E31A7))
+    (comp (ref U6)
+      (value 74LS04)
+      (footprint Package_SO:SOIC-14_3.9x8.7mm_P1.27mm)
+      (datasheet http://www.ti.com/lit/gpn/sn74LS04)
+      (libsource (lib 74xx) (part 74LS04) (description "Hex Inverter"))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 604EF080))
+    (comp (ref U2)
+      (value 74LS244)
+      (footprint Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm)
+      (datasheet http://www.ti.com/lit/ds/symlink/sn74ls244.pdf)
+      (libsource (lib 74xx) (part 74LS244) (description "Octal Buffer and Line Driver With 3-State Output, active-low enables, non-inverting outputs"))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 604F3E3F))
+    (comp (ref U3)
+      (value 74LS244)
+      (footprint Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm)
+      (datasheet http://www.ti.com/lit/ds/symlink/sn74ls244.pdf)
+      (libsource (lib 74xx) (part 74LS244) (description "Octal Buffer and Line Driver With 3-State Output, active-low enables, non-inverting outputs"))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 604F5709))
+    (comp (ref U4)
+      (value 74LS244)
+      (footprint Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm)
+      (datasheet http://www.ti.com/lit/ds/symlink/sn74ls244.pdf)
+      (libsource (lib 74xx) (part 74LS244) (description "Octal Buffer and Line Driver With 3-State Output, active-low enables, non-inverting outputs"))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 604F64D5))
+    (comp (ref U5)
+      (value 74LS244)
+      (footprint Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm)
+      (datasheet http://www.ti.com/lit/ds/symlink/sn74ls244.pdf)
+      (libsource (lib 74xx) (part 74LS244) (description "Octal Buffer and Line Driver With 3-State Output, active-low enables, non-inverting outputs"))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 604F64DB))
+    (comp (ref U7)
+      (value 74LS244)
+      (footprint Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm)
+      (datasheet http://www.ti.com/lit/ds/symlink/sn74ls244.pdf)
+      (libsource (lib 74xx) (part 74LS244) (description "Octal Buffer and Line Driver With 3-State Output, active-low enables, non-inverting outputs"))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 604F92C3)))
+  (libparts
+    (libpart (lib 65xx) (part 6510)
+      (aliases
+        (alias 8500))
+      (description "6510 8-bit NMOS Microprocessor, 64K, 6-bit I/O Port, DIP-40")
+      (docs http://www.6502.org/documents/datasheets/mos/mos_6510_mpu.pdf)
+      (footprints
+        (fp DIP-40_W15.24mm*))
+      (fields
+        (field (name Reference) U)
+        (field (name Value) 6510))
+      (pins
+        (pin (num 1) (name ϕ0) (type input))
+        (pin (num 2) (name RDY) (type input))
+        (pin (num 3) (name ~IRQ) (type input))
+        (pin (num 4) (name ~NMI) (type input))
+        (pin (num 5) (name AEC) (type input))
+        (pin (num 6) (name VCC) (type power_in))
+        (pin (num 7) (name A0) (type 3state))
+        (pin (num 8) (name A1) (type 3state))
+        (pin (num 9) (name A2) (type 3state))
+        (pin (num 10) (name A3) (type 3state))
+        (pin (num 11) (name A4) (type 3state))
+        (pin (num 12) (name A5) (type 3state))
+        (pin (num 13) (name A6) (type 3state))
+        (pin (num 14) (name A7) (type 3state))
+        (pin (num 15) (name A8) (type 3state))
+        (pin (num 16) (name A9) (type 3state))
+        (pin (num 17) (name A10) (type 3state))
+        (pin (num 18) (name A11) (type 3state))
+        (pin (num 19) (name A12) (type 3state))
+        (pin (num 20) (name A13) (type 3state))
+        (pin (num 21) (name VSS) (type power_in))
+        (pin (num 22) (name A14) (type 3state))
+        (pin (num 23) (name A15) (type 3state))
+        (pin (num 24) (name P5) (type BiDi))
+        (pin (num 25) (name P4) (type BiDi))
+        (pin (num 26) (name P3) (type BiDi))
+        (pin (num 27) (name P2) (type BiDi))
+        (pin (num 28) (name P1) (type BiDi))
+        (pin (num 29) (name P0) (type BiDi))
+        (pin (num 30) (name D7) (type BiDi))
+        (pin (num 31) (name D6) (type BiDi))
+        (pin (num 32) (name D5) (type BiDi))
+        (pin (num 33) (name D4) (type BiDi))
+        (pin (num 34) (name D3) (type BiDi))
+        (pin (num 35) (name D2) (type BiDi))
+        (pin (num 36) (name D1) (type BiDi))
+        (pin (num 37) (name D0) (type BiDi))
+        (pin (num 38) (name R/~W) (type 3state))
+        (pin (num 39) (name ϕ2) (type output))
+        (pin (num 40) (name ~RES) (type input))))
+    (libpart (lib 74xx) (part 74LS04)
+      (aliases
+        (alias 74HC04)
+        (alias 74HCT04)
+        (alias 74AHC04)
+        (alias 74AHCT04))
+      (description "Hex Inverter")
+      (docs http://www.ti.com/lit/gpn/sn74LS04)
+      (footprints
+        (fp DIP*W7.62mm*)
+        (fp SSOP?14*)
+        (fp TSSOP?14*))
+      (fields
+        (field (name Reference) U)
+        (field (name Value) 74LS04))
+      (pins
+        (pin (num 1) (name ~) (type input))
+        (pin (num 2) (name ~) (type output))
+        (pin (num 3) (name ~) (type input))
+        (pin (num 4) (name ~) (type output))
+        (pin (num 5) (name ~) (type input))
+        (pin (num 6) (name ~) (type output))
+        (pin (num 7) (name GND) (type power_in))
+        (pin (num 8) (name ~) (type output))
+        (pin (num 9) (name ~) (type input))
+        (pin (num 10) (name ~) (type output))
+        (pin (num 11) (name ~) (type input))
+        (pin (num 12) (name ~) (type output))
+        (pin (num 13) (name ~) (type input))
+        (pin (num 14) (name VCC) (type power_in))))
+    (libpart (lib 74xx) (part 74LS244)
+      (description "Octal Buffer and Line Driver With 3-State Output, active-low enables, non-inverting outputs")
+      (docs http://www.ti.com/lit/ds/symlink/sn74ls244.pdf)
+      (footprints
+        (fp DIP?20*))
+      (fields
+        (field (name Reference) U)
+        (field (name Value) 74LS244))
+      (pins
+        (pin (num 1) (name OEa) (type input))
+        (pin (num 2) (name I0a) (type input))
+        (pin (num 3) (name O3b) (type 3state))
+        (pin (num 4) (name I1a) (type input))
+        (pin (num 5) (name O2b) (type 3state))
+        (pin (num 6) (name I2a) (type input))
+        (pin (num 7) (name O1b) (type 3state))
+        (pin (num 8) (name I3a) (type input))
+        (pin (num 9) (name O0b) (type 3state))
+        (pin (num 10) (name GND) (type power_in))
+        (pin (num 11) (name I0b) (type input))
+        (pin (num 12) (name O3a) (type 3state))
+        (pin (num 13) (name I1b) (type input))
+        (pin (num 14) (name O2a) (type 3state))
+        (pin (num 15) (name I2b) (type input))
+        (pin (num 16) (name O1a) (type 3state))
+        (pin (num 17) (name I3b) (type input))
+        (pin (num 18) (name O0a) (type 3state))
+        (pin (num 19) (name OEb) (type input))
+        (pin (num 20) (name VCC) (type power_in))))
+    (libpart (lib teensy) (part Teensy4.1)
+      (fields
+        (field (name Reference) U)
+        (field (name Value) Teensy4.1))
+      (pins
+        (pin (num 1) (name GND) (type power_in))
+        (pin (num 2) (name 0_RX1_CRX2_CS1) (type BiDi))
+        (pin (num 3) (name 1_TX1_CTX2_MISO1) (type BiDi))
+        (pin (num 4) (name 2_OUT2) (type BiDi))
+        (pin (num 5) (name 3_LRCLK2) (type BiDi))
+        (pin (num 6) (name 4_BCLK2) (type BiDi))
+        (pin (num 7) (name 5_IN2) (type BiDi))
+        (pin (num 8) (name 6_OUT1D) (type BiDi))
+        (pin (num 9) (name 7_RX2_OUT1A) (type BiDi))
+        (pin (num 10) (name 8_TX2_IN1) (type BiDi))
+        (pin (num 11) (name 9_OUT1C) (type BiDi))
+        (pin (num 12) (name 10_CS_MQSR) (type BiDi))
+        (pin (num 13) (name 11_MOSI_CTX1) (type BiDi))
+        (pin (num 14) (name 12_MISO_MQSL) (type BiDi))
+        (pin (num 15) (name 3V3) (type power_in))
+        (pin (num 16) (name 24_A10_TX6_SCL2) (type BiDi))
+        (pin (num 17) (name 25_A11_RX6_SDA2) (type BiDi))
+        (pin (num 18) (name 26_A12_MOSI1) (type BiDi))
+        (pin (num 19) (name 27_A13_SCK1) (type BiDi))
+        (pin (num 20) (name 28_RX7) (type BiDi))
+        (pin (num 21) (name 29_TX7) (type BiDi))
+        (pin (num 22) (name 30_CRX3) (type BiDi))
+        (pin (num 23) (name 31_CTX3) (type BiDi))
+        (pin (num 24) (name 32_OUT1B) (type BiDi))
+        (pin (num 25) (name 33_MCLK2) (type BiDi))
+        (pin (num 26) (name 34_RX8) (type BiDi))
+        (pin (num 27) (name 35_TX8) (type BiDi))
+        (pin (num 28) (name 36_CS) (type BiDi))
+        (pin (num 29) (name 37_CS) (type BiDi))
+        (pin (num 30) (name 38_CS1_IN1) (type BiDi))
+        (pin (num 31) (name 39_MISO1_OUT1A) (type BiDi))
+        (pin (num 32) (name 40_A16) (type BiDi))
+        (pin (num 33) (name 41_A17) (type BiDi))
+        (pin (num 34) (name GND) (type power_in))
+        (pin (num 35) (name 13_SCK_LED) (type BiDi))
+        (pin (num 36) (name 14_A0_TX3_SPDIF_OUT) (type BiDi))
+        (pin (num 37) (name 15_A1_RX3_SPDIF_IN) (type BiDi))
+        (pin (num 38) (name 16_A2_RX4_SCL1) (type BiDi))
+        (pin (num 39) (name 17_A3_TX4_SDA1) (type BiDi))
+        (pin (num 40) (name 18_A4_SDA) (type BiDi))
+        (pin (num 41) (name 19_A5_SCL) (type BiDi))
+        (pin (num 42) (name 20_A6_TX5_LRCLK1) (type BiDi))
+        (pin (num 43) (name 21_A7_RX5_BCLK1) (type BiDi))
+        (pin (num 44) (name 22_A8_CTX1) (type BiDi))
+        (pin (num 45) (name 23_A9_CRX1_MCLK1) (type BiDi))
+        (pin (num 46) (name 3V3) (type output))
+        (pin (num 47) (name GND) (type output))
+        (pin (num 48) (name VIN) (type power_in)))))
+  (libraries
+    (library (logical 65xx)
+      (uri F:/Latest_1_9_2021/MCL64/MCL64_PCB/65xx.lib))
+    (library (logical 74xx)
+      (uri "C:\\Program Files\\KiCad\\share\\kicad\\library/74xx.lib"))
+    (library (logical teensy)
+      (uri Z:/Ted/projs/KiCAD_Library/Teensy/teensy.lib)))
+  (nets
+    (net (code 1) (name "Net-(U3-Pad7)")
+      (node (ref U3) (pin 7)))
+    (net (code 2) (name "Net-(U3-Pad14)")
+      (node (ref U3) (pin 14)))
+    (net (code 3) (name "Net-(U3-Pad15)")
+      (node (ref U3) (pin 15)))
+    (net (code 4) (name "Net-(U3-Pad16)")
+      (node (ref U3) (pin 16)))
+    (net (code 5) (name "Net-(U3-Pad17)")
+      (node (ref U3) (pin 17)))
+    (net (code 6) (name "Net-(U3-Pad18)")
+      (node (ref U3) (pin 18)))
+    (net (code 7) (name "Net-(U3-Pad19)")
+      (node (ref U3) (pin 19)))
+    (net (code 8) (name "Net-(U3-Pad2)")
+      (node (ref U3) (pin 2)))
+    (net (code 9) (name "Net-(U3-Pad20)")
+      (node (ref U3) (pin 20)))
+    (net (code 10) (name "Net-(U3-Pad3)")
+      (node (ref U3) (pin 3)))
+    (net (code 11) (name "Net-(U3-Pad4)")
+      (node (ref U3) (pin 4)))
+    (net (code 12) (name "Net-(U3-Pad5)")
+      (node (ref U3) (pin 5)))
+    (net (code 13) (name "Net-(U3-Pad6)")
+      (node (ref U3) (pin 6)))
+    (net (code 14) (name "Net-(U3-Pad13)")
+      (node (ref U3) (pin 13)))
+    (net (code 15) (name "Net-(U3-Pad8)")
+      (node (ref U3) (pin 8)))
+    (net (code 16) (name "Net-(U3-Pad9)")
+      (node (ref U3) (pin 9)))
+    (net (code 17) (name "Net-(U4-Pad1)")
+      (node (ref U4) (pin 1)))
+    (net (code 18) (name "Net-(U4-Pad10)")
+      (node (ref U4) (pin 10)))
+    (net (code 19) (name "Net-(U4-Pad11)")
+      (node (ref U4) (pin 11)))
+    (net (code 20) (name "Net-(U4-Pad12)")
+      (node (ref U4) (pin 12)))
+    (net (code 21) (name "Net-(U4-Pad13)")
+      (node (ref U4) (pin 13)))
+    (net (code 22) (name "Net-(U4-Pad14)")
+      (node (ref U4) (pin 14)))
+    (net (code 23) (name "Net-(U4-Pad15)")
+      (node (ref U4) (pin 15)))
+    (net (code 24) (name "Net-(U4-Pad16)")
+      (node (ref U4) (pin 16)))
+    (net (code 25) (name "Net-(U4-Pad17)")
+      (node (ref U4) (pin 17)))
+    (net (code 26) (name "Net-(U4-Pad18)")
+      (node (ref U4) (pin 18)))
+    (net (code 27) (name "Net-(U2-Pad20)")
+      (node (ref U2) (pin 20)))
+    (net (code 28) (name "Net-(U2-Pad1)")
+      (node (ref U2) (pin 1)))
+    (net (code 29) (name "Net-(U2-Pad10)")
+      (node (ref U2) (pin 10)))
+    (net (code 30) (name "Net-(U2-Pad11)")
+      (node (ref U2) (pin 11)))
+    (net (code 31) (name "Net-(U2-Pad12)")
+      (node (ref U2) (pin 12)))
+    (net (code 32) (name "Net-(U2-Pad13)")
+      (node (ref U2) (pin 13)))
+    (net (code 33) (name "Net-(U2-Pad14)")
+      (node (ref U2) (pin 14)))
+    (net (code 34) (name "Net-(U2-Pad15)")
+      (node (ref U2) (pin 15)))
+    (net (code 35) (name "Net-(U2-Pad16)")
+      (node (ref U2) (pin 16)))
+    (net (code 36) (name "Net-(U2-Pad17)")
+      (node (ref U2) (pin 17)))
+    (net (code 37) (name "Net-(U2-Pad18)")
+      (node (ref U2) (pin 18)))
+    (net (code 38) (name "Net-(U2-Pad19)")
+      (node (ref U2) (pin 19)))
+    (net (code 39) (name "Net-(U2-Pad2)")
+      (node (ref U2) (pin 2)))
+    (net (code 40) (name "Net-(U4-Pad19)")
+      (node (ref U4) (pin 19)))
+    (net (code 41) (name "Net-(U2-Pad3)")
+      (node (ref U2) (pin 3)))
+    (net (code 42) (name "Net-(U2-Pad4)")
+      (node (ref U2) (pin 4)))
+    (net (code 43) (name "Net-(U2-Pad5)")
+      (node (ref U2) (pin 5)))
+    (net (code 44) (name "Net-(U2-Pad6)")
+      (node (ref U2) (pin 6)))
+    (net (code 45) (name "Net-(U2-Pad7)")
+      (node (ref U2) (pin 7)))
+    (net (code 46) (name "Net-(U2-Pad8)")
+      (node (ref U2) (pin 8)))
+    (net (code 47) (name "Net-(U2-Pad9)")
+      (node (ref U2) (pin 9)))
+    (net (code 48) (name "Net-(U3-Pad1)")
+      (node (ref U3) (pin 1)))
+    (net (code 49) (name "Net-(U3-Pad10)")
+      (node (ref U3) (pin 10)))
+    (net (code 50) (name "Net-(U3-Pad11)")
+      (node (ref U3) (pin 11)))
+    (net (code 51) (name "Net-(U3-Pad12)")
+      (node (ref U3) (pin 12)))
+    (net (code 52) (name "Net-(U7-Pad17)")
+      (node (ref U7) (pin 17)))
+    (net (code 53) (name "Net-(U5-Pad6)")
+      (node (ref U5) (pin 6)))
+    (net (code 54) (name "Net-(U5-Pad7)")
+      (node (ref U5) (pin 7)))
+    (net (code 55) (name "Net-(U5-Pad8)")
+      (node (ref U5) (pin 8)))
+    (net (code 56) (name "Net-(U5-Pad9)")
+      (node (ref U5) (pin 9)))
+    (net (code 57) (name "Net-(U7-Pad1)")
+      (node (ref U7) (pin 1)))
+    (net (code 58) (name "Net-(U7-Pad10)")
+      (node (ref U7) (pin 10)))
+    (net (code 59) (name "Net-(U7-Pad11)")
+      (node (ref U7) (pin 11)))
+    (net (code 60) (name "Net-(U7-Pad12)")
+      (node (ref U7) (pin 12)))
+    (net (code 61) (name "Net-(U7-Pad13)")
+      (node (ref U7) (pin 13)))
+    (net (code 62) (name "Net-(U7-Pad14)")
+      (node (ref U7) (pin 14)))
+    (net (code 63) (name "Net-(U7-Pad15)")
+      (node (ref U7) (pin 15)))
+    (net (code 64) (name "Net-(U7-Pad16)")
+      (node (ref U7) (pin 16)))
+    (net (code 65) (name "Net-(U5-Pad5)")
+      (node (ref U5) (pin 5)))
+    (net (code 66) (name "Net-(U7-Pad18)")
+      (node (ref U7) (pin 18)))
+    (net (code 67) (name "Net-(U7-Pad19)")
+      (node (ref U7) (pin 19)))
+    (net (code 68) (name "Net-(U7-Pad2)")
+      (node (ref U7) (pin 2)))
+    (net (code 69) (name "Net-(U7-Pad20)")
+      (node (ref U7) (pin 20)))
+    (net (code 70) (name "Net-(U7-Pad3)")
+      (node (ref U7) (pin 3)))
+    (net (code 71) (name "Net-(U7-Pad4)")
+      (node (ref U7) (pin 4)))
+    (net (code 72) (name "Net-(U7-Pad5)")
+      (node (ref U7) (pin 5)))
+    (net (code 73) (name "Net-(U7-Pad6)")
+      (node (ref U7) (pin 6)))
+    (net (code 74) (name "Net-(U7-Pad7)")
+      (node (ref U7) (pin 7)))
+    (net (code 75) (name "Net-(U7-Pad8)")
+      (node (ref U7) (pin 8)))
+    (net (code 76) (name "Net-(U7-Pad9)")
+      (node (ref U7) (pin 9)))
+    (net (code 77) (name "Net-(U5-Pad12)")
+      (node (ref U5) (pin 12)))
+    (net (code 78) (name "Net-(U4-Pad2)")
+      (node (ref U4) (pin 2)))
+    (net (code 79) (name "Net-(U4-Pad20)")
+      (node (ref U4) (pin 20)))
+    (net (code 80) (name "Net-(U4-Pad3)")
+      (node (ref U4) (pin 3)))
+    (net (code 81) (name "Net-(U4-Pad4)")
+      (node (ref U4) (pin 4)))
+    (net (code 82) (name "Net-(U4-Pad5)")
+      (node (ref U4) (pin 5)))
+    (net (code 83) (name "Net-(U4-Pad6)")
+      (node (ref U4) (pin 6)))
+    (net (code 84) (name "Net-(U4-Pad7)")
+      (node (ref U4) (pin 7)))
+    (net (code 85) (name "Net-(U4-Pad8)")
+      (node (ref U4) (pin 8)))
+    (net (code 86) (name "Net-(U4-Pad9)")
+      (node (ref U4) (pin 9)))
+    (net (code 87) (name "Net-(U5-Pad1)")
+      (node (ref U5) (pin 1)))
+    (net (code 88) (name "Net-(U5-Pad10)")
+      (node (ref U5) (pin 10)))
+    (net (code 89) (name "Net-(U5-Pad11)")
+      (node (ref U5) (pin 11)))
+    (net (code 90) (name "Net-(U6-Pad7)")
+      (node (ref U6) (pin 7)))
+    (net (code 91) (name "Net-(U5-Pad13)")
+      (node (ref U5) (pin 13)))
+    (net (code 92) (name "Net-(U5-Pad14)")
+      (node (ref U5) (pin 14)))
+    (net (code 93) (name "Net-(U5-Pad15)")
+      (node (ref U5) (pin 15)))
+    (net (code 94) (name "Net-(U5-Pad16)")
+      (node (ref U5) (pin 16)))
+    (net (code 95) (name "Net-(U5-Pad17)")
+      (node (ref U5) (pin 17)))
+    (net (code 96) (name "Net-(U5-Pad18)")
+      (node (ref U5) (pin 18)))
+    (net (code 97) (name "Net-(U5-Pad19)")
+      (node (ref U5) (pin 19)))
+    (net (code 98) (name "Net-(U5-Pad2)")
+      (node (ref U5) (pin 2)))
+    (net (code 99) (name "Net-(U5-Pad20)")
+      (node (ref U5) (pin 20)))
+    (net (code 100) (name "Net-(U5-Pad3)")
+      (node (ref U5) (pin 3)))
+    (net (code 101) (name "Net-(U5-Pad4)")
+      (node (ref U5) (pin 4)))
+    (net (code 102) (name "Net-(U8-Pad8)")
+      (node (ref U8) (pin 8)))
+    (net (code 103) (name "Net-(U8-Pad33)")
+      (node (ref U8) (pin 33)))
+    (net (code 104) (name "Net-(U8-Pad34)")
+      (node (ref U8) (pin 34)))
+    (net (code 105) (name "Net-(U8-Pad35)")
+      (node (ref U8) (pin 35)))
+    (net (code 106) (name "Net-(U8-Pad36)")
+      (node (ref U8) (pin 36)))
+    (net (code 107) (name "Net-(U8-Pad37)")
+      (node (ref U8) (pin 37)))
+    (net (code 108) (name "Net-(U8-Pad38)")
+      (node (ref U8) (pin 38)))
+    (net (code 109) (name "Net-(U8-Pad39)")
+      (node (ref U8) (pin 39)))
+    (net (code 110) (name "Net-(U8-Pad4)")
+      (node (ref U8) (pin 4)))
+    (net (code 111) (name "Net-(U8-Pad40)")
+      (node (ref U8) (pin 40)))
+    (net (code 112) (name "Net-(U8-Pad5)")
+      (node (ref U8) (pin 5)))
+    (net (code 113) (name "Net-(U8-Pad6)")
+      (node (ref U8) (pin 6)))
+    (net (code 114) (name "Net-(U8-Pad7)")
+      (node (ref U8) (pin 7)))
+    (net (code 115) (name "Net-(U8-Pad32)")
+      (node (ref U8) (pin 32)))
+    (net (code 116) (name "Net-(U8-Pad9)")
+      (node (ref U8) (pin 9)))
+    (net (code 117) (name "Net-(U1-Pad10)")
+      (node (ref U1) (pin 10)))
+    (net (code 118) (name "Net-(U1-Pad11)")
+      (node (ref U1) (pin 11)))
+    (net (code 119) (name "Net-(U1-Pad12)")
+      (node (ref U1) (pin 12)))
+    (net (code 120) (name "Net-(U1-Pad13)")
+      (node (ref U1) (pin 13)))
+    (net (code 121) (name "Net-(U1-Pad14)")
+      (node (ref U1) (pin 14)))
+    (net (code 122) (name "Net-(U1-Pad15)")
+      (node (ref U1) (pin 15)))
+    (net (code 123) (name "Net-(U1-Pad16)")
+      (node (ref U1) (pin 16)))
+    (net (code 124) (name "Net-(U1-Pad17)")
+      (node (ref U1) (pin 17)))
+    (net (code 125) (name "Net-(U1-Pad18)")
+      (node (ref U1) (pin 18)))
+    (net (code 126) (name "Net-(U1-Pad19)")
+      (node (ref U1) (pin 19)))
+    (net (code 127) (name "Net-(U1-Pad20)")
+      (node (ref U1) (pin 20)))
+    (net (code 128) (name "Net-(U8-Pad21)")
+      (node (ref U8) (pin 21)))
+    (net (code 129) (name "Net-(U8-Pad10)")
+      (node (ref U8) (pin 10)))
+    (net (code 130) (name "Net-(U8-Pad11)")
+      (node (ref U8) (pin 11)))
+    (net (code 131) (name "Net-(U8-Pad12)")
+      (node (ref U8) (pin 12)))
+    (net (code 132) (name "Net-(U8-Pad13)")
+      (node (ref U8) (pin 13)))
+    (net (code 133) (name "Net-(U8-Pad14)")
+      (node (ref U8) (pin 14)))
+    (net (code 134) (name "Net-(U8-Pad15)")
+      (node (ref U8) (pin 15)))
+    (net (code 135) (name "Net-(U8-Pad16)")
+      (node (ref U8) (pin 16)))
+    (net (code 136) (name "Net-(U8-Pad17)")
+      (node (ref U8) (pin 17)))
+    (net (code 137) (name "Net-(U8-Pad18)")
+      (node (ref U8) (pin 18)))
+    (net (code 138) (name "Net-(U8-Pad19)")
+      (node (ref U8) (pin 19)))
+    (net (code 139) (name "Net-(U8-Pad2)")
+      (node (ref U8) (pin 2)))
+    (net (code 140) (name "Net-(U8-Pad20)")
+      (node (ref U8) (pin 20)))
+    (net (code 141) (name "Net-(U1-Pad21)")
+      (node (ref U1) (pin 21)))
+    (net (code 142) (name "Net-(U8-Pad22)")
+      (node (ref U8) (pin 22)))
+    (net (code 143) (name "Net-(U8-Pad23)")
+      (node (ref U8) (pin 23)))
+    (net (code 144) (name "Net-(U8-Pad24)")
+      (node (ref U8) (pin 24)))
+    (net (code 145) (name "Net-(U8-Pad25)")
+      (node (ref U8) (pin 25)))
+    (net (code 146) (name "Net-(U8-Pad26)")
+      (node (ref U8) (pin 26)))
+    (net (code 147) (name "Net-(U8-Pad27)")
+      (node (ref U8) (pin 27)))
+    (net (code 148) (name "Net-(U8-Pad28)")
+      (node (ref U8) (pin 28)))
+    (net (code 149) (name "Net-(U8-Pad29)")
+      (node (ref U8) (pin 29)))
+    (net (code 150) (name "Net-(U8-Pad3)")
+      (node (ref U8) (pin 3)))
+    (net (code 151) (name "Net-(U8-Pad30)")
+      (node (ref U8) (pin 30)))
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+    (net (code 156) (name "Net-(U1-Pad6)")
+      (node (ref U1) (pin 6)))
+    (net (code 157) (name "Net-(U1-Pad7)")
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+    (net (code 170) (name "Net-(U6-Pad6)")
+      (node (ref U6) (pin 6)))
+    (net (code 171) (name "Net-(U6-Pad8)")
+      (node (ref U6) (pin 8)))
+    (net (code 172) (name "Net-(U6-Pad9)")
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+    (net (code 173) (name "Net-(U6-Pad10)")
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+    (net (code 179) (name "Net-(U1-Pad22)")
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+    (net (code 180) (name "Net-(U1-Pad23)")
+      (node (ref U1) (pin 23)))
+    (net (code 181) (name "Net-(U1-Pad24)")
+      (node (ref U1) (pin 24)))
+    (net (code 182) (name "Net-(U1-Pad25)")
+      (node (ref U1) (pin 25)))
+    (net (code 183) (name "Net-(U1-Pad26)")
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+    (net (code 184) (name "Net-(U1-Pad27)")
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+      (node (ref U1) (pin 28)))
+    (net (code 186) (name "Net-(U1-Pad29)")
+      (node (ref U1) (pin 29)))
+    (net (code 187) (name "Net-(U1-Pad30)")
+      (node (ref U1) (pin 30)))
+    (net (code 188) (name "Net-(U1-Pad31)")
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+    (net (code 189) (name "Net-(U1-Pad32)")
+      (node (ref U1) (pin 32)))
+    (net (code 190) (name "Net-(U1-Pad33)")
+      (node (ref U1) (pin 33)))
+    (net (code 191) (name "Net-(U8-Pad1)")
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+    (net (code 192) (name "Net-(U1-Pad36)")
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+    (net (code 193) (name "Net-(U1-Pad37)")
+      (node (ref U1) (pin 37)))
+    (net (code 194) (name "Net-(U1-Pad38)")
+      (node (ref U1) (pin 38)))
+    (net (code 195) (name "Net-(U1-Pad39)")
+      (node (ref U1) (pin 39)))
+    (net (code 196) (name "Net-(U1-Pad40)")
+      (node (ref U1) (pin 40)))
+    (net (code 197) (name "Net-(U1-Pad41)")
+      (node (ref U1) (pin 41)))
+    (net (code 198) (name "Net-(U1-Pad42)")
+      (node (ref U1) (pin 42)))
+    (net (code 199) (name "Net-(U1-Pad43)")
+      (node (ref U1) (pin 43)))
+    (net (code 200) (name "Net-(U1-Pad44)")
+      (node (ref U1) (pin 44)))
+    (net (code 201) (name "Net-(U1-Pad45)")
+      (node (ref U1) (pin 45)))
+    (net (code 202) (name "Net-(U1-Pad46)")
+      (node (ref U1) (pin 46)))))
\ No newline at end of file
diff --git a/MCL64/PCB/MCL64/MCL64.pro b/MCL64/PCB/MCL64/MCL64.pro
new file mode 100644
index 0000000..9181640
--- /dev/null
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diff --git a/MCL64/PCB/MCL64/MCL64.sch b/MCL64/PCB/MCL64/MCL64.sch
new file mode 100644
index 0000000..2bc3457
--- /dev/null
+++ b/MCL64/PCB/MCL64/MCL64.sch
@@ -0,0 +1,1241 @@
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+Wire Wire Line
+	2600 3900 2900 3900
+Text GLabel 2600 3900 0    50   Input ~ 0
+TEENSY_READY_n
+Wire Wire Line
+	2600 3800 2900 3800
+Text GLabel 2600 3800 0    50   Input ~ 0
+TEENSY_IRQ
+Wire Wire Line
+	5400 3700 5100 3700
+Text GLabel 5400 3700 2    50   Input ~ 0
+TEENSY_NMI
+Wire Wire Line
+	5400 3800 5100 3800
+Text GLabel 5400 3800 2    50   Input ~ 0
+TEENSY_RST
+Wire Wire Line
+	2600 3700 2900 3700
+Text GLabel 2600 3700 0    50   Input ~ 0
+TEENSY_CLKIN
+Wire Wire Line
+	5350 2200 5350 2050
+$Comp
+L power:GND #PWR?
+U 1 1 605017D7
+P 14350 5550
+F 0 "#PWR?" H 14350 5300 50  0001 C CNN
+F 1 "GND" H 14355 5377 50  0000 C CNN
+F 2 "" H 14350 5550 50  0001 C CNN
+F 3 "" H 14350 5550 50  0001 C CNN
+	1    14350 5550
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	14350 5550 14350 5400
+Wire Wire Line
+	14350 5400 14200 5400
+$Comp
+L Device:CP1 C?
+U 1 1 60529805
+P 9000 9650
+F 0 "C?" H 9115 9696 50  0000 L CNN
+F 1 "10uF" H 9115 9605 50  0000 L CNN
+F 2 "Capacitor_THT:C_Disc_D7.0mm_W2.5mm_P5.00mm" H 9000 9650 50  0001 C CNN
+F 3 "~" H 9000 9650 50  0001 C CNN
+	1    9000 9650
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:GND #PWR?
+U 1 1 6052A3E4
+P 9000 9950
+F 0 "#PWR?" H 9000 9700 50  0001 C CNN
+F 1 "GND" H 9005 9777 50  0000 C CNN
+F 2 "" H 9000 9950 50  0001 C CNN
+F 3 "" H 9000 9950 50  0001 C CNN
+	1    9000 9950
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	9000 9950 9000 9800
+$Comp
+L power:+3V3 #PWR?
+U 1 1 6053E1A1
+P 9000 9400
+F 0 "#PWR?" H 9000 9250 50  0001 C CNN
+F 1 "+3V3" H 9015 9573 50  0000 C CNN
+F 2 "" H 9000 9400 50  0001 C CNN
+F 3 "" H 9000 9400 50  0001 C CNN
+	1    9000 9400
+	-1   0    0    -1  
+$EndComp
+Wire Wire Line
+	9000 9500 9000 9400
+$EndSCHEMATC
diff --git a/MCL64/PCB/MCL64/MCL64.xml b/MCL64/PCB/MCL64/MCL64.xml
new file mode 100644
index 0000000..2d114db
--- /dev/null
+++ b/MCL64/PCB/MCL64/MCL64.xml
@@ -0,0 +1,723 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<export version="D">
+  <design>
+    <source>F:\Latest_1_9_2021\MCL64\MCL64_PCB\MCL64\MCL64.sch</source>
+    <date>3/16/2021 10:05:42 PM</date>
+    <tool>Eeschema (5.1.8)-1</tool>
+    <sheet number="1" name="/" tstamps="/">
+      <title_block>
+        <title/>
+        <company/>
+        <rev/>
+        <date/>
+        <source>MCL64.sch</source>
+        <comment number="1" value=""/>
+        <comment number="2" value=""/>
+        <comment number="3" value=""/>
+        <comment number="4" value=""/>
+      </title_block>
+    </sheet>
+  </design>
+  <components>
+    <comp ref="U1">
+      <value>Teensy 4.1</value>
+      <footprint>Teensy:Teensy41_Ted_Modified</footprint>
+      <datasheet>http://www.ti.com/lit/gpn/sn74LS04</datasheet>
+      <libsource lib="teensy" part="Teensy4.1" description=""/>
+      <sheetpath names="/" tstamps="/"/>
+      <tstamp>604E31A7</tstamp>
+    </comp>
+    <comp ref="U6">
+      <value>74LS04</value>
+      <footprint>Package_SO:SSOP-14_5.3x6.2mm_P0.65mm</footprint>
+      <datasheet>http://www.ti.com/lit/gpn/sn74LS04</datasheet>
+      <libsource lib="74xx" part="74LS04" description="Hex Inverter"/>
+      <sheetpath names="/" tstamps="/"/>
+      <tstamp>604EF080</tstamp>
+    </comp>
+    <comp ref="U7">
+      <value>74LS244</value>
+      <footprint>Package_SO:SSOP-20_5.3x7.2mm_P0.65mm</footprint>
+      <datasheet>http://www.ti.com/lit/ds/symlink/sn74ls244.pdf</datasheet>
+      <libsource lib="74xx" part="74LS244" description="Octal Buffer and Line Driver With 3-State Output, active-low enables, non-inverting outputs"/>
+      <sheetpath names="/" tstamps="/"/>
+      <tstamp>604F92C3</tstamp>
+    </comp>
+    <comp ref="U8">
+      <value>6510</value>
+      <footprint>Package_DIP:DIP-40_W15.24mm</footprint>
+      <datasheet>http://www.ti.com/lit/gpn/sn74LS04</datasheet>
+      <libsource lib="65xx" part="6510" description="6510 8-bit NMOS Microprocessor, 64K, 6-bit I/O Port, DIP-40"/>
+      <sheetpath names="/" tstamps="/"/>
+      <tstamp>604E276C</tstamp>
+    </comp>
+    <comp ref="U4">
+      <value>74LS573</value>
+      <footprint>Package_SO:SSOP-20_5.3x7.2mm_P0.65mm</footprint>
+      <datasheet>74xx/74hc573.pdf</datasheet>
+      <libsource lib="74xx" part="74LS573" description="8-bit Latch 3-state outputs"/>
+      <sheetpath names="/" tstamps="/"/>
+      <tstamp>6058D2B5</tstamp>
+    </comp>
+    <comp ref="U2">
+      <value>74LS573</value>
+      <footprint>Package_SO:SSOP-20_5.3x7.2mm_P0.65mm</footprint>
+      <datasheet>74xx/74hc573.pdf</datasheet>
+      <libsource lib="74xx" part="74LS573" description="8-bit Latch 3-state outputs"/>
+      <sheetpath names="/" tstamps="/"/>
+      <tstamp>605A5248</tstamp>
+    </comp>
+    <comp ref="U3">
+      <value>74LS573</value>
+      <footprint>Package_SO:SSOP-20_5.3x7.2mm_P0.65mm</footprint>
+      <datasheet>74xx/74hc573.pdf</datasheet>
+      <libsource lib="74xx" part="74LS573" description="8-bit Latch 3-state outputs"/>
+      <sheetpath names="/" tstamps="/"/>
+      <tstamp>605D8A68</tstamp>
+    </comp>
+    <comp ref="U5">
+      <value>74LS573</value>
+      <footprint>Package_SO:SSOP-20_5.3x7.2mm_P0.65mm</footprint>
+      <datasheet>74xx/74hc573.pdf</datasheet>
+      <libsource lib="74xx" part="74LS573" description="8-bit Latch 3-state outputs"/>
+      <sheetpath names="/" tstamps="/"/>
+      <tstamp>605FE39B</tstamp>
+    </comp>
+    <comp ref="C1">
+      <value>10uF</value>
+      <footprint>Capacitor_THT:C_Disc_D7.0mm_W2.5mm_P5.00mm</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="CP1" description="Polarized capacitor, US symbol"/>
+      <sheetpath names="/" tstamps="/"/>
+      <tstamp>60529805</tstamp>
+    </comp>
+  </components>
+  <libparts>
+    <libpart lib="65xx" part="6510">
+      <aliases>
+        <alias>8500</alias>
+      </aliases>
+      <description>6510 8-bit NMOS Microprocessor, 64K, 6-bit I/O Port, DIP-40</description>
+      <docs>http://www.6502.org/documents/datasheets/mos/mos_6510_mpu.pdf</docs>
+      <footprints>
+        <fp>DIP-40_W15.24mm*</fp>
+      </footprints>
+      <fields>
+        <field name="Reference">U</field>
+        <field name="Value">6510</field>
+      </fields>
+      <pins>
+        <pin num="1" name="ϕ0" type="input"/>
+        <pin num="2" name="RDY" type="input"/>
+        <pin num="3" name="~IRQ" type="input"/>
+        <pin num="4" name="~NMI" type="input"/>
+        <pin num="5" name="AEC" type="input"/>
+        <pin num="6" name="VCC" type="power_in"/>
+        <pin num="7" name="A0" type="3state"/>
+        <pin num="8" name="A1" type="3state"/>
+        <pin num="9" name="A2" type="3state"/>
+        <pin num="10" name="A3" type="3state"/>
+        <pin num="11" name="A4" type="3state"/>
+        <pin num="12" name="A5" type="3state"/>
+        <pin num="13" name="A6" type="3state"/>
+        <pin num="14" name="A7" type="3state"/>
+        <pin num="15" name="A8" type="3state"/>
+        <pin num="16" name="A9" type="3state"/>
+        <pin num="17" name="A10" type="3state"/>
+        <pin num="18" name="A11" type="3state"/>
+        <pin num="19" name="A12" type="3state"/>
+        <pin num="20" name="A13" type="3state"/>
+        <pin num="21" name="VSS" type="power_in"/>
+        <pin num="22" name="A14" type="3state"/>
+        <pin num="23" name="A15" type="3state"/>
+        <pin num="24" name="P5" type="BiDi"/>
+        <pin num="25" name="P4" type="BiDi"/>
+        <pin num="26" name="P3" type="BiDi"/>
+        <pin num="27" name="P2" type="BiDi"/>
+        <pin num="28" name="P1" type="BiDi"/>
+        <pin num="29" name="P0" type="BiDi"/>
+        <pin num="30" name="D7" type="BiDi"/>
+        <pin num="31" name="D6" type="BiDi"/>
+        <pin num="32" name="D5" type="BiDi"/>
+        <pin num="33" name="D4" type="BiDi"/>
+        <pin num="34" name="D3" type="BiDi"/>
+        <pin num="35" name="D2" type="BiDi"/>
+        <pin num="36" name="D1" type="BiDi"/>
+        <pin num="37" name="D0" type="BiDi"/>
+        <pin num="38" name="R/~W" type="3state"/>
+        <pin num="39" name="ϕ2" type="output"/>
+        <pin num="40" name="~RES" type="input"/>
+      </pins>
+    </libpart>
+    <libpart lib="74xx" part="74LS04">
+      <aliases>
+        <alias>74HC04</alias>
+        <alias>74HCT04</alias>
+        <alias>74AHC04</alias>
+        <alias>74AHCT04</alias>
+      </aliases>
+      <description>Hex Inverter</description>
+      <docs>http://www.ti.com/lit/gpn/sn74LS04</docs>
+      <footprints>
+        <fp>DIP*W7.62mm*</fp>
+        <fp>SSOP?14*</fp>
+        <fp>TSSOP?14*</fp>
+      </footprints>
+      <fields>
+        <field name="Reference">U</field>
+        <field name="Value">74LS04</field>
+      </fields>
+      <pins>
+        <pin num="1" name="~" type="input"/>
+        <pin num="2" name="~" type="output"/>
+        <pin num="3" name="~" type="input"/>
+        <pin num="4" name="~" type="output"/>
+        <pin num="5" name="~" type="input"/>
+        <pin num="6" name="~" type="output"/>
+        <pin num="7" name="GND" type="power_in"/>
+        <pin num="8" name="~" type="output"/>
+        <pin num="9" name="~" type="input"/>
+        <pin num="10" name="~" type="output"/>
+        <pin num="11" name="~" type="input"/>
+        <pin num="12" name="~" type="output"/>
+        <pin num="13" name="~" type="input"/>
+        <pin num="14" name="VCC" type="power_in"/>
+      </pins>
+    </libpart>
+    <libpart lib="74xx" part="74LS244">
+      <description>Octal Buffer and Line Driver With 3-State Output, active-low enables, non-inverting outputs</description>
+      <docs>http://www.ti.com/lit/ds/symlink/sn74ls244.pdf</docs>
+      <footprints>
+        <fp>DIP?20*</fp>
+      </footprints>
+      <fields>
+        <field name="Reference">U</field>
+        <field name="Value">74LS244</field>
+      </fields>
+      <pins>
+        <pin num="1" name="OEa" type="input"/>
+        <pin num="2" name="I0a" type="input"/>
+        <pin num="3" name="O3b" type="3state"/>
+        <pin num="4" name="I1a" type="input"/>
+        <pin num="5" name="O2b" type="3state"/>
+        <pin num="6" name="I2a" type="input"/>
+        <pin num="7" name="O1b" type="3state"/>
+        <pin num="8" name="I3a" type="input"/>
+        <pin num="9" name="O0b" type="3state"/>
+        <pin num="10" name="GND" type="power_in"/>
+        <pin num="11" name="I0b" type="input"/>
+        <pin num="12" name="O3a" type="3state"/>
+        <pin num="13" name="I1b" type="input"/>
+        <pin num="14" name="O2a" type="3state"/>
+        <pin num="15" name="I2b" type="input"/>
+        <pin num="16" name="O1a" type="3state"/>
+        <pin num="17" name="I3b" type="input"/>
+        <pin num="18" name="O0a" type="3state"/>
+        <pin num="19" name="OEb" type="input"/>
+        <pin num="20" name="VCC" type="power_in"/>
+      </pins>
+    </libpart>
+    <libpart lib="74xx" part="74LS573">
+      <description>8-bit Latch 3-state outputs</description>
+      <docs>74xx/74hc573.pdf</docs>
+      <footprints>
+        <fp>DIP?20*</fp>
+      </footprints>
+      <fields>
+        <field name="Reference">U</field>
+        <field name="Value">74LS573</field>
+      </fields>
+      <pins>
+        <pin num="1" name="OE" type="input"/>
+        <pin num="2" name="D0" type="input"/>
+        <pin num="3" name="D1" type="input"/>
+        <pin num="4" name="D2" type="input"/>
+        <pin num="5" name="D3" type="input"/>
+        <pin num="6" name="D4" type="input"/>
+        <pin num="7" name="D5" type="input"/>
+        <pin num="8" name="D6" type="input"/>
+        <pin num="9" name="D7" type="input"/>
+        <pin num="10" name="GND" type="power_in"/>
+        <pin num="11" name="Load" type="input"/>
+        <pin num="12" name="Q7" type="3state"/>
+        <pin num="13" name="Q6" type="3state"/>
+        <pin num="14" name="Q5" type="3state"/>
+        <pin num="15" name="Q4" type="3state"/>
+        <pin num="16" name="Q3" type="3state"/>
+        <pin num="17" name="Q2" type="3state"/>
+        <pin num="18" name="Q1" type="3state"/>
+        <pin num="19" name="Q0" type="3state"/>
+        <pin num="20" name="VCC" type="power_in"/>
+      </pins>
+    </libpart>
+    <libpart lib="Device" part="CP1">
+      <description>Polarized capacitor, US symbol</description>
+      <docs>~</docs>
+      <footprints>
+        <fp>CP_*</fp>
+      </footprints>
+      <fields>
+        <field name="Reference">C</field>
+        <field name="Value">CP1</field>
+      </fields>
+      <pins>
+        <pin num="1" name="~" type="passive"/>
+        <pin num="2" name="~" type="passive"/>
+      </pins>
+    </libpart>
+    <libpart lib="teensy" part="Teensy4.1">
+      <fields>
+        <field name="Reference">U</field>
+        <field name="Value">Teensy4.1</field>
+      </fields>
+      <pins>
+        <pin num="1" name="GND" type="power_in"/>
+        <pin num="2" name="0_RX1_CRX2_CS1" type="BiDi"/>
+        <pin num="3" name="1_TX1_CTX2_MISO1" type="BiDi"/>
+        <pin num="4" name="2_OUT2" type="BiDi"/>
+        <pin num="5" name="3_LRCLK2" type="BiDi"/>
+        <pin num="6" name="4_BCLK2" type="BiDi"/>
+        <pin num="7" name="5_IN2" type="BiDi"/>
+        <pin num="8" name="6_OUT1D" type="BiDi"/>
+        <pin num="9" name="7_RX2_OUT1A" type="BiDi"/>
+        <pin num="10" name="8_TX2_IN1" type="BiDi"/>
+        <pin num="11" name="9_OUT1C" type="BiDi"/>
+        <pin num="12" name="10_CS_MQSR" type="BiDi"/>
+        <pin num="13" name="11_MOSI_CTX1" type="BiDi"/>
+        <pin num="14" name="12_MISO_MQSL" type="BiDi"/>
+        <pin num="15" name="3V3" type="power_in"/>
+        <pin num="16" name="24_A10_TX6_SCL2" type="BiDi"/>
+        <pin num="17" name="25_A11_RX6_SDA2" type="BiDi"/>
+        <pin num="18" name="26_A12_MOSI1" type="BiDi"/>
+        <pin num="19" name="27_A13_SCK1" type="BiDi"/>
+        <pin num="20" name="28_RX7" type="BiDi"/>
+        <pin num="21" name="29_TX7" type="BiDi"/>
+        <pin num="22" name="30_CRX3" type="BiDi"/>
+        <pin num="23" name="31_CTX3" type="BiDi"/>
+        <pin num="24" name="32_OUT1B" type="BiDi"/>
+        <pin num="25" name="33_MCLK2" type="BiDi"/>
+        <pin num="26" name="34_RX8" type="BiDi"/>
+        <pin num="27" name="35_TX8" type="BiDi"/>
+        <pin num="28" name="36_CS" type="BiDi"/>
+        <pin num="29" name="37_CS" type="BiDi"/>
+        <pin num="30" name="38_CS1_IN1" type="BiDi"/>
+        <pin num="31" name="39_MISO1_OUT1A" type="BiDi"/>
+        <pin num="32" name="40_A16" type="BiDi"/>
+        <pin num="33" name="41_A17" type="BiDi"/>
+        <pin num="34" name="GND" type="power_in"/>
+        <pin num="35" name="13_SCK_LED" type="BiDi"/>
+        <pin num="36" name="14_A0_TX3_SPDIF_OUT" type="BiDi"/>
+        <pin num="37" name="15_A1_RX3_SPDIF_IN" type="BiDi"/>
+        <pin num="38" name="16_A2_RX4_SCL1" type="BiDi"/>
+        <pin num="39" name="17_A3_TX4_SDA1" type="BiDi"/>
+        <pin num="40" name="18_A4_SDA" type="BiDi"/>
+        <pin num="41" name="19_A5_SCL" type="BiDi"/>
+        <pin num="42" name="20_A6_TX5_LRCLK1" type="BiDi"/>
+        <pin num="43" name="21_A7_RX5_BCLK1" type="BiDi"/>
+        <pin num="44" name="22_A8_CTX1" type="BiDi"/>
+        <pin num="45" name="23_A9_CRX1_MCLK1" type="BiDi"/>
+        <pin num="46" name="3V3" type="output"/>
+        <pin num="47" name="GND" type="output"/>
+        <pin num="48" name="VIN" type="power_in"/>
+      </pins>
+    </libpart>
+  </libparts>
+  <libraries>
+    <library logical="65xx">
+      <uri>F:/Latest_1_9_2021/MCL64/MCL64_PCB/65xx.lib</uri>
+    </library>
+    <library logical="74xx">
+      <uri>C:\Program Files\KiCad\share\kicad\library/74xx.lib</uri>
+    </library>
+    <library logical="Device">
+      <uri>C:\Program Files\KiCad\share\kicad\library/Device.lib</uri>
+    </library>
+    <library logical="teensy">
+      <uri>Z:/Ted/projs/KiCAD_Library/Teensy/teensy.lib</uri>
+    </library>
+  </libraries>
+  <nets>
+    <net code="1" name="TEENSY_A8">
+      <node ref="U1" pin="23"/>
+      <node ref="U3" pin="2"/>
+    </net>
+    <net code="2" name="TEENSY_A9">
+      <node ref="U3" pin="3"/>
+      <node ref="U1" pin="26"/>
+    </net>
+    <net code="3" name="TEENSY_A10">
+      <node ref="U1" pin="24"/>
+      <node ref="U3" pin="4"/>
+    </net>
+    <net code="4" name="TEENSY_A11">
+      <node ref="U3" pin="5"/>
+      <node ref="U1" pin="25"/>
+    </net>
+    <net code="5" name="TEENSY_A13">
+      <node ref="U1" pin="2"/>
+      <node ref="U3" pin="7"/>
+    </net>
+    <net code="6" name="TEENSY_A14">
+      <node ref="U1" pin="4"/>
+      <node ref="U3" pin="8"/>
+    </net>
+    <net code="7" name="TEENSY_A15">
+      <node ref="U1" pin="45"/>
+      <node ref="U3" pin="9"/>
+    </net>
+    <net code="8" name="TEENSY_DATA_OE_n">
+      <node ref="U1" pin="5"/>
+      <node ref="U5" pin="1"/>
+    </net>
+    <net code="9" name="TEENSY_A0">
+      <node ref="U2" pin="2"/>
+      <node ref="U1" pin="19"/>
+    </net>
+    <net code="10" name="TEENSY_A1">
+      <node ref="U1" pin="30"/>
+      <node ref="U2" pin="3"/>
+    </net>
+    <net code="11" name="TEENSY_A3">
+      <node ref="U1" pin="29"/>
+      <node ref="U2" pin="5"/>
+    </net>
+    <net code="12" name="TEENSY_A4">
+      <node ref="U2" pin="6"/>
+      <node ref="U1" pin="21"/>
+    </net>
+    <net code="13" name="TEENSY_A5">
+      <node ref="U2" pin="7"/>
+      <node ref="U1" pin="28"/>
+    </net>
+    <net code="14" name="TEENSY_A6">
+      <node ref="U1" pin="22"/>
+      <node ref="U2" pin="8"/>
+    </net>
+    <net code="15" name="TEENSY_A7">
+      <node ref="U1" pin="27"/>
+      <node ref="U2" pin="9"/>
+    </net>
+    <net code="16" name="GND">
+      <node ref="C1" pin="2"/>
+      <node ref="U4" pin="10"/>
+      <node ref="U4" pin="1"/>
+      <node ref="U2" pin="10"/>
+      <node ref="U7" pin="10"/>
+      <node ref="U7" pin="19"/>
+      <node ref="U1" pin="1"/>
+      <node ref="U1" pin="34"/>
+      <node ref="U3" pin="10"/>
+      <node ref="U5" pin="10"/>
+      <node ref="U8" pin="21"/>
+      <node ref="U8" pin="24"/>
+      <node ref="U6" pin="7"/>
+      <node ref="U1" pin="47"/>
+    </net>
+    <net code="17" name="+3V3">
+      <node ref="C1" pin="1"/>
+      <node ref="U3" pin="20"/>
+      <node ref="U1" pin="46"/>
+      <node ref="U7" pin="20"/>
+      <node ref="U1" pin="15"/>
+      <node ref="U6" pin="14"/>
+      <node ref="U5" pin="11"/>
+      <node ref="U2" pin="20"/>
+      <node ref="U4" pin="20"/>
+      <node ref="U2" pin="11"/>
+      <node ref="U5" pin="20"/>
+      <node ref="U3" pin="11"/>
+    </net>
+    <net code="18" name="CPU_AEC">
+      <node ref="U8" pin="5"/>
+      <node ref="U6" pin="1"/>
+    </net>
+    <net code="19" name="CPU_AEC_n">
+      <node ref="U2" pin="1"/>
+      <node ref="U6" pin="2"/>
+      <node ref="U7" pin="1"/>
+      <node ref="U3" pin="1"/>
+    </net>
+    <net code="20" name="CPU_D6">
+      <node ref="U5" pin="13"/>
+      <node ref="U8" pin="31"/>
+      <node ref="U4" pin="8"/>
+    </net>
+    <net code="21" name="CPU_D5">
+      <node ref="U8" pin="32"/>
+      <node ref="U5" pin="14"/>
+      <node ref="U4" pin="7"/>
+    </net>
+    <net code="22" name="CPU_D3">
+      <node ref="U5" pin="16"/>
+      <node ref="U4" pin="5"/>
+      <node ref="U8" pin="34"/>
+    </net>
+    <net code="23" name="CPU_D2">
+      <node ref="U5" pin="17"/>
+      <node ref="U4" pin="4"/>
+      <node ref="U8" pin="35"/>
+    </net>
+    <net code="24" name="CPU_D0">
+      <node ref="U5" pin="19"/>
+      <node ref="U4" pin="2"/>
+      <node ref="U8" pin="37"/>
+    </net>
+    <net code="25" name="TEENSY_OUT_D4">
+      <node ref="U5" pin="6"/>
+      <node ref="U1" pin="9"/>
+    </net>
+    <net code="26" name="TEENSY_OUT_D5">
+      <node ref="U1" pin="8"/>
+      <node ref="U5" pin="7"/>
+    </net>
+    <net code="27" name="TEENSY_OUT_D6">
+      <node ref="U1" pin="7"/>
+      <node ref="U5" pin="8"/>
+    </net>
+    <net code="28" name="TEENSY_OUT_D7">
+      <node ref="U5" pin="9"/>
+      <node ref="U1" pin="6"/>
+    </net>
+    <net code="29" name="TEENSY_A2">
+      <node ref="U1" pin="20"/>
+      <node ref="U2" pin="4"/>
+    </net>
+    <net code="30" name="CPU_D1">
+      <node ref="U4" pin="3"/>
+      <node ref="U8" pin="36"/>
+      <node ref="U5" pin="18"/>
+    </net>
+    <net code="31" name="CPU_D4">
+      <node ref="U8" pin="33"/>
+      <node ref="U5" pin="15"/>
+      <node ref="U4" pin="6"/>
+    </net>
+    <net code="32" name="CPU_D7">
+      <node ref="U8" pin="30"/>
+      <node ref="U4" pin="9"/>
+      <node ref="U5" pin="12"/>
+    </net>
+    <net code="33" name="TEENSY_A12">
+      <node ref="U1" pin="3"/>
+      <node ref="U3" pin="6"/>
+    </net>
+    <net code="34" name="TEENSY_OUT_D3">
+      <node ref="U1" pin="10"/>
+      <node ref="U5" pin="5"/>
+    </net>
+    <net code="35" name="TEENSY_IN_D6">
+      <node ref="U1" pin="42"/>
+      <node ref="U4" pin="13"/>
+    </net>
+    <net code="36" name="TEENSY_IN_D1">
+      <node ref="U1" pin="37"/>
+      <node ref="U4" pin="18"/>
+    </net>
+    <net code="37" name="TEENSY_IN_D2">
+      <node ref="U1" pin="38"/>
+      <node ref="U4" pin="17"/>
+    </net>
+    <net code="38" name="TEENSY_IN_D3">
+      <node ref="U4" pin="16"/>
+      <node ref="U1" pin="39"/>
+    </net>
+    <net code="39" name="TEENSY_IN_D4">
+      <node ref="U4" pin="15"/>
+      <node ref="U1" pin="40"/>
+    </net>
+    <net code="40" name="TEENSY_IN_D5">
+      <node ref="U1" pin="41"/>
+      <node ref="U4" pin="14"/>
+    </net>
+    <net code="41" name="TEENSY_IN_D7">
+      <node ref="U1" pin="43"/>
+      <node ref="U4" pin="12"/>
+    </net>
+    <net code="42" name="TEENSY_OUT_D0">
+      <node ref="U1" pin="13"/>
+      <node ref="U5" pin="2"/>
+    </net>
+    <net code="43" name="TEENSY_OUT_D1">
+      <node ref="U5" pin="3"/>
+      <node ref="U1" pin="12"/>
+    </net>
+    <net code="44" name="TEENSY_OUT_D2">
+      <node ref="U5" pin="4"/>
+      <node ref="U1" pin="11"/>
+    </net>
+    <net code="45" name="TEENSY_NMI">
+      <node ref="U6" pin="8"/>
+      <node ref="U1" pin="33"/>
+    </net>
+    <net code="46" name="TEENSY_RST">
+      <node ref="U6" pin="10"/>
+      <node ref="U1" pin="32"/>
+    </net>
+    <net code="47" name="TEENSY_CLKIN">
+      <node ref="U1" pin="16"/>
+      <node ref="U6" pin="12"/>
+    </net>
+    <net code="48" name="TEENSY_IRQ">
+      <node ref="U6" pin="6"/>
+      <node ref="U1" pin="17"/>
+    </net>
+    <net code="49" name="TEENSY_P1">
+      <node ref="U7" pin="15"/>
+      <node ref="U1" pin="35"/>
+    </net>
+    <net code="50" name="TEENSY_P2">
+      <node ref="U7" pin="17"/>
+      <node ref="U1" pin="31"/>
+    </net>
+    <net code="51" name="TEENSY_P0">
+      <node ref="U7" pin="13"/>
+      <node ref="U1" pin="44"/>
+    </net>
+    <net code="52" name="TEENSY_WR_n">
+      <node ref="U1" pin="14"/>
+      <node ref="U7" pin="2"/>
+    </net>
+    <net code="53" name="TEENSY_READY_n">
+      <node ref="U1" pin="18"/>
+      <node ref="U6" pin="4"/>
+    </net>
+    <net code="54" name="CPU_P2">
+      <node ref="U8" pin="27"/>
+      <node ref="U7" pin="3"/>
+    </net>
+    <net code="55" name="CPU_P1">
+      <node ref="U7" pin="5"/>
+      <node ref="U8" pin="28"/>
+    </net>
+    <net code="56" name="CPU_P0">
+      <node ref="U7" pin="7"/>
+      <node ref="U8" pin="29"/>
+    </net>
+    <net code="57" name="CPU_READY">
+      <node ref="U6" pin="3"/>
+      <node ref="U8" pin="2"/>
+    </net>
+    <net code="58" name="CPU_WR_n">
+      <node ref="U8" pin="38"/>
+      <node ref="U7" pin="18"/>
+    </net>
+    <net code="59" name="CPU_IRQ_n">
+      <node ref="U6" pin="5"/>
+      <node ref="U8" pin="3"/>
+    </net>
+    <net code="60" name="CPU_NMI_n">
+      <node ref="U8" pin="4"/>
+      <node ref="U6" pin="9"/>
+    </net>
+    <net code="61" name="CPU_RST_n">
+      <node ref="U8" pin="40"/>
+      <node ref="U6" pin="11"/>
+    </net>
+    <net code="62" name="CPU_CLKOUT">
+      <node ref="U7" pin="9"/>
+      <node ref="U8" pin="39"/>
+    </net>
+    <net code="63" name="TEENSY_IN_D0">
+      <node ref="U4" pin="19"/>
+      <node ref="U1" pin="36"/>
+    </net>
+    <net code="64" name="CPU_CLKIN">
+      <node ref="U6" pin="13"/>
+      <node ref="U7" pin="11"/>
+      <node ref="U4" pin="11"/>
+      <node ref="U8" pin="1"/>
+    </net>
+    <net code="65" name="CPU_A2">
+      <node ref="U2" pin="17"/>
+      <node ref="U8" pin="9"/>
+    </net>
+    <net code="66" name="CPU_A6">
+      <node ref="U8" pin="13"/>
+      <node ref="U2" pin="13"/>
+    </net>
+    <net code="67" name="CPU_A5">
+      <node ref="U2" pin="14"/>
+      <node ref="U8" pin="12"/>
+    </net>
+    <net code="68" name="CPU_A4">
+      <node ref="U8" pin="11"/>
+      <node ref="U2" pin="15"/>
+    </net>
+    <net code="69" name="CPU_A3">
+      <node ref="U2" pin="16"/>
+      <node ref="U8" pin="10"/>
+    </net>
+    <net code="70" name="CPU_A7">
+      <node ref="U2" pin="12"/>
+      <node ref="U8" pin="14"/>
+    </net>
+    <net code="71" name="CPU_A1">
+      <node ref="U2" pin="18"/>
+      <node ref="U8" pin="8"/>
+    </net>
+    <net code="72" name="CPU_A0">
+      <node ref="U8" pin="7"/>
+      <node ref="U2" pin="19"/>
+    </net>
+    <net code="73" name="CPU_A11">
+      <node ref="U3" pin="16"/>
+      <node ref="U8" pin="18"/>
+    </net>
+    <net code="74" name="Net-(U7-Pad8)">
+      <node ref="U7" pin="8"/>
+    </net>
+    <net code="75" name="CPU_A8">
+      <node ref="U3" pin="19"/>
+      <node ref="U8" pin="15"/>
+    </net>
+    <net code="76" name="CPU_A9">
+      <node ref="U8" pin="16"/>
+      <node ref="U3" pin="18"/>
+    </net>
+    <net code="77" name="CPU_A10">
+      <node ref="U3" pin="17"/>
+      <node ref="U8" pin="17"/>
+    </net>
+    <net code="78" name="CPU_A12">
+      <node ref="U3" pin="15"/>
+      <node ref="U8" pin="19"/>
+    </net>
+    <net code="79" name="CPU_A13">
+      <node ref="U3" pin="14"/>
+      <node ref="U8" pin="20"/>
+    </net>
+    <net code="80" name="CPU_A14">
+      <node ref="U3" pin="13"/>
+      <node ref="U8" pin="22"/>
+    </net>
+    <net code="81" name="CPU_A15">
+      <node ref="U3" pin="12"/>
+      <node ref="U8" pin="23"/>
+    </net>
+    <net code="82" name="Net-(U8-Pad25)">
+      <node ref="U8" pin="25"/>
+    </net>
+    <net code="83" name="Net-(U8-Pad26)">
+      <node ref="U8" pin="26"/>
+    </net>
+    <net code="84" name="Net-(U7-Pad16)">
+      <node ref="U7" pin="16"/>
+    </net>
+    <net code="85" name="Net-(U7-Pad12)">
+      <node ref="U7" pin="12"/>
+    </net>
+    <net code="86" name="Net-(U7-Pad14)">
+      <node ref="U7" pin="14"/>
+    </net>
+    <net code="87" name="Net-(U7-Pad4)">
+      <node ref="U7" pin="4"/>
+    </net>
+    <net code="88" name="Net-(U7-Pad6)">
+      <node ref="U7" pin="6"/>
+    </net>
+    <net code="89" name="+5V">
+      <node ref="U8" pin="6"/>
+      <node ref="U1" pin="48"/>
+    </net>
+  </nets>
+</export>
diff --git a/MCL64/PCB/MCL64/MCL64_Schematic.pdf b/MCL64/PCB/MCL64/MCL64_Schematic.pdf
new file mode 100644
index 0000000..cd50f8b
Binary files /dev/null and b/MCL64/PCB/MCL64/MCL64_Schematic.pdf differ
diff --git a/MCL64/PCB/MCL64/PCB_Products/MCL64-B_Mask.gbr b/MCL64/PCB/MCL64/PCB_Products/MCL64-B_Mask.gbr
new file mode 100644
index 0000000..235e895
--- /dev/null
+++ b/MCL64/PCB/MCL64/PCB_Products/MCL64-B_Mask.gbr
@@ -0,0 +1,1073 @@
+G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.8)-1*
+G04 #@! TF.CreationDate,2021-03-17T09:54:22-07:00*
+G04 #@! TF.ProjectId,MCL64,4d434c36-342e-46b6-9963-61645f706362,rev?*
+G04 #@! TF.SameCoordinates,Original*
+G04 #@! TF.FileFunction,Soldermask,Bot*
+G04 #@! TF.FilePolarity,Negative*
+%FSLAX46Y46*%
+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
+G04 Created by KiCad (PCBNEW (5.1.8)-1) date 2021-03-17 09:54:22*
+%MOMM*%
+%LPD*%
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diff --git a/MCL64/PCB/MCL64/PCB_Products/MCL64-B_Paste.gbr b/MCL64/PCB/MCL64/PCB_Products/MCL64-B_Paste.gbr
new file mode 100644
index 0000000..919b6ad
--- /dev/null
+++ b/MCL64/PCB/MCL64/PCB_Products/MCL64-B_Paste.gbr
@@ -0,0 +1,975 @@
+G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.8)-1*
+G04 #@! TF.CreationDate,2021-03-17T09:54:22-07:00*
+G04 #@! TF.ProjectId,MCL64,4d434c36-342e-46b6-9963-61645f706362,rev?*
+G04 #@! TF.SameCoordinates,Original*
+G04 #@! TF.FileFunction,Paste,Bot*
+G04 #@! TF.FilePolarity,Positive*
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+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
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new file mode 100644
index 0000000..827e73e
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new file mode 100644
index 0000000..9a1e51e
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diff --git a/MCL64/PCB/MCL64/PCB_Products/MCL64-F_Paste.gbr b/MCL64/PCB/MCL64/PCB_Products/MCL64-F_Paste.gbr
new file mode 100644
index 0000000..fd9f6e7
--- /dev/null
+++ b/MCL64/PCB/MCL64/PCB_Products/MCL64-F_Paste.gbr
@@ -0,0 +1,1471 @@
+G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.8)-1*
+G04 #@! TF.CreationDate,2021-03-17T09:54:22-07:00*
+G04 #@! TF.ProjectId,MCL64,4d434c36-342e-46b6-9963-61645f706362,rev?*
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+G04 #@! TF.FileFunction,Paste,Top*
+G04 #@! TF.FilePolarity,Positive*
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+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
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diff --git a/MCL64/PCB/MCL64/PCB_Products/MCL64-F_SilkS.gbr b/MCL64/PCB/MCL64/PCB_Products/MCL64-F_SilkS.gbr
new file mode 100644
index 0000000..e30a0b1
--- /dev/null
+++ b/MCL64/PCB/MCL64/PCB_Products/MCL64-F_SilkS.gbr
@@ -0,0 +1,441 @@
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new file mode 100644
index 0000000..4ef2972
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diff --git a/MCL64/PCB/MCL64/PCB_Products/MCL64-Inner2_Cu.gbr b/MCL64/PCB/MCL64/PCB_Products/MCL64-Inner2_Cu.gbr
new file mode 100644
index 0000000..d38b9b1
--- /dev/null
+++ b/MCL64/PCB/MCL64/PCB_Products/MCL64-Inner2_Cu.gbr
@@ -0,0 +1,9733 @@
+G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.8)-1*
+G04 #@! TF.CreationDate,2021-03-17T09:54:22-07:00*
+G04 #@! TF.ProjectId,MCL64,4d434c36-342e-46b6-9963-61645f706362,rev?*
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+G04 Created by KiCad (PCBNEW (5.1.8)-1) date 2021-03-17 09:54:22*
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+G04 #@! TA.AperFunction,Conductor*
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diff --git a/MCL64/PCB/MCL64/PCB_Products/MCL64-Top_Cu.gbr b/MCL64/PCB/MCL64/PCB_Products/MCL64-Top_Cu.gbr
new file mode 100644
index 0000000..2d36285
--- /dev/null
+++ b/MCL64/PCB/MCL64/PCB_Products/MCL64-Top_Cu.gbr
@@ -0,0 +1,2386 @@
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diff --git a/MCL64/PCB/MCL64/PCB_Products/MCL64-bottom-pos.csv b/MCL64/PCB/MCL64/PCB_Products/MCL64-bottom-pos.csv
new file mode 100644
index 0000000..a39aad3
--- /dev/null
+++ b/MCL64/PCB/MCL64/PCB_Products/MCL64-bottom-pos.csv
@@ -0,0 +1,3 @@
+Ref,Val,Package,PosX,PosY,Rot,Side
+"U3","74LS573","SSOP-20_5.3x7.2mm_P0.65mm",28.727400,17.749520,180.000000,bottom
+"U4","74LS573","SSOP-20_5.3x7.2mm_P0.65mm",10.287000,23.136860,180.000000,bottom
diff --git a/MCL64/PCB/MCL64/PCB_Products/MCL64-job.gbrjob b/MCL64/PCB/MCL64/PCB_Products/MCL64-job.gbrjob
new file mode 100644
index 0000000..9d1f3fb
--- /dev/null
+++ b/MCL64/PCB/MCL64/PCB_Products/MCL64-job.gbrjob
@@ -0,0 +1,163 @@
+{
+  "Header":
+  {
+    "GenerationSoftware":
+    {
+      "Vendor":      "KiCad",
+      "Application": "Pcbnew",
+      "Version":     "(5.1.8)-1"
+    },
+    "CreationDate":  "2021-03-17T09:54:22-07:00"
+  },
+  "GeneralSpecs":
+  {
+    "ProjectId":
+    {
+      "Name": "MCL64",
+      "GUID": "4d434c36-342e-46b6-9963-61645f706362",
+      "Revision": "rev?"
+    },
+    "Size":
+    {
+      "X": 41.786,
+      "Y": 64.366
+    },
+    "LayerNumber": 4,
+    "BoardThickness":  1.600
+  },
+  "DesignRules":
+  [
+    {
+      "Layers": "Outer",
+      "PadToPad":  0.127,
+      "PadToTrack":  0.127,
+      "TrackToTrack":  0.127,
+      "MinLineWidth":  0.178
+    },
+    {
+      "Layers": "Inner",
+      "PadToPad":  0.127,
+      "PadToTrack":  0.127,
+      "TrackToTrack":  0.127,
+      "MinLineWidth":  0.178,
+      "TrackToRegion":  0.254,
+      "RegionToRegion":  0.254
+    }
+  ],
+  "FilesAttributes":
+  [
+    {
+      "Path":  "MCL64-Top_Cu.gbr",
+      "FileFunction":  "Copper,L1,Top",
+      "FilePolarity":  "Positive"
+    },
+    {
+      "Path":  "MCL64-Inner1_Cu.gbr",
+      "FileFunction":  "Copper,L2,Inr",
+      "FilePolarity":  "Positive"
+    },
+    {
+      "Path":  "MCL64-Inner2_Cu.gbr",
+      "FileFunction":  "Copper,L3,Inr",
+      "FilePolarity":  "Positive"
+    },
+    {
+      "Path":  "MCL64-Bottom_Cu.gbr",
+      "FileFunction":  "Copper,L4,Bot",
+      "FilePolarity":  "Positive"
+    },
+    {
+      "Path":  "MCL64-F_Paste.gbr",
+      "FileFunction":  "SolderPaste,Top",
+      "FilePolarity":  "Positive"
+    },
+    {
+      "Path":  "MCL64-B_Paste.gbr",
+      "FileFunction":  "SolderPaste,Bot",
+      "FilePolarity":  "Positive"
+    },
+    {
+      "Path":  "MCL64-F_SilkS.gbr",
+      "FileFunction":  "Legend,Top",
+      "FilePolarity":  "Positive"
+    },
+    {
+      "Path":  "MCL64-B_SilkS.gbr",
+      "FileFunction":  "Legend,Bot",
+      "FilePolarity":  "Positive"
+    },
+    {
+      "Path":  "MCL64-F_Mask.gbr",
+      "FileFunction":  "SolderMask,Top",
+      "FilePolarity":  "Negative"
+    },
+    {
+      "Path":  "MCL64-B_Mask.gbr",
+      "FileFunction":  "SolderMask,Bot",
+      "FilePolarity":  "Negative"
+    },
+    {
+      "Path":  "MCL64-Edge_Cuts.gbr",
+      "FileFunction":  "Profile",
+      "FilePolarity":  "Positive"
+    }
+  ],
+  "MaterialStackup":
+  [
+    {
+      "Type":  "Legend",
+      "Notes":  "Layer F.SilkS"
+    },
+    {
+      "Type":  "SolderPaste",
+      "Notes":  "Layer F.Paste"
+    },
+    {
+      "Type":  "SolderMask",
+      "Notes":  "Layer F.Mask"
+    },
+    {
+      "Type":  "Copper",
+      "Notes":  "Layer Top.Cu"
+    },
+    {
+      "Type":  "Dielectric",
+      "Material":  "FR4",
+      "Notes":  "Layers L1/L2"
+    },
+    {
+      "Type":  "Copper",
+      "Notes":  "Layer Inner1.Cu"
+    },
+    {
+      "Type":  "Dielectric",
+      "Material":  "FR4",
+      "Notes":  "Layers L2/L3"
+    },
+    {
+      "Type":  "Copper",
+      "Notes":  "Layer Inner2.Cu"
+    },
+    {
+      "Type":  "Dielectric",
+      "Material":  "FR4",
+      "Notes":  "Layers L3/L4"
+    },
+    {
+      "Type":  "Copper",
+      "Notes":  "Layer Bottom.Cu"
+    },
+    {
+      "Type":  "SolderMask",
+      "Notes":  "Layer B.Mask"
+    },
+    {
+      "Type":  "SolderPaste",
+      "Notes":  "Layer B.Paste"
+    },
+    {
+      "Type":  "Legend",
+      "Notes":  "Layer B.SilkS"
+    }
+  ]
+}
diff --git a/MCL64/PCB/MCL64/PCB_Products/MCL64-top-pos.csv b/MCL64/PCB/MCL64/PCB_Products/MCL64-top-pos.csv
new file mode 100644
index 0000000..907d0cb
--- /dev/null
+++ b/MCL64/PCB/MCL64/PCB_Products/MCL64-top-pos.csv
@@ -0,0 +1,5 @@
+Ref,Val,Package,PosX,PosY,Rot,Side
+"U2","74LS573","SSOP-20_5.3x7.2mm_P0.65mm",9.847580,36.959540,0.000000,top
+"U5","74LS573","SSOP-20_5.3x7.2mm_P0.65mm",10.253980,23.103840,0.000000,top
+"U6","74LS04","SSOP-14_5.3x6.2mm_P0.65mm",28.676600,52.082700,0.000000,top
+"U7","74LS244","SSOP-20_5.3x7.2mm_P0.65mm",28.524200,36.855400,0.000000,top
diff --git a/MCL64/PCB/MCL64/PCB_Products/MCL64.zip b/MCL64/PCB/MCL64/PCB_Products/MCL64.zip
new file mode 100644
index 0000000..0854cb9
Binary files /dev/null and b/MCL64/PCB/MCL64/PCB_Products/MCL64.zip differ
diff --git a/MCL64/PCB/MCL64/fp-info-cache b/MCL64/PCB/MCL64/fp-info-cache
new file mode 100644
index 0000000..f56a1e9
--- /dev/null
+++ b/MCL64/PCB/MCL64/fp-info-cache
@@ -0,0 +1,435 @@
+99453256981182
+Resistor_SMD
+R_0201_0603Metric
+Resistor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator
+resistor
+0
+4
+2
+Resistor_SMD
+R_0201_0603Metric_Pad0.64x0.40mm_HandSolder
+Resistor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+4
+2
+Resistor_SMD
+R_0402_1005Metric
+Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_0402_1005Metric_Pad0.72x0.64mm_HandSolder
+Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_0603_1608Metric
+Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_0603_1608Metric_Pad0.98x0.95mm_HandSolder
+Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_0612_1632Metric
+Resistor SMD 0612 (1632 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20019/rcwe.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_0612_1632Metric_Pad1.18x3.40mm_HandSolder
+Resistor SMD 0612 (1632 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.vishay.com/docs/20019/rcwe.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_0805_2012Metric
+Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_0805_2012Metric_Pad1.20x1.40mm_HandSolder
+Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_0815_2038Metric
+Resistor SMD 0815 (2038 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.susumu.co.jp/common/pdf/n_catalog_partition07_en.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_0815_2038Metric_Pad1.20x4.05mm_HandSolder
+Resistor SMD 0815 (2038 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.susumu.co.jp/common/pdf/n_catalog_partition07_en.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_01005_0402Metric
+Resistor SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator
+resistor
+0
+4
+2
+Resistor_SMD
+R_01005_0402Metric_Pad0.57x0.30mm_HandSolder
+Resistor SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+4
+2
+Resistor_SMD
+R_1020_2550Metric
+Resistor SMD 1020 (2550 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20019/rcwe.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_1020_2550Metric_Pad1.33x5.20mm_HandSolder
+Resistor SMD 1020 (2550 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.vishay.com/docs/20019/rcwe.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_1206_3216Metric
+Resistor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_1206_3216Metric_Pad1.30x1.75mm_HandSolder
+Resistor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_1210_3225Metric
+Resistor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_1210_3225Metric_Pad1.30x2.65mm_HandSolder
+Resistor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_1218_3246Metric
+Resistor SMD 1218 (3246 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20035/dcrcwe3.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_1218_3246Metric_Pad1.22x4.75mm_HandSolder
+Resistor SMD 1218 (3246 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.vishay.com/docs/20035/dcrcwe3.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_1812_4532Metric
+Resistor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_1812_4532Metric_Pad1.30x3.40mm_HandSolder
+Resistor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_2010_5025Metric
+Resistor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_2010_5025Metric_Pad1.40x2.65mm_HandSolder
+Resistor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_2512_6332Metric
+Resistor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_2512_6332Metric_Pad1.40x3.35mm_HandSolder
+Resistor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_2816_7142Metric
+Resistor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_2816_7142Metric_Pad3.20x4.45mm_HandSolder
+Resistor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_4020_10251Metric
+Resistor SMD 4020 (10251 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://datasheet.octopart.com/HVC0603T5004FET-Ohmite-datasheet-26699797.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_4020_10251Metric_Pad1.65x5.30mm_HandSolder
+Resistor SMD 4020 (10251 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://datasheet.octopart.com/HVC0603T5004FET-Ohmite-datasheet-26699797.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_Array_Concave_2x0603
+Thick Film Chip Resistor Array, Wave soldering, Vishay CRA06P (see cra06p.pdf)
+resistor array
+0
+4
+4
+Resistor_SMD
+R_Array_Concave_4x0402
+Thick Film Chip Resistor Array, Wave soldering, Vishay CRA04P (see cra04p.pdf)
+resistor array
+0
+8
+8
+Resistor_SMD
+R_Array_Concave_4x0603
+Thick Film Chip Resistor Array, Wave soldering, Vishay CRA06P (see cra06p.pdf)
+resistor array
+0
+8
+8
+Resistor_SMD
+R_Array_Convex_2x0402
+Chip Resistor Network, ROHM MNR02 (see mnr_g.pdf)
+resistor array
+0
+4
+4
+Resistor_SMD
+R_Array_Convex_2x0603
+Chip Resistor Network, ROHM MNR12 (see mnr_g.pdf)
+resistor array
+0
+4
+4
+Resistor_SMD
+R_Array_Convex_2x0606
+Precision Thin Film Chip Resistor Array, VISHAY (see http://www.vishay.com/docs/28770/acasat.pdf)
+resistor array
+0
+4
+4
+Resistor_SMD
+R_Array_Convex_2x1206
+Chip Resistor Network, ROHM MNR32 (see mnr_g.pdf)
+resistor array
+0
+4
+4
+Resistor_SMD
+R_Array_Convex_4x0402
+Chip Resistor Network, ROHM MNR04 (see mnr_g.pdf)
+resistor array
+0
+8
+8
+Resistor_SMD
+R_Array_Convex_4x0603
+Chip Resistor Network, ROHM MNR14 (see mnr_g.pdf)
+resistor array
+0
+8
+8
+Resistor_SMD
+R_Array_Convex_4x0612
+Precision Thin Film Chip Resistor Array, VISHAY (see http://www.vishay.com/docs/28770/acasat.pdf)
+resistor array
+0
+8
+8
+Resistor_SMD
+R_Array_Convex_4x1206
+Chip Resistor Network, ROHM MNR34 (see mnr_g.pdf)
+resistor array
+0
+8
+8
+Resistor_SMD
+R_Array_Convex_5x0603
+Chip Resistor Network, ROHM MNR15 (see mnr_g.pdf)
+resistor array
+0
+10
+10
+Resistor_SMD
+R_Array_Convex_5x1206
+Chip Resistor Network, ROHM MNR35 (see mnr_g.pdf)
+resistor array
+0
+10
+10
+Resistor_SMD
+R_Array_Convex_8x0602
+Chip Resistor Network, ROHM MNR18 (see mnr_g.pdf)
+resistor array
+0
+16
+16
+Resistor_SMD
+R_Cat16-2
+SMT resistor net, Bourns CAT16 series, 2 way
+SMT resistor net Bourns CAT16 series 2 way
+0
+4
+4
+Resistor_SMD
+R_Cat16-4
+SMT resistor net, Bourns CAT16 series, 4 way
+SMT resistor net Bourns CAT16 series 4 way
+0
+8
+8
+Resistor_SMD
+R_Cat16-8
+SMT resistor net, Bourns CAT16 series, 8 way
+SMT resistor net Bourns CAT16 series 8 way
+0
+16
+16
+Resistor_SMD
+R_MELF_MMB-0207
+Resistor, MELF, MMB-0207, http://www.vishay.com/docs/28713/melfprof.pdf
+MELF Resistor
+0
+2
+2
+Resistor_SMD
+R_MicroMELF_MMU-0102
+Resistor, MicroMELF, MMU-0102, http://www.vishay.com/docs/28713/melfprof.pdf
+MicroMELF Resistor
+0
+2
+2
+Resistor_SMD
+R_MiniMELF_MMA-0204
+Resistor, MiniMELF, MMA-0204, http://www.vishay.com/docs/28713/melfprof.pdf
+MiniMELF Resistor
+0
+2
+2
+Resistor_SMD
+R_Shunt_Ohmite_LVK12
+4 contact shunt resistor
+shunt resistor 4 contacts
+0
+4
+4
+Resistor_SMD
+R_Shunt_Ohmite_LVK20
+4 contacts shunt resistor, https://www.ohmite.com/assets/docs/res_lvk.pdf
+4 contacts resistor smd
+0
+4
+4
+Resistor_SMD
+R_Shunt_Ohmite_LVK24
+4 contacts shunt resistor,https://www.ohmite.com/assets/docs/res_lvk.pdf
+4 contacts resistor smd
+0
+4
+4
+Resistor_SMD
+R_Shunt_Ohmite_LVK25
+4 contacts shunt resistor,https://www.ohmite.com/assets/docs/res_lvk.pdf
+4 contacts resistor smd
+0
+4
+4
+Resistor_SMD
+R_Shunt_Vishay_WSK2512_6332Metric_T1.19mm
+Shunt Resistor SMD 2512 (6332 Metric), 2.6mm thick, Vishay WKS2512, Terminal length (T) 1.19mm, 5 to 200 milli Ohm (http://http://www.vishay.com/docs/30108/wsk.pdf)
+resistor shunt WSK2512
+0
+4
+4
+Resistor_SMD
+R_Shunt_Vishay_WSK2512_6332Metric_T2.21mm
+Shunt Resistor SMD 2512 (6332 Metric), 2.6mm thick, Vishay WKS2512, Terminal length (T) 2.21mm, 1 to 4.9 milli Ohm (http://http://www.vishay.com/docs/30108/wsk.pdf)
+resistor shunt WSK2512
+0
+4
+4
+Resistor_SMD
+R_Shunt_Vishay_WSK2512_6332Metric_T2.66mm
+Shunt Resistor SMD 2512 (6332 Metric), 2.6mm thick, Vishay WKS2512, Terminal length (T) 2.66mm, 0.5 to 0.99 milli Ohm (http://http://www.vishay.com/docs/30108/wsk.pdf)
+resistor shunt WSK2512
+0
+4
+4
+Resistor_SMD
+R_Shunt_Vishay_WSKW0612
+https://www.vishay.com/docs/30332/wskw0612.pdf
+4-Terminal SMD Shunt
+0
+4
+4
+Resistor_SMD
+R_Shunt_Vishay_WSR2_WSR3
+Power Metal Strip Resistors 0.005 to 0.2, https://www.vishay.com/docs/30101/wsr.pdf
+SMD Shunt Resistor
+0
+2
+2
+Resistor_SMD
+R_Shunt_Vishay_WSR2_WSR3_KelvinConnection
+Power Metal Strip Resistors 0.005 to 0.2, https://www.vishay.com/docs/30101/wsr.pdf
+SMD Shunt Resistor
+0
+4
+2
diff --git a/MCL64/PCB/MCL64/sym-lib-table b/MCL64/PCB/MCL64/sym-lib-table
new file mode 100644
index 0000000..83d229a
--- /dev/null
+++ b/MCL64/PCB/MCL64/sym-lib-table
@@ -0,0 +1,3 @@
+(sym_lib_table
+  (lib (name 65xx)(type Legacy)(uri F:/Latest_1_9_2021/MCL64/MCL64_PCB/65xx.lib)(options "")(descr ""))
+)
diff --git a/MCL64/SourceCode/MCL64.ino b/MCL64/SourceCode/MCL64.ino
new file mode 100644
index 0000000..7d6a5a6
--- /dev/null
+++ b/MCL64/SourceCode/MCL64.ino
@@ -0,0 +1,2120 @@
+//
+//
+//  File Name   :  MCL64.c
+//  Used on     :  
+//  Author      :  Ted Fried, MicroCore Labs
+//  Creation    :  4/21/2021
+//
+//   Description:
+//   ============
+//   
+//  MOS 6510 emulator with bus interface.
+//
+//------------------------------------------------------------------------
+//
+// Modification History:
+// =====================
+//
+// Revision 1 4/21/2021
+// Initial revision
+//
+//
+//------------------------------------------------------------------------
+//
+// Copyright (c) 2021 Ted Fried
+// 
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+// 
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+// 
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+//------------------------------------------------------------------------
+
+#include <stdint.h>
+
+// Teensy 4.1 pin assignments
+//
+#define PIN_CLK0            24
+#define PIN_READY_n          26
+#define PIN_IRQ             25
+#define PIN_NMI             41
+#define PIN_RESET           40
+#define PIN_RDWR_n          12
+#define PIN_P0              22
+#define PIN_P1              13
+#define PIN_P2              39
+                    
+#define PIN_ADDR0           27 
+#define PIN_ADDR1           38 
+#define PIN_ADDR2           28 
+#define PIN_ADDR3           37 
+#define PIN_ADDR4           29 
+#define PIN_ADDR5           36 
+#define PIN_ADDR6           30 
+#define PIN_ADDR7           35         
+#define PIN_ADDR8           31 
+#define PIN_ADDR9           34 
+#define PIN_ADDR10          32 
+#define PIN_ADDR11          33 
+#define PIN_ADDR12          1  
+#define PIN_ADDR13          0  
+#define PIN_ADDR14          2  
+#define PIN_ADDR15          23 
+        
+#define PIN_DATAIN0         14 
+#define PIN_DATAIN1         15 
+#define PIN_DATAIN2         16 
+#define PIN_DATAIN3         17 
+#define PIN_DATAIN4         18 
+#define PIN_DATAIN5         19 
+#define PIN_DATAIN6         20 
+#define PIN_DATAIN7         21 
+        
+#define PIN_DATAOUT0        11 
+#define PIN_DATAOUT1        10 
+#define PIN_DATAOUT2        9 
+#define PIN_DATAOUT3        8 
+#define PIN_DATAOUT4        7 
+#define PIN_DATAOUT5        6 
+#define PIN_DATAOUT6        5 
+#define PIN_DATAOUT7        4 
+#define PIN_DATAOUT_OE_n    3 
+
+
+// 6502 Flags
+//
+#define flag_n    (register_flags & 0x80) >> 7    // register_flags[7]
+#define flag_v    (register_flags & 0x40) >> 6    // register_flags[6]
+#define flag_b    (register_flags & 0x10) >> 4    // register_flags[4]
+#define flag_d    (register_flags & 0x08) >> 3    // register_flags[3]
+#define flag_i    (register_flags & 0x04) >> 2    // register_flags[2]
+#define flag_z    (register_flags & 0x02) >> 1    // register_flags[1]
+#define flag_c    (register_flags & 0x01) >> 0    // register_flags[0]
+
+
+
+#define Page_128_159  ( (current_address >= 0x8000) && (current_address <= 0x9FFF) ) ? 0x1 : 0x0 
+#define Page_160_191  ( (current_address >= 0xA000) && (current_address <= 0xBFFF) ) ? 0x1 : 0x0 
+#define Page_224_255  ( (current_address >= 0xE000) && (current_address <= 0xFFFF) ) ? 0x1 : 0x0 
+
+#define bank_mode  ( (EXROM<<4) | (GAME<<3) | (current_p&0x7)  )
+
+// 6502 stack always in Page 1
+//
+#define register_sp_fixed  (0x0100 | register_sp)
+
+
+// CPU register for direct reads of the GPIOs
+//
+uint8_t   current_p=0x7; 
+uint8_t   register_flags=0x34; 
+uint8_t   next_instruction;
+uint8_t   internal_memory_range=0;
+uint8_t   nmi_n_old=1;
+uint8_t   register_a=0;
+uint8_t   register_x=0;
+uint8_t   register_y=0;
+uint8_t   register_sp=0xFF;
+uint8_t   direct_datain=0;
+uint8_t   direct_reset=0;
+uint8_t   direct_ready_n=0;
+uint8_t   direct_irq=0;
+uint8_t   direct_nmi=0;
+uint8_t   assert_sync=0;
+uint8_t   global_temp=0;
+uint8_t   last_access_internal_RAM=0;
+
+uint16_t  register_pc=0;
+uint16_t  current_address=0;
+uint16_t  effective_address=0;
+
+uint8_t   internal_RAM[65536];
+
+
+// First few bytes of Commodore 64 Copyrighted ROMs
+//
+uint8_t   BASIC_ROM[0x2000]={ 0x94,0xe3,0x7b,0xe3,0x43,0x42,0x4d,0x42,0x41,0x53,0x49,0x43,0x30,0xa8,0x41,0xa7,0x1d,0xad };
+uint8_t   KERNAL_ROM[0x2000]={ 0x85,0x56,0x20,0xf,0xbc,0xa5,0x61,0xc9,0x88,0x90,0x3,0x20,0xd4,0xba,0x20,0xcc,0xbc,0xa5,0x7 };
+
+
+// Dead Test
+
+#define EXROM  1
+#define GAME   1
+// First few bytes of Copyrighted ROMs
+uint8_t   CART_HIGH_ROM[0x4000]={ 0x78,0xa2,0xff,0x9a,0xd8,0xa9,0xe7,0x85,0x1,0xa9,0x37,0x85,0x0,0x4c,0x83,0xe1,0xa9 } ;
+uint8_t   CART_LOW_ROM[0x2000];
+
+
+// When set to 1 it will remove the unnecessary 6502 bus fetches, reads, and writes
+// Set to 0 for cycle-accurate mode
+//
+#define SPEEDUP 1
+    
+// ------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
+
+// Setup Teensy 4.1 IO's
+//
+void setup() {
+  
+  pinMode(PIN_CLK0,        INPUT);  
+  pinMode(PIN_RESET,       INPUT);  
+  pinMode(PIN_READY_n,     INPUT);  
+  pinMode(PIN_IRQ,         INPUT);  
+  pinMode(PIN_NMI,         INPUT);  
+  pinMode(PIN_RDWR_n,      OUTPUT); 
+  pinMode(PIN_P0,          OUTPUT); 
+  pinMode(PIN_P1,          OUTPUT); 
+  pinMode(PIN_P2,          OUTPUT); 
+  
+  pinMode(PIN_ADDR0,       OUTPUT); 
+  pinMode(PIN_ADDR1,       OUTPUT); 
+  pinMode(PIN_ADDR2,       OUTPUT); 
+  pinMode(PIN_ADDR3,       OUTPUT); 
+  pinMode(PIN_ADDR4,       OUTPUT); 
+  pinMode(PIN_ADDR5,       OUTPUT); 
+  pinMode(PIN_ADDR6,       OUTPUT); 
+  pinMode(PIN_ADDR7,       OUTPUT);
+  pinMode(PIN_ADDR8,       OUTPUT); 
+  pinMode(PIN_ADDR9,       OUTPUT); 
+  pinMode(PIN_ADDR10,      OUTPUT); 
+  pinMode(PIN_ADDR11,      OUTPUT); 
+  pinMode(PIN_ADDR12,      OUTPUT); 
+  pinMode(PIN_ADDR13,      OUTPUT); 
+  pinMode(PIN_ADDR14,      OUTPUT); 
+  pinMode(PIN_ADDR15,      OUTPUT);  
+  
+  pinMode(PIN_DATAIN0,     INPUT); 
+  pinMode(PIN_DATAIN1,     INPUT); 
+  pinMode(PIN_DATAIN2,     INPUT); 
+  pinMode(PIN_DATAIN3,     INPUT); 
+  pinMode(PIN_DATAIN4,     INPUT); 
+  pinMode(PIN_DATAIN5,     INPUT); 
+  pinMode(PIN_DATAIN6,     INPUT); 
+  pinMode(PIN_DATAIN7,     INPUT);
+    
+  pinMode(PIN_DATAOUT0,    OUTPUT); 
+  pinMode(PIN_DATAOUT1,    OUTPUT); 
+  pinMode(PIN_DATAOUT2,    OUTPUT); 
+  pinMode(PIN_DATAOUT3,    OUTPUT); 
+  pinMode(PIN_DATAOUT4,    OUTPUT); 
+  pinMode(PIN_DATAOUT5,    OUTPUT); 
+  pinMode(PIN_DATAOUT6,    OUTPUT); 
+  pinMode(PIN_DATAOUT7,    OUTPUT);
+  pinMode(PIN_DATAOUT_OE_n,  OUTPUT); 
+
+  digitalWriteFast(PIN_P0, 0x1 ); 
+  digitalWriteFast(PIN_P1, 0x1 ); 
+  digitalWriteFast(PIN_P2, 0x1 ); 
+
+}
+
+
+// --------------------------------------------------------------------------------------------------
+// --------------------------------------------------------------------------------------------------
+//
+// Begin 6502 Bus Interface Unit 
+//
+// --------------------------------------------------------------------------------------------------
+// --------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------------------------
+// Address range check
+//  Return: 0x0 - All exernal memory accesses
+//          0x1 - Reads and writes are cycle accurate using internal memory with writes passing through to motherboard
+//          0x2 - Reads accelerated using internal memory and writes are cycle accurate and pass through to motherboard
+//          0x3 - All read and write accesses use accelerated internal memory 
+// ----------------------------------------------------------
+inline uint8_t internal_address_check(uint16_t local_address) {
+
+  if ( (local_address > 0x0001 ) && (local_address <= 0x03FF) ) return 0x1;  //   Zero-Page up to video 
+  if ( (local_address >= 0x0400) && (local_address <= 0x07FF) ) return 0x1;  //   C64 Video Memory 
+  if ( (local_address >= 0x0800) && (local_address <= 0x9FFF) ) return 0x1;  //   C64 RAM 
+  if ( (local_address >= 0xA000) && (local_address <= 0xBFFF) ) return 0x1;  //   C64 BASIC ROM
+  if ( (local_address >= 0xC000) && (local_address <= 0xCFFF) ) return 0x1;  //   C64 RAM
+//if ( (local_address >= 0xD000) && (local_address <= 0xDFFF) ) return 0x1;  //   C64 I/O
+  if ( (local_address >= 0xE000) && (local_address <= 0xE4FF) ) return 0x1;  //   C64 KERNAL ROM  
+  if ( (local_address >= 0xE500) && (local_address <= 0xFF7F) ) return 0x1;  //   C64 KERNAL ROM  
+  if ( (local_address >= 0xFF80) && (local_address <= 0xFFFF) ) return 0x1;  //   C64 KERNAL ROM 
+
+  return 0x0;
+} 
+
+
+// -------------------------------------------------
+// Wait for the CLK1 rising edge and sample signals
+// -------------------------------------------------
+inline void wait_for_CLK_rising_edge() {
+  register uint32_t GPIO6_data=0;
+  register uint32_t GPIO6_data_d1=0;
+  uint32_t   d10, d2, d3, d4, d5, d76;
+
+    while (((GPIO6_DR >> 12) & 0x1)!=0) {}            // Teensy 4.1 Pin-24  GPIO6_DR[12]     CLK
+    
+    while (((GPIO6_DR >> 12) & 0x1)==0) {GPIO6_data=GPIO6_DR;}                  // This method is ok for VIC-20 and Apple-II+ non-DRAM ranges 
+    
+    //do {  GPIO6_data_d1=GPIO6_DR;   } while (((GPIO6_data_d1 >> 12) & 0x1)==0);   // This method needed to support Apple-II+ DRAM read data setup time
+    //GPIO6_data=GPIO6_data_d1;
+    
+    d10             = (GPIO6_data&0x000C0000) >> 18;  // Teensy 4.1 Pin-14  GPIO6_DR[19:18]  D1:D0
+    d2              = (GPIO6_data&0x00800000) >> 21;  // Teensy 4.1 Pin-16  GPIO6_DR[23]     D2
+    d3              = (GPIO6_data&0x00400000) >> 19;  // Teensy 4.1 Pin-17  GPIO6_DR[22]     D3
+    d4              = (GPIO6_data&0x00020000) >> 13;  // Teensy 4.1 Pin-18  GPIO6_DR[17]     D4
+    d5              = (GPIO6_data&0x00010000) >> 11;  // Teensy 4.1 Pin-19  GPIO6_DR[16]     D5
+    d76             = (GPIO6_data&0x0C000000) >> 20;  // Teensy 4.1 Pin-20  GPIO6_DR[27:26]  D7:D6
+    
+    direct_irq      = (GPIO6_data&0x00002000) >> 13;  // Teensy 4.1 Pin-25  GPIO6_DR[13]     IRQ
+    direct_ready_n  = (GPIO6_data&0x40000000) >> 30;  // Teensy 4.1 Pin-26  GPIO6_DR[30]     READY
+    direct_reset    = (GPIO6_data&0x00100000) >> 20;  // Teensy 4.1 Pin-40  GPIO6_DR[20]     RESET
+    direct_nmi      = (GPIO6_data&0x00200000) >> 21;  // Teensy 4.1 Pin-41  GPIO6_DR[21]     NMI
+    
+    direct_datain = d76 | d5 | d4 | d3 | d2 | d10;
+    
+    return; 
+}
+
+
+// -------------------------------------------------
+// Wait for the CLK1 falling edge 
+// -------------------------------------------------
+inline void wait_for_CLK_falling_edge() {
+
+  while (((GPIO6_DR >> 12) & 0x1)==0) {}   // Teensy 4.1 Pin-24  GPIO6_DR[12]  CLK
+  while (((GPIO6_DR >> 12) & 0x1)!=0) {}
+  return; 
+}
+
+
+// -------------------------------------------------
+// Drive the 6502 Address pins
+// -------------------------------------------------
+inline void send_address(uint32_t local_address) {
+  register uint32_t writeback_data=0;
+  
+    writeback_data = (0x6DFFFFF3 & GPIO6_DR);   // Read in current GPIOx register value and clear the bits we intend to update
+    writeback_data = writeback_data | (local_address & 0x8000)<<10 ;  // 6502_Address[15]   TEENSY_PIN23   GPIO6_DR[25]
+    writeback_data = writeback_data | (local_address & 0x2000)>>10 ;  // 6502_Address[13]   TEENSY_PIN0    GPIO6_DR[3]
+    writeback_data = writeback_data | (local_address & 0x1000)>>10 ;  // 6502_Address[12]   TEENSY_PIN1    GPIO6_DR[2]
+    writeback_data = writeback_data | (local_address & 0x0002)<<27 ;  // 6502_Address[1]    TEENSY_PIN38   GPIO6_DR[28]
+    GPIO6_DR       = writeback_data | (local_address & 0x0001)<<31 ;  // 6502_Address[0]    TEENSY_PIN27   GPIO6_DR[31]
+    
+    writeback_data = (0xCFF3EFFF & GPIO7_DR);   // Read in current GPIOx register value and clear the bits we intend to update
+    writeback_data = writeback_data | (local_address & 0x0400)<<2  ;  // 6502_Address[10]   TEENSY_PIN32   GPIO7_DR[12]
+    writeback_data = writeback_data | (local_address & 0x0200)<<20 ;  // 6502_Address[9]    TEENSY_PIN34   GPIO7_DR[29]
+    writeback_data = writeback_data | (local_address & 0x0080)<<21 ;  // 6502_Address[7]    TEENSY_PIN35   GPIO7_DR[28]
+    writeback_data = writeback_data | (local_address & 0x0020)<<13 ;  // 6502_Address[5]    TEENSY_PIN36   GPIO7_DR[18]
+    GPIO7_DR       = writeback_data | (local_address & 0x0008)<<16 ;  // 6502_Address[3]    TEENSY_PIN37   GPIO7_DR[19]
+                
+    writeback_data = (0xFF3BFFFF & GPIO8_DR);   // Read in current GPIOx register value and clear the bits we intend to update
+    writeback_data = writeback_data | (local_address & 0x0100)<<14 ;  // 6502_Address[8]    TEENSY_PIN31   GPIO8_DR[22]
+    writeback_data = writeback_data | (local_address & 0x0040)<<17 ;  // 6502_Address[6]    TEENSY_PIN30   GPIO8_DR[23]
+    GPIO8_DR       = writeback_data | (local_address & 0x0004)<<16 ;  // 6502_Address[2]    TEENSY_PIN28   GPIO8_DR[18]
+    
+    writeback_data = (0x7FFFFF6F & GPIO9_DR);   // Read in current GPIOx register value and clear the bits we intend to update
+    writeback_data = writeback_data | (local_address & 0x4000)>>10 ;  // 6502_Address[14]   TEENSY_PIN2    GPIO9_DR[4]
+    writeback_data = writeback_data | (local_address & 0x0800)>>4  ;  // 6502_Address[11]   TEENSY_PIN33   GPIO9_DR[7]
+    GPIO9_DR       = writeback_data | (local_address & 0x0010)<<27 ;  // 6502_Address[4]    TEENSY_PIN29   GPIO9_DR[31]
+    
+    return;
+}
+
+        
+// -------------------------------------------------
+// Send the address for a read cyle
+// -------------------------------------------------
+inline void start_read(uint32_t local_address) {
+  
+  current_address = local_address; 
+   
+    if (internal_address_check(current_address)>0x1)  { 
+      //last_access_internal_RAM=1;
+    }
+
+    else 
+    {
+       if (last_access_internal_RAM==1) wait_for_CLK_rising_edge();
+       last_access_internal_RAM=0;
+
+        digitalWriteFast(PIN_RDWR_n,  0x1);
+        send_address(local_address);
+     }
+    return;
+}
+
+
+
+// -------------------------------------------------
+// Fetch data from the correct C64 address bank
+// -------------------------------------------------
+inline uint8_t fetch_byte_from_bank() {
+
+
+    if (Page_128_159==0x1)  {  if ( (EXROM==1 && GAME==0) || ( EXROM==0 && ((bank_mode&0x3)==0x3) ) )          {  return CART_LOW_ROM[current_address - 0x8000];     }
+                               else                                                                            {  return internal_RAM[current_address];              }  }
+                               
+    if (Page_160_191==0x1)  {  if       ( EXROM==0 && ((bank_mode&0x2)==0x2) )                                 {  return CART_HIGH_ROM[current_address - 0xA000];    }
+                               else if  ( GAME==1  && ((bank_mode&0x3)==0x3) )                                 {  return BASIC_ROM[current_address & 0x1FFF];        }
+                               else                                                                            {  return internal_RAM[current_address];              }  }
+    
+    if (Page_224_255==0x1)  {  if (EXROM==1 && GAME==0)                                                        {  return CART_HIGH_ROM[current_address - 0xE000];    }
+                               else if ( (bank_mode&0x2)==0x2)                                                 {  return KERNAL_ROM[current_address & 0x1FFF];       }
+                               else                                                                            {  return internal_RAM[current_address];              }  }
+    
+     return internal_RAM[current_address];
+}
+  
+
+// -------------------------------------------------
+// On the rising CLK edge, read in the data
+// -------------------------------------------------
+inline uint8_t finish_read_byte() {  
+  
+  if (internal_address_check(current_address)>0x1)  {
+    last_access_internal_RAM=1;
+    return fetch_byte_from_bank();   
+    }         
+    else 
+    {
+       if (last_access_internal_RAM==1) wait_for_CLK_rising_edge();
+       last_access_internal_RAM=0;
+       
+       do {  wait_for_CLK_rising_edge();  }  while (direct_ready_n == 0x1);  // Delay a clock cycle until ready is active 
+                      
+       if (internal_address_check(current_address)>0x0)  {  return fetch_byte_from_bank();   }
+       else                                              {  if (current_address==0x1) return (current_p|0x10); else return direct_datain;                  }
+    }
+}
+  
+
+
+// -------------------------------------------------
+// Full read cycle with address and data read in
+// -------------------------------------------------
+inline uint8_t read_byte(uint16_t local_address) {  
+  
+  current_address = local_address;
+  
+  if (internal_address_check(local_address)>0x1)  {
+    last_access_internal_RAM=1;
+        return fetch_byte_from_bank(); 
+    }
+    else 
+    {
+       if (last_access_internal_RAM==1) wait_for_CLK_rising_edge();
+       last_access_internal_RAM=0;
+       
+       start_read(local_address);
+       do {  wait_for_CLK_rising_edge();  }  while (direct_ready_n == 0x1);  // Delay a clock cycle until ready is active 
+
+       if (internal_address_check(current_address)>0x0)  {  return fetch_byte_from_bank();  }
+       else                                              {  if (current_address==0x1) return (current_p|0x10); else return direct_datain;                  }
+     }
+} 
+
+
+// -------------------------------------------------
+// Full write cycle with address and data written
+// -------------------------------------------------
+inline void write_byte(uint16_t local_address , uint8_t local_write_data) {
+  
+  // Internal RAM
+  //
+    if (internal_address_check(local_address)>0x2)  {
+    last_access_internal_RAM=1;
+    internal_RAM[local_address] = local_write_data;
+      //if ( (Page_128_159==0x1)  && ( (EXROM==1 && GAME==0) || ( EXROM==0 && ((bank_mode&0x3)==0x3) ) )) {  } else internal_RAM[local_address] = local_write_data; 
+  }
+  else 
+  {
+       if (last_access_internal_RAM==1) wait_for_CLK_rising_edge();
+       last_access_internal_RAM=0;
+       internal_RAM[local_address] = local_write_data;
+      //if ( (Page_128_159==0x1)  && ( (EXROM==1 && GAME==0) || ( EXROM==0 && ((bank_mode&0x3)==0x3) ) )) {  } else internal_RAM[local_address] = local_write_data; 
+     
+       digitalWriteFast(PIN_RDWR_n,  0x0);
+       send_address(local_address);
+
+       
+     // Drive the data bus pins from the Teensy to the bus driver which is inactive
+     //
+       digitalWriteFast(PIN_DATAOUT0,  (local_write_data & 0x01)    );
+       digitalWriteFast(PIN_DATAOUT1,  (local_write_data & 0x02)>>1 ); 
+       digitalWriteFast(PIN_DATAOUT2,  (local_write_data & 0x04)>>2 ); 
+       digitalWriteFast(PIN_DATAOUT3,  (local_write_data & 0x08)>>3 ); 
+       digitalWriteFast(PIN_DATAOUT4,  (local_write_data & 0x10)>>4 ); 
+       digitalWriteFast(PIN_DATAOUT5,  (local_write_data & 0x20)>>5 ); 
+       digitalWriteFast(PIN_DATAOUT6,  (local_write_data & 0x40)>>6 ); 
+       digitalWriteFast(PIN_DATAOUT7,  (local_write_data & 0x80)>>7 ); 
+     
+       if (local_address==0x1) {  
+       current_p = local_write_data;
+       digitalWriteFast(PIN_P0,  (local_write_data & 0x01) ); 
+       digitalWriteFast(PIN_P1,  (local_write_data & 0x02) >> 1 ); 
+       digitalWriteFast(PIN_P2,  (local_write_data & 0x04) >> 2 ); 
+     }
+     
+       
+       // During the second CLK phase, enable the data bus output drivers
+       //
+       wait_for_CLK_falling_edge();
+       digitalWriteFast(PIN_DATAOUT_OE_n,  0x0 ); 
+       
+       wait_for_CLK_rising_edge();
+       digitalWriteFast(PIN_DATAOUT_OE_n,  0x1 );   
+  }            
+   return;
+}
+
+  
+// --------------------------------------------------------------------------------------------------
+// --------------------------------------------------------------------------------------------------
+//
+// End 6502 Bus Interface Unit
+//
+// --------------------------------------------------------------------------------------------------
+// --------------------------------------------------------------------------------------------------
+
+
+void push(uint8_t push_data) {    
+    write_byte(register_sp_fixed, push_data); 
+    register_sp = register_sp - 1;
+    return;
+}
+
+
+uint8_t pop() {
+    uint8_t temp=0;
+    register_sp = register_sp + 1;
+    temp = read_byte(register_sp_fixed);
+    return temp;
+}
+    
+  
+void Calc_Flags_NEGATIVE_ZERO(uint8_t local_data) {
+    
+    if (0x80&local_data)   register_flags = register_flags | 0x80;              // Set the N flag
+    else                   register_flags = register_flags & 0x7F;              // Clear the N flag
+    
+    if (local_data==0)     register_flags = register_flags | 0x02;              // Set the Z flag
+    else                   register_flags = register_flags & 0xFD;              // Clear the Z flag 
+    
+    return;
+}
+
+
+uint16_t Sign_Extend16(uint16_t reg_data)  {
+    if ((reg_data&0x0080)== 0x0080)   { return (reg_data | 0xFF00); } 
+    else                              { return (reg_data & 0x00FF); }  
+}
+
+
+void Begin_Fetch_Next_Opcode()  {
+    register_pc++;
+    assert_sync=1;
+    start_read(register_pc);
+    return;
+}
+
+
+// -------------------------------------------------
+// Addressing Modes
+// -------------------------------------------------
+uint8_t Fetch_Immediate()  {
+    register_pc++;
+    return read_byte(register_pc);
+}
+
+uint8_t Fetch_ZeroPage()  { 
+    effective_address = Fetch_Immediate(); 
+    return read_byte(effective_address);
+}
+
+uint8_t Fetch_ZeroPage_X()  {   
+    uint16_t bal;
+    bal = Fetch_Immediate();
+    if (SPEEDUP==0) read_byte(register_pc+1); 
+    effective_address = (0x00FF & (bal + register_x));
+    return read_byte(effective_address);
+}
+
+uint8_t Fetch_ZeroPage_Y()  {   
+    uint16_t bal;
+    bal = Fetch_Immediate();
+    if (SPEEDUP==0) read_byte(register_pc+1); 
+    effective_address = (0x00FF & (bal + register_y)); 
+    return read_byte(effective_address);
+}
+
+uint16_t Calculate_Absolute()  { 
+    uint16_t adl, adh;
+
+    adl = Fetch_Immediate();
+    adh = Fetch_Immediate()<<8;
+    effective_address = adl + adh;  
+    return effective_address;
+}
+
+uint8_t Fetch_Absolute()  { 
+    uint16_t adl, adh;
+
+    adl = Fetch_Immediate();
+    adh = Fetch_Immediate()<<8;
+    effective_address = adl + adh;  
+    return read_byte(effective_address);
+}
+
+uint8_t Fetch_Absolute_X(uint8_t page_cross_check)  {
+    uint16_t bal, bah;
+    uint8_t  local_data;
+    
+    bal = Fetch_Immediate();
+    bah = Fetch_Immediate()<<8;
+    effective_address = bah + bal + register_x;
+    local_data = read_byte(effective_address );
+    
+    if (  (SPEEDUP==0) && page_cross_check==1 && (  (0xFF00&effective_address) != (0xFF00&bah) ) ) {  
+        local_data = read_byte(effective_address ); 
+    }
+    return local_data;
+}
+
+uint8_t Fetch_Absolute_Y(uint8_t page_cross_check)  {
+    uint16_t bal, bah;
+    uint8_t  local_data;
+    
+    bal = Fetch_Immediate();
+    bah = Fetch_Immediate()<<8;
+    effective_address = bah + bal + register_y;
+    local_data = read_byte(effective_address );
+    
+    if ( (SPEEDUP==0)  && page_cross_check==1 && (  (0xFF00&effective_address) != (0xFF00&bah) ) ) {  
+        local_data = read_byte(effective_address ); 
+    } 
+    return local_data;
+}
+
+uint8_t Fetch_Indexed_Indirect_X()  { 
+    uint16_t bal;
+    uint16_t adl, adh;
+    uint8_t  local_data;
+    
+    bal = Fetch_Immediate() + register_x;
+    read_byte(bal);
+    adl = read_byte(0xFF&bal);
+    adh = read_byte(0xFF&(bal+1)) << 8;
+    effective_address = adh + adl ;
+    local_data = read_byte(effective_address);
+    return local_data;
+}
+
+uint8_t Fetch_Indexed_Indirect_Y(uint8_t page_cross_check)  {
+    uint16_t ial, bah, bal;
+    uint8_t  local_data;
+    
+    ial = Fetch_Immediate();
+    bal = read_byte(0xFF&ial);
+    bah = read_byte(0xFF&(ial+1)) << 8;
+    
+    effective_address = bah + bal + register_y;
+    local_data = read_byte(effective_address);
+    
+    if ( (SPEEDUP==0) && page_cross_check==1 && ((0xFF00&effective_address) != (0xFF00&bah)) ) {  
+        local_data = read_byte(effective_address); 
+    }
+    return local_data;
+}
+
+
+void Write_ZeroPage(uint8_t local_data)  {
+    effective_address = Fetch_Immediate();
+    write_byte(effective_address , local_data);
+    return;
+}
+
+void Write_Absolute(uint8_t local_data)  {
+    effective_address = Fetch_Immediate();
+    effective_address = (Fetch_Immediate() << 8) + effective_address;
+    write_byte(effective_address , local_data );
+    return;
+}
+
+void Write_ZeroPage_X(uint8_t local_data)  {
+    effective_address = Fetch_Immediate();
+    if (SPEEDUP==0) read_byte(effective_address);
+    write_byte( (0x00FF&(effective_address + register_x)) , local_data );
+    return;
+}
+
+void Write_ZeroPage_Y(uint8_t local_data)  {
+    effective_address = Fetch_Immediate();
+    if (SPEEDUP==0) read_byte(effective_address);
+    write_byte( (0x00FF&(effective_address + register_y)) , local_data );
+    return;
+}
+
+void Write_Absolute_X(uint8_t local_data)  {
+    uint16_t bal,bah;
+
+    bal = Fetch_Immediate();
+    bah = Fetch_Immediate()<<8;
+    effective_address = bal + bah + register_x; 
+    if (SPEEDUP==0) read_byte(effective_address);
+    write_byte(effective_address , local_data );  
+    return;
+}
+
+void Write_Absolute_Y(uint8_t local_data)  {
+    uint16_t bal,bah;
+
+    bal = Fetch_Immediate();
+    bah = Fetch_Immediate()<<8;
+    effective_address = bal + bah + register_y;
+    read_byte(effective_address);
+
+    if (SPEEDUP==0) {
+        if ( (0xFF00&effective_address) != (0xFF00&bah) ) { 
+        read_byte(effective_address);
+        }
+    }
+    write_byte(effective_address , local_data );  
+    return;
+}
+
+void Write_Indexed_Indirect_X(uint8_t local_data)  {
+    uint16_t bal;
+    uint16_t adl, adh;
+
+    bal = Fetch_Immediate();
+    read_byte(bal);
+    adl = read_byte(0xFF&(bal+register_x));
+    adh = read_byte(0xFF&(bal+register_x+1)) << 8;
+    effective_address = adh + adl;
+    write_byte(effective_address , local_data );
+    return;
+}
+
+void Write_Indexed_Indirect_Y(uint8_t local_data)  {  
+    uint16_t ial;
+    uint16_t bal, bah;
+
+    ial = Fetch_Immediate();
+    bal = read_byte(ial);
+    bah = read_byte(ial+1)<<8;
+    effective_address = bah + bal + register_y;
+    if (SPEEDUP==0) read_byte(effective_address);
+    write_byte(effective_address , local_data );
+    return;
+}
+
+void Double_WriteBack(uint8_t local_data)  {  
+    write_byte(effective_address , local_data);
+    if (SPEEDUP==0)  write_byte(effective_address , local_data);
+    return;
+}
+
+
+// -------------------------------------------------
+// Reset sequence for the 6502
+// -------------------------------------------------
+void reset_sequence() {
+    uint16_t temp1, temp2;
+       
+    while (digitalReadFast(PIN_RESET)!=0) {}                        // Stay here until RESET deasserts
+            
+                
+    digitalWriteFast(PIN_RDWR_n,  0x1);         
+    digitalWriteFast(PIN_DATAOUT_OE_n,  0x1 );  
+    
+    digitalWriteFast(PIN_P0, 0x1 ); 
+    digitalWriteFast(PIN_P1, 0x1 ); 
+    digitalWriteFast(PIN_P2, 0x1 );           
+            
+            
+    temp1 = read_byte(register_pc);                                 // Address ??
+    temp1 = read_byte(register_pc+1);                               // Address ?? + 1
+    temp1 = read_byte(register_sp_fixed);                           // Address SP
+    temp1 = read_byte(register_sp_fixed-1);                         // Address SP - 1
+    temp1 = read_byte(register_sp_fixed-2);                         // Address SP - 2
+                
+    temp1 = read_byte(0xFFFC);                                      // Fetch Vector PCL
+    temp2 = read_byte(0xFFFD);                                      // Fetch Vector PCH
+                
+    register_flags = 0x34;                                          // Set the I and B flags
+            
+    register_pc = (temp2<<8) | temp1;    
+    assert_sync=1;  
+    start_read(register_pc);                                        // Fetch first opcode at vector PCH,PCL
+    
+    
+    return;
+}
+
+
+// -------------------------------------------------
+// NMI Interrupt Processing
+// -------------------------------------------------
+void nmi_handler() {
+    uint16_t temp1, temp2;
+    
+    wait_for_CLK_rising_edge();                                     // Begin processing on next CLK edge
+    
+    register_flags = register_flags | 0x20;                         // Set the flag[5]          
+    register_flags = register_flags & 0xEF;                         // Clear the B flag     
+    
+    read_byte(register_pc+1);                                       // Fetch PC+1 (Discard)
+    push(register_pc>>8);                                           // Push PCH
+    push(register_pc);                                              // Push PCL
+    push(register_flags);                                           // Push P
+    temp1 = read_byte(0xFFFA);                                      // Fetch Vector PCL
+    temp2 = read_byte(0xFFFB);                                      // Fetch Vector PCH
+                
+    register_flags = register_flags | 0x34;                         // Set the I flag and restore the B flag
+
+    register_pc = (temp2<<8) | temp1;           
+    assert_sync=1;
+    start_read(register_pc);                                        // Fetch first opcode at vector PCH,PCL
+    
+    return;
+}
+    
+
+// -------------------------------------------------
+// BRK & IRQ Interrupt Processing
+// -------------------------------------------------
+void irq_handler(uint8_t opcode_is_brk) {
+    uint16_t temp1, temp2;
+    
+    wait_for_CLK_rising_edge();                                     // Begin processing on next CLK edge
+                        
+    register_flags = register_flags | 0x20;                         // Set the flag[5]          
+    if (opcode_is_brk==1) register_flags = register_flags | 0x10;   // Set the B flag
+    else                  register_flags = register_flags & 0xEF;   // Clear the B flag
+    
+    read_byte(register_pc+1);                                       // Fetch PC+1 (Discard)
+    push(register_pc>>8);                                           // Push PCH
+    push(register_pc);                                              // Push PCL
+    push(register_flags);                                           // Push P
+    temp1 = read_byte(0xFFFE);                                      // Fetch Vector PCL
+    temp2 = read_byte(0xFFFF);                                      // Fetch Vector PCH
+                
+    register_flags = register_flags | 0x34;                         // Set the I flag and restore the B flag
+                
+    register_pc = (temp2<<8) | temp1;           
+    assert_sync=1;
+    start_read(register_pc);                                        // Fetch first opcode at vector PCH,PCL
+    
+    return;
+}
+    
+
+// -------------------------------------------------
+//
+//               6502 Opcodes
+//
+// -------------------------------------------------
+
+// -------------------------------------------------
+// 0x0A - ASL A - Arithmetic Shift Left - Accumulator
+// -------------------------------------------------
+void opcode_0x0A() {
+    
+    read_byte(register_pc);        
+    Begin_Fetch_Next_Opcode();
+     
+    if (0x80&register_a)   register_flags = register_flags | 0x01;              // Set the C flag
+    else                   register_flags = register_flags & 0xFE;              // Clear the C flag
+    
+    register_a = register_a << 1;
+    
+    Calc_Flags_NEGATIVE_ZERO(register_a);
+    return;
+}
+
+
+
+// -------------------------------------------------
+// 0x4A - LSR A - Logical Shift Right - Accumulator
+// -------------------------------------------------
+void opcode_0x4A() {
+    
+    read_byte(register_pc);        
+    Begin_Fetch_Next_Opcode();
+    
+    if (0x01&register_a)   register_flags = register_flags | 0x01;              // Set the C flag
+    else                   register_flags = register_flags & 0xFE;              // Clear the C flag
+    
+    register_a = register_a >> 1;
+
+    Calc_Flags_NEGATIVE_ZERO(register_a);
+    return;
+}
+
+// -------------------------------------------------
+// 0x6A - ROR A - Rotate Right - Accumulator
+// -------------------------------------------------
+void opcode_0x6A() {
+
+  uint8_t old_carry_flag=0;
+    
+    read_byte(register_pc);        
+    Begin_Fetch_Next_Opcode();
+    
+    old_carry_flag = register_flags << 7;                                       // Shift the old carry flag to bit[8] to be rotated in
+    
+    if (0x01&register_a)   register_flags = register_flags | 0x01;              // Set the C flag
+    else                   register_flags = register_flags & 0xFE;              // Clear the C flag
+    
+    register_a = ( old_carry_flag | (register_a>>1) );
+
+    Calc_Flags_NEGATIVE_ZERO(register_a);
+    return;
+}
+
+
+// -------------------------------------------------
+// 0x2A - ROL A - Rotate Left - Accumulator
+// -------------------------------------------------
+void opcode_0x2A() {
+
+  uint8_t old_carry_flag=0;
+
+    read_byte(register_pc);        
+    Begin_Fetch_Next_Opcode();
+    
+    old_carry_flag = 0x1 & register_flags;                                      // Store the old carry flag to be rotated in
+    
+    
+    if (0x80&register_a)   register_flags = register_flags | 0x01;              // Set the C flag
+    else                   register_flags = register_flags & 0xFE;              // Clear the C flag
+    
+    register_a = (register_a<<1) | old_carry_flag;
+
+    Calc_Flags_NEGATIVE_ZERO(register_a);
+    return;
+}
+
+
+// -------------------------------------------------
+// ADC 
+// -------------------------------------------------
+void Calculate_ADC(uint16_t local_data)  { 
+    uint16_t total=0;
+    uint16_t bcd_low=0;
+    uint16_t bcd_high=0;
+    uint16_t bcd_total=0;
+    uint8_t operand0=0;
+    uint8_t operand1=0;
+    uint8_t result=0;
+    uint8_t low_carry=0;
+    uint8_t high_carry=0;
+    
+    Begin_Fetch_Next_Opcode();
+    
+    if ((flag_d)==1) {  
+        bcd_low = (0x0F&register_a) + (0x0F&local_data) + (flag_c) ;    
+        if (bcd_low>0x9) { low_carry=0x10; bcd_low = bcd_low - 0xA ; } 
+            
+        bcd_high = (0xF0&register_a) + (0xF0&local_data) + low_carry;   
+        if (bcd_high>0x90) { high_carry=1;  bcd_high = bcd_high - 0xA0 ; } 
+        
+        register_flags = register_flags & 0xFE;              // Clear the C flag
+        if ((0x00FF&bcd_total) > 0x09) { bcd_total=bcd_total+0x010; bcd_total=bcd_total-0x0A; }    
+
+        if (high_carry==1) { bcd_total=bcd_total-0xA0; register_flags = register_flags | 0x01;  }           // Set the C flag
+        else                                           register_flags = register_flags & 0xFE;              // Clear the C flag     
+        
+        total = (0xFF & (bcd_low + bcd_high));
+    }
+    
+    else {
+        total =  register_a + local_data + (flag_c);
+    
+        if (total>255)    register_flags = register_flags | 0x01;              // Set the C flag
+        else              register_flags = register_flags & 0xFE;              // Clear the C flag
+    }
+    
+    
+    operand0 = (register_a & 0x80);  
+    operand1 = (local_data & 0x80);  
+    result   = (total      & 0x80); 
+
+    if      (operand0==0 && operand1==0 && result!=0)  register_flags = register_flags | 0x40;              // Set the V flag
+    else if (operand0!=0 && operand1!=0 && result==0)  register_flags = register_flags | 0x40;  
+    else                                               register_flags = register_flags & 0xBF;              // Clear the V flag
+    
+    register_a = (0xFF & total);
+    Calc_Flags_NEGATIVE_ZERO(register_a);
+    
+    return;
+}
+void opcode_0x69() { Calculate_ADC(Fetch_Immediate());             return;  }  // 0x69 - ADC - Immediate - Binary
+void opcode_0x65() { Calculate_ADC(Fetch_ZeroPage());              return;  }  // 0x65 - ADC - ZeroPage
+void opcode_0x75() { Calculate_ADC(Fetch_ZeroPage_X());            return;  }  // 0x75 - ADC - ZeroPage , X
+void opcode_0x6D() { Calculate_ADC(Fetch_Absolute());              return;  }  // 0x6D - ADC - Absolute
+void opcode_0x7D() { Calculate_ADC(Fetch_Absolute_X(1));           return;  }  // 0x7D - ADC - Absolute , X
+void opcode_0x79() { Calculate_ADC(Fetch_Absolute_Y(1));           return;  }  // 0x79 - ADC - Absolute , Y
+void opcode_0x61() { Calculate_ADC(Fetch_Indexed_Indirect_X());    return;  }  // 0x61 - ADC - Indexed Indirect X
+void opcode_0x71() { Calculate_ADC(Fetch_Indexed_Indirect_Y(1));   return;  }  // 0x71 - ADC - Indirect Indexed  Y
+
+
+
+// -------------------------------------------------
+// SBC 
+// -------------------------------------------------
+void Calculate_SBC(uint16_t local_data)  { 
+    uint16_t total=0;
+    uint16_t bcd_low=0;
+    uint16_t bcd_high=0;
+    uint16_t bcd_total=0;
+    int16_t signed_total=0;
+    uint8_t operand0=0;
+    uint8_t operand1=0;
+    uint8_t result=0;
+    uint8_t flag_c_invert=0;
+    uint8_t low_carry=0;
+    uint8_t high_carry=0;
+    
+    Begin_Fetch_Next_Opcode();
+    
+    if (flag_c!=0) flag_c_invert=0; else flag_c_invert=1;
+    
+    if ((flag_d)==1) {  
+        bcd_low = (0x0F&register_a) - (0x0F&local_data) - flag_c_invert ;   
+        if (bcd_low>0x9) { low_carry=0x10; bcd_low = bcd_low + 0xA ; } 
+            
+        bcd_high = (0xF0&register_a) - (0xF0&local_data) - low_carry;    
+        if (bcd_high>0x90) { high_carry=1;  bcd_high = bcd_high + 0xA0 ; } 
+        
+        register_flags = register_flags & 0xFE;              // Clear the C flag
+        if ((0x00FF&bcd_total) > 0x09) { bcd_total=bcd_total+0x010; bcd_total=bcd_total-0x0A; }    
+
+        if (high_carry==0) { bcd_total=bcd_total-0xA0; register_flags = register_flags | 0x01;  }           // Set the C flag
+        else                                           register_flags = register_flags & 0xFE;              // Clear the C flag     
+        
+        total = (0xFF & (bcd_low + bcd_high));
+    }
+    
+    else {  
+
+    total =  register_a - local_data - flag_c_invert;
+    signed_total = (int16_t)register_a - (int16_t)(local_data ) - flag_c_invert;
+
+    
+    if (signed_total>=0)    register_flags = register_flags | 0x01;                                         // Set the C flag
+    else                    register_flags = register_flags & 0xFE;                                         // Clear the C flag  
+    }
+    
+    
+    operand0 = (register_a & 0x80);  
+    operand1 = (local_data & 0x80);  
+    result   = (total      & 0x80); 
+
+    if      (operand0==0 && operand1!=0 && result!=0)  register_flags = register_flags | 0x40;              // Set the V flag
+    else if (operand0!=0 && operand1==0 && result==0)  register_flags = register_flags | 0x40;  
+    else                                               register_flags = register_flags & 0xBF;              // Clear the V flag
+
+
+    register_a = (0xFF & total);
+    Calc_Flags_NEGATIVE_ZERO(register_a);
+    
+    return;
+}
+void opcode_0xE9() { Calculate_SBC(Fetch_Immediate());             return;  }  // 0xE9 - SBC - Immediate
+void opcode_0xE5() { Calculate_SBC(Fetch_ZeroPage());              return;  }  // 0xE5 - SBC - ZeroPage
+void opcode_0xF5() { Calculate_SBC(Fetch_ZeroPage_X());            return;  }  // 0xF5 - SBC - ZeroPage , X
+void opcode_0xED() { Calculate_SBC(Fetch_Absolute());              return;  }  // 0xED - SBC - Absolute
+void opcode_0xFD() { Calculate_SBC(Fetch_Absolute_X(1));           return;  }  // 0xFD - SBC - Absolute , X
+void opcode_0xF9() { Calculate_SBC(Fetch_Absolute_Y(1));           return;  }  // 0xF9 - SBC - Absolute , Y
+void opcode_0xE1() { Calculate_SBC(Fetch_Indexed_Indirect_X());    return;  }  // 0xE1 - SBC - Indexed Indirect X
+void opcode_0xF1() { Calculate_SBC(Fetch_Indexed_Indirect_Y(1));   return;  }  // 0xF1 - SBC - Indirect Indexed  Y
+
+
+// -------------------------------------------------
+// Flag set/resets and NOP
+// -------------------------------------------------
+void opcode_0xEA() {  read_byte(register_pc+1);  Begin_Fetch_Next_Opcode();                                        return;  }  // 0xEA - NOP   
+void opcode_0x18() {  read_byte(register_pc+1);  Begin_Fetch_Next_Opcode();  register_flags=register_flags&0xFE;   return;  }  // 0x18 - CLC - Clear Carry Flag  
+void opcode_0xD8() {  read_byte(register_pc+1);  Begin_Fetch_Next_Opcode();  register_flags=register_flags&0xF7;   return;  }  // 0xD8 - CLD - Clear Decimal Mode  
+void opcode_0x58() {  read_byte(register_pc+1);  Begin_Fetch_Next_Opcode();  register_flags=register_flags&0xFB;   return;  }  // 0x58 - CLI - Clear Interrupt Flag  
+void opcode_0xB8() {  read_byte(register_pc+1);  Begin_Fetch_Next_Opcode();  register_flags=register_flags&0xBF;   return;  }  // 0xB8 - CLV - Clear Overflow Flag  
+void opcode_0x38() {  read_byte(register_pc+1);  Begin_Fetch_Next_Opcode();  register_flags=register_flags|0x01;   return;  }  // 0x38 - SEC - Set Carry Flag  
+void opcode_0x78() {  read_byte(register_pc+1);  Begin_Fetch_Next_Opcode();  register_flags=register_flags|0x04;   return;  }  // 0x78 - SEI - Set Interrupt Flag  
+void opcode_0xF8() {  read_byte(register_pc+1);  Begin_Fetch_Next_Opcode();  register_flags=register_flags|0x08;   return;  }  // 0xF8 - SED - Set Decimal Mode  
+
+
+// -------------------------------------------------
+// Increment/Decrements
+// -------------------------------------------------
+void opcode_0xCA() {  read_byte(register_pc+1);  Begin_Fetch_Next_Opcode();  register_x=register_x-1;   Calc_Flags_NEGATIVE_ZERO(register_x); return;  }  // 0xCA - DEX - Decrement X  
+void opcode_0x88() {  read_byte(register_pc+1);  Begin_Fetch_Next_Opcode();  register_y=register_y-1;   Calc_Flags_NEGATIVE_ZERO(register_y); return;  }  // 0x88 - DEY - Decrement Y  
+void opcode_0xE8() {  read_byte(register_pc+1);  Begin_Fetch_Next_Opcode();  register_x=register_x+1;   Calc_Flags_NEGATIVE_ZERO(register_x); return;  }  // 0xE8 - INX - Increment X  
+void opcode_0xC8() {  read_byte(register_pc+1);  Begin_Fetch_Next_Opcode();  register_y=register_y+1;   Calc_Flags_NEGATIVE_ZERO(register_y); return;  }  // 0xC8 - INY - Increment Y  
+
+
+// -------------------------------------------------
+// Transfers
+// -------------------------------------------------
+void opcode_0xAA() {  read_byte(register_pc+1);  Begin_Fetch_Next_Opcode();  register_x=register_a;   Calc_Flags_NEGATIVE_ZERO(register_x); return;  }  // 0xAA - TAX - Transfer Accumulator to X 
+void opcode_0xA8() {  read_byte(register_pc+1);  Begin_Fetch_Next_Opcode();  register_y=register_a;   Calc_Flags_NEGATIVE_ZERO(register_y); return;  }  // 0xA8 - TAY - Transfer Accumulator to Y
+void opcode_0xBA() {  read_byte(register_pc+1);  Begin_Fetch_Next_Opcode();  register_x=register_sp;  Calc_Flags_NEGATIVE_ZERO(register_x); return;  }  // 0xBA - TSX - Transfer Stack Pointer to X
+void opcode_0x8A() {  read_byte(register_pc+1);  Begin_Fetch_Next_Opcode();  register_a=register_x;   Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0x8A - TXA - Transfer X to Accumulator
+void opcode_0x9A() {  read_byte(register_pc+1);  Begin_Fetch_Next_Opcode();  register_sp=register_x;                                        return;  }  // 0x9A - TXS - Transfer X to Stack Pointer
+void opcode_0x98() {  read_byte(register_pc+1);  Begin_Fetch_Next_Opcode();  register_a=register_y;   Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0x98 - TYA - Transfer Y to Accumulator
+
+
+// -------------------------------------------------
+// PUSH/POP Flags and Accumulator 
+// -------------------------------------------------
+void opcode_0x08() {  read_byte(register_pc+1);  push(register_flags|0x30);                                                              Begin_Fetch_Next_Opcode();  return;  }  // 0x08 - PHP - Push Flags to Stack
+void opcode_0x48() {  read_byte(register_pc+1);  push(register_a);                                                                       Begin_Fetch_Next_Opcode();  return;  }  // 0x48 - PHA - Push Accumulator to the stack
+void opcode_0x28() {  read_byte(register_pc+1);  read_byte(register_sp_fixed);  register_flags=(pop()|0x30);                             Begin_Fetch_Next_Opcode();  return;  }  // 0x28 - PLP - Pop Flags from Stack
+void opcode_0x68() {  read_byte(register_pc+1);  read_byte(register_sp_fixed);  register_a=pop();  Calc_Flags_NEGATIVE_ZERO(register_a); Begin_Fetch_Next_Opcode();  return;  }  // 0x68 - PLA - Pop Accumulator from Stack
+
+
+// -------------------------------------------------
+// AND
+// -------------------------------------------------
+void opcode_0x29() { register_a=register_a&(Fetch_Immediate());           Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0x29 - AND - Immediate
+void opcode_0x25() { register_a=register_a&(Fetch_ZeroPage());            Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0x25 - AND - ZeroPage
+void opcode_0x35() { register_a=register_a&(Fetch_ZeroPage_X());          Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0x35 - AND - ZeroPage , X
+void opcode_0x2D() { register_a=register_a&(Fetch_Absolute());            Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0x2D - AND - Absolute
+void opcode_0x3D() { register_a=register_a&(Fetch_Absolute_X(1));         Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0x3D - AND - Absolute , X
+void opcode_0x39() { register_a=register_a&(Fetch_Absolute_Y(1));         Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0x19 - OR - Absolute , Y
+void opcode_0x21() { register_a=register_a&(Fetch_Indexed_Indirect_X());  Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0x21 - AND - Indexed Indirect X
+void opcode_0x31() { register_a=register_a&(Fetch_Indexed_Indirect_Y(1)); Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0x31 - AND - Indirect Indexed  Y
+
+
+// -------------------------------------------------
+// ORA
+// -------------------------------------------------
+void opcode_0x09() { register_a=register_a|(Fetch_Immediate());            Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a);  return;  }  // 0x09 - OR - Immediate
+void opcode_0x05() { register_a=register_a|(Fetch_ZeroPage());             Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a);  return;  }  // 0x05 - OR - ZeroPage
+void opcode_0x15() { register_a=register_a|(Fetch_ZeroPage_X());           Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a);  return;  }  // 0x15 - OR - ZeroPage , X
+void opcode_0x0D() { register_a=register_a|(Fetch_Absolute());             Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a);  return;  }  // 0x0D - OR - Absolute
+void opcode_0x1D() { register_a=register_a|(Fetch_Absolute_X(1));          Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a);  return;  }  // 0x1D - OR - Absolute , X
+void opcode_0x19() { register_a=register_a|(Fetch_Absolute_Y(1));          Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a);  return;  }  // 0x19 - OR - Absolute , Y
+void opcode_0x01() { register_a=register_a|(Fetch_Indexed_Indirect_X());   Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a);  return;  }  // 0x01 - OR - Indexed Indirect X
+void opcode_0x11() { register_a=register_a|(Fetch_Indexed_Indirect_Y(1));  Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a);  return;  }  // 0x11 - OR - Indirect Indexed  Y
+
+
+// -------------------------------------------------
+// EOR
+// -------------------------------------------------
+void opcode_0x49() { register_a=register_a^(Fetch_Immediate());            Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0x49 - EOR - Immediate
+void opcode_0x45() { register_a=register_a^(Fetch_ZeroPage());             Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0x45 - EOR - ZeroPage
+void opcode_0x55() { register_a=register_a^(Fetch_ZeroPage_X());           Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0x55 - EOR - ZeroPage , X
+void opcode_0x4D() { register_a=register_a^(Fetch_Absolute());             Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0x4D - EOR - Absolute
+void opcode_0x5D() { register_a=register_a^(Fetch_Absolute_X(1));          Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0x5D - EOR - Absolute , X
+void opcode_0x59() { register_a=register_a^(Fetch_Absolute_Y(1));          Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0x59 - EOR - Absolute , Y
+void opcode_0x41() { register_a=register_a^(Fetch_Indexed_Indirect_X());   Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0x41 - EOR - Indexed Indirect X
+void opcode_0x51() { register_a=register_a^(Fetch_Indexed_Indirect_Y(1));  Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0x51 - EOR - Indirect Indexed  Y
+
+
+// -------------------------------------------------
+// LDA
+// -------------------------------------------------
+void opcode_0xA9() { register_a=Fetch_Immediate();            Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0xA9 - LDA - Immediate
+void opcode_0xA5() { register_a=Fetch_ZeroPage();             Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0xA5 - LDA - ZeroPage
+void opcode_0xB5() { register_a=Fetch_ZeroPage_X();           Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0xB5 - LDA - ZeroPage , X
+void opcode_0xAD() { register_a=Fetch_Absolute();             Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0xAD - LDA - Absolute
+void opcode_0xBD() { register_a=Fetch_Absolute_X(1);          Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0xBD - LDA - Absolute , X
+void opcode_0xB9() { register_a=Fetch_Absolute_Y(1);          Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0xB9 - LDA - Absolute , Y
+void opcode_0xA1() { register_a=Fetch_Indexed_Indirect_X();   Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0xA1 - LDA - Indexed Indirect X
+void opcode_0xB1() { register_a=Fetch_Indexed_Indirect_Y(1);  Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0xB1 - LDA - Indirect Indexed  Y
+
+
+// -------------------------------------------------
+// LDX
+// -------------------------------------------------
+void opcode_0xA2() { register_x=Fetch_Immediate();            Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_x); return;  }  // 0xA2 - LDX - Immediate
+void opcode_0xA6() { register_x=Fetch_ZeroPage();             Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_x); return;  }  // 0xA6 - LDX - ZeroPage
+void opcode_0xB6() { register_x=Fetch_ZeroPage_Y();           Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_x); return;  }  // 0xB6 - LDX - ZeroPage , Y
+void opcode_0xAE() { register_x=Fetch_Absolute();             Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_x); return;  }  // 0xAE - LDX - Absolute
+void opcode_0xBE() { register_x=Fetch_Absolute_Y(1);          Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_x); return;  }  // 0xBE - LDX - Absolute , Y
+                                                              
+                                                              
+// -------------------------------------------------          
+// LDY                                                        
+// -------------------------------------------------          
+void opcode_0xA0() { register_y=Fetch_Immediate();             Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_y);return;  }  // 0xA0 - LDY - Immediate
+void opcode_0xA4() { register_y=Fetch_ZeroPage();              Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_y);return;  }  // 0xA4 - LDY - ZeroPage
+void opcode_0xB4() { register_y=Fetch_ZeroPage_X();            Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_y);return;  }  // 0xB4 - LDY - ZeroPage , X
+void opcode_0xAC() { register_y=Fetch_Absolute();              Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_y);return;  }  // 0xAC - LDY - Absolute
+void opcode_0xBC() { register_y=Fetch_Absolute_X(1);           Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_y);return;  }  // 0xBC - LDY - Absolute , X
+
+
+// -------------------------------------------------
+// BIT 
+// -------------------------------------------------
+void Calculate_BIT(uint8_t local_data)  {
+    uint8_t temp=0;
+    
+    Begin_Fetch_Next_Opcode();
+    
+    register_flags = (register_flags & 0x3F) | (local_data & 0xC0);             // Copy fetched memory[7:6] to C,V flags
+    
+    temp = local_data & register_a;
+    if (temp==0)           register_flags = register_flags | 0x02;              // Set the Z flag
+    else                   register_flags = register_flags & 0xFD;              // Clear the Z flag 
+    
+    
+    return;
+}
+void opcode_0x24() { Calculate_BIT(Fetch_ZeroPage());    return;  }             // 0x24 - BIT - ZeroPage
+void opcode_0x2C() { Calculate_BIT(Fetch_Absolute());    return;  }             // 0x2C - BIT - Absolute
+
+
+// -------------------------------------------------
+// CMP 
+// -------------------------------------------------
+void Calculate_CMP(uint8_t local_data)  {
+    int16_t temp=0;
+    
+    Begin_Fetch_Next_Opcode();
+    
+    temp = register_a - local_data;
+    
+
+    if (register_a >= local_data) register_flags = register_flags | 0x01;       // Set the C flag
+    else                          register_flags = register_flags & 0xFE;       // Clear the C flag  
+    
+    Calc_Flags_NEGATIVE_ZERO(temp);
+    return;
+}
+void opcode_0xC9() {  Calculate_CMP(Fetch_Immediate());             return;  }  // 0xC9 - CMP - Immediate
+void opcode_0xC5() {  Calculate_CMP(Fetch_ZeroPage());              return;  }  // 0xC5 - CMP - ZeroPage
+void opcode_0xD5() {  Calculate_CMP(Fetch_ZeroPage_X());            return;  }  // 0xD5 - CMP - ZeroPage , X
+void opcode_0xCD() {  Calculate_CMP(Fetch_Absolute());              return;  }  // 0xCD - CMP - Absolute
+void opcode_0xDD() {  Calculate_CMP(Fetch_Absolute_X(1));           return;  }  // 0xDD - CMP - Absolute , X
+void opcode_0xD9() {  Calculate_CMP(Fetch_Absolute_Y(1));           return;  }  // 0xD9 - CMP - Absolute , Y
+void opcode_0xC1() {  Calculate_CMP(Fetch_Indexed_Indirect_X());    return;  }  // 0xC1 - CMP - Indexed Indirect X
+void opcode_0xD1() {  Calculate_CMP(Fetch_Indexed_Indirect_Y(1));   return;  }  // 0xD1 - CMP - Indirect Indexed  Y
+
+
+// -------------------------------------------------
+// CPX 
+// -------------------------------------------------
+void Calculate_CPX(uint8_t local_data)  {
+    uint16_t temp=0;
+    
+    Begin_Fetch_Next_Opcode();
+    
+    temp = register_x - local_data;
+
+    if (register_x >= local_data) register_flags = register_flags | 0x01;       // Set the C flag
+    else                          register_flags = register_flags & 0xFE;       // Clear the C flag  
+    
+    Calc_Flags_NEGATIVE_ZERO(temp);
+    return;
+}
+void opcode_0xE0() {  Calculate_CPX(Fetch_Immediate());   return;  }  // 0xE0 - CPX - Immediate
+void opcode_0xE4() {  Calculate_CPX(Fetch_ZeroPage());    return;  }  // 0xE4 - CPX - ZeroPage
+void opcode_0xEC() {  Calculate_CPX(Fetch_Absolute());    return;  }  // 0xEC - CPX - Absolute
+
+
+// -------------------------------------------------
+// CPY
+// -------------------------------------------------
+void Calculate_CPY(uint8_t local_data)  {
+    uint16_t temp=0;
+    
+    Begin_Fetch_Next_Opcode();
+    
+    temp = register_y - local_data; 
+
+    if (register_y >= local_data) register_flags = register_flags | 0x01;       // Set the C flag
+    else                          register_flags = register_flags & 0xFE;       // Clear the C flag  
+    
+    Calc_Flags_NEGATIVE_ZERO(temp);
+    return;
+}
+void opcode_0xC0() {  Calculate_CPY(Fetch_Immediate());    return;  }  // 0xC0 - CPY - Immediate
+void opcode_0xC4() {  Calculate_CPY(Fetch_ZeroPage());     return;  }  // 0xC4 - CPY - ZeroPage
+void opcode_0xCC() {  Calculate_CPY(Fetch_Absolute());     return;  }  // 0xCC - CPY - Absolute
+
+
+// -------------------------------------------------
+// Store Operations
+// -------------------------------------------------
+void opcode_0x85() {  Write_ZeroPage(register_a);            Begin_Fetch_Next_Opcode();  return;  }  // 0x85 - STA - ZeroPage
+void opcode_0x8D() {  Write_Absolute(register_a);            Begin_Fetch_Next_Opcode();  return;  }  // 0x8D - STA - Absolute
+void opcode_0x95() {  Write_ZeroPage_X(register_a);          Begin_Fetch_Next_Opcode();  return;  }  // 0x95 - STA - ZeroPage , X
+void opcode_0x9D() {  Write_Absolute_X(register_a);          Begin_Fetch_Next_Opcode();  return;  }  // 0x9D - STA - Absolute , X
+void opcode_0x99() {  Write_Absolute_Y(register_a);          Begin_Fetch_Next_Opcode();  return;  }  // 0x99 - STA - Absolute , Y
+void opcode_0x81() {  Write_Indexed_Indirect_X(register_a);  Begin_Fetch_Next_Opcode();  return;  }  // 0x81 - STA - Indexed Indirect X
+void opcode_0x91() {  Write_Indexed_Indirect_Y(register_a);  Begin_Fetch_Next_Opcode();  return;  }  // 0x91 - STA - Indirect Indexed  Y
+void opcode_0x86() {  Write_ZeroPage(register_x);            Begin_Fetch_Next_Opcode();  return;  }  // 0x86 - STX - ZeroPage
+void opcode_0x96() {  Write_ZeroPage_Y(register_x);          Begin_Fetch_Next_Opcode();  return;  }  // 0x96 - STX - ZeroPage , Y
+void opcode_0x8E() {  Write_Absolute(register_x);            Begin_Fetch_Next_Opcode();  return;  }  // 0x8E - STX - Absolute
+void opcode_0x84() {  Write_ZeroPage(register_y);            Begin_Fetch_Next_Opcode();  return;  }  // 0x84 - STY - ZeroPage
+void opcode_0x94() {  Write_ZeroPage_X(register_y);          Begin_Fetch_Next_Opcode();  return;  }  // 0x94 - STY - ZeroPage , X
+void opcode_0x8C() {  Write_Absolute(register_y);            Begin_Fetch_Next_Opcode();  return;  }  // 0x8C - STY - Absolute
+
+
+// -------------------------------------------------
+// ASL - Arithmetic Shift Left - Memory
+// -------------------------------------------------
+uint8_t Calculate_ASL(uint8_t local_data) {
+
+    if ((0x80&local_data)==0x80)   register_flags = register_flags | 0x01;              // Set the C flag
+    else                           register_flags = register_flags & 0xFE;              // Clear the C flag
+    
+    local_data = ((local_data << 1) & 0xFE);
+
+    Calc_Flags_NEGATIVE_ZERO(local_data);
+    return local_data;
+}
+
+
+// -------------------------------------------------
+// ASL - Read-modify-write Operations
+// -------------------------------------------------
+void opcode_0x06() {  Double_WriteBack(Calculate_ASL(Fetch_ZeroPage()));     Begin_Fetch_Next_Opcode();  return;  }  // 0x06 - ASL  - Arithmetic Shift Left - ZeroPage
+void opcode_0x16() {  Double_WriteBack(Calculate_ASL(Fetch_ZeroPage_X()));   Begin_Fetch_Next_Opcode();  return;  }  // 0x16 - ASL  - Arithmetic Shift Left - ZeroPage , X
+void opcode_0x0E() {  Double_WriteBack(Calculate_ASL(Fetch_Absolute()));     Begin_Fetch_Next_Opcode();  return;  }  // 0x0E - ASL  - Arithmetic Shift Left - Absolute
+void opcode_0x1E() {  Double_WriteBack(Calculate_ASL(Fetch_Absolute_X(0)));  Begin_Fetch_Next_Opcode();  return;  }  // 0x1E - ASL  - Arithmetic Shift Left - Absolute , X
+
+
+// -------------------------------------------------
+// INC - Memory
+// -------------------------------------------------
+uint8_t Calculate_INC(uint8_t local_data) {
+
+    local_data = local_data + 1;
+    global_temp = local_data;
+    Calc_Flags_NEGATIVE_ZERO(local_data);
+    return local_data;
+}
+
+void opcode_0xE6() {  Double_WriteBack(Calculate_INC(Fetch_ZeroPage()));     Begin_Fetch_Next_Opcode();  return;  }  // 0xE6 - INC - ZeroPage
+void opcode_0xF6() {  Double_WriteBack(Calculate_INC(Fetch_ZeroPage_X()));   Begin_Fetch_Next_Opcode();  return;  }  // 0xF6 - INC - ZeroPage , X
+void opcode_0xEE() {  Double_WriteBack(Calculate_INC(Fetch_Absolute()));     Begin_Fetch_Next_Opcode();  return;  }  // 0xEE - INC - Absolute
+void opcode_0xFE() {  Double_WriteBack(Calculate_INC(Fetch_Absolute_X(0)));  Begin_Fetch_Next_Opcode();  return;  }  // 0xFE - INC - Absolute , X
+
+
+// -------------------------------------------------
+// DEC - Memory
+// -------------------------------------------------
+uint8_t Calculate_DEC(uint8_t local_data) {
+
+    local_data = local_data - 1;
+    global_temp = local_data;
+    Calc_Flags_NEGATIVE_ZERO(local_data);
+    return local_data;
+}
+
+void opcode_0xC6() {  Double_WriteBack(Calculate_DEC(Fetch_ZeroPage()));     Begin_Fetch_Next_Opcode();  return;  }  // 0xC6 - DEC - ZeroPage
+void opcode_0xD6() {  Double_WriteBack(Calculate_DEC(Fetch_ZeroPage_X()));   Begin_Fetch_Next_Opcode();  return;  }  // 0xD6 - DEC - ZeroPage , X
+void opcode_0xCE() {  Double_WriteBack(Calculate_DEC(Fetch_Absolute()));     Begin_Fetch_Next_Opcode();  return;  }  // 0xCE - DEC - Absolute
+void opcode_0xDE() {  Double_WriteBack(Calculate_DEC(Fetch_Absolute_X(0)));  Begin_Fetch_Next_Opcode();  return;  }  // 0xDE - DEC - Absolute , X
+
+
+// -------------------------------------------------
+// LSR - Memory
+// -------------------------------------------------
+uint8_t Calculate_LSR(uint8_t local_data) {
+
+    if ((0x01&local_data)==0x01)   register_flags = register_flags | 0x01;              // Set the C flag
+    else                           register_flags = register_flags & 0xFE;              // Clear the C flag
+      
+    local_data = (0x7F& (local_data >> 1));  
+
+
+    Calc_Flags_NEGATIVE_ZERO(local_data);
+    return local_data;
+}
+void opcode_0x46() {  Double_WriteBack(Calculate_LSR(Fetch_ZeroPage()));     Begin_Fetch_Next_Opcode();  return;  }  // 0x46 - LSR - Logical Shift Right - ZeroPage
+void opcode_0x56() {  Double_WriteBack(Calculate_LSR(Fetch_ZeroPage_X()));   Begin_Fetch_Next_Opcode();  return;  }  // 0x56 - LSR - Logical Shift Right - ZeroPage , X
+void opcode_0x4E() {  Double_WriteBack(Calculate_LSR(Fetch_Absolute()));     Begin_Fetch_Next_Opcode();  return;  }  // 0x4E - LSR - Logical Shift Right - Absolute
+void opcode_0x5E() {  Double_WriteBack(Calculate_LSR(Fetch_Absolute_X(0)));  Begin_Fetch_Next_Opcode();  return;  }  // 0x5E - LSR - Logical Shift Right - Absolute , X
+
+
+// -------------------------------------------------
+// ROR - Memory
+// -------------------------------------------------
+uint8_t Calculate_ROR(uint8_t local_data) {
+
+  uint8_t old_carry_flag=0;
+  
+
+    old_carry_flag = register_flags << 7;                                       // Shift the old carry flag to bit[8] to be rotated in
+    
+    if ((0x01&local_data)==0x01)   register_flags = register_flags | 0x01;              // Set the C flag
+    else                           register_flags = register_flags & 0xFE;              // Clear the C flag
+    
+    local_data = ( old_carry_flag | (local_data>>1) );
+    
+
+    Calc_Flags_NEGATIVE_ZERO(local_data);
+    return local_data;
+}
+void opcode_0x66() {  Double_WriteBack(Calculate_ROR(Fetch_ZeroPage()));     Begin_Fetch_Next_Opcode();  return;  }  // 0x66 - ROR - Rotate Right - ZeroPage
+void opcode_0x76() {  Double_WriteBack(Calculate_ROR(Fetch_ZeroPage_X()));   Begin_Fetch_Next_Opcode();  return;  }  // 0x76 - ROR - Rotate Right - ZeroPage , X
+void opcode_0x6E() {  Double_WriteBack(Calculate_ROR(Fetch_Absolute()));     Begin_Fetch_Next_Opcode();  return;  }  // 0x6E - ROR - Rotate Right - Absolute
+void opcode_0x7E() {  Double_WriteBack(Calculate_ROR(Fetch_Absolute_X(0)));  Begin_Fetch_Next_Opcode();  return;  }  // 0x7E - ROR - Rotate Right - Absolute , X
+
+
+// -------------------------------------------------
+// ROL - Memory
+// -------------------------------------------------
+uint8_t Calculate_ROL(uint8_t local_data) {
+
+  uint8_t old_carry_flag=0;
+  
+    old_carry_flag = 0x1 & register_flags;                                      // Store the old carry flag to be rotated in
+    
+    
+    if (0x80&local_data)   register_flags = register_flags | 0x01;              // Set the C flag
+    else                   register_flags = register_flags & 0xFE;              // Clear the C flag
+    
+    local_data = (local_data<<1) | old_carry_flag;
+
+    Calc_Flags_NEGATIVE_ZERO(local_data);
+    return local_data;
+}
+void opcode_0x26() {  Double_WriteBack(Calculate_ROL(Fetch_ZeroPage()));     Begin_Fetch_Next_Opcode();  return;  }  // 0x26 - ROL - Rotate Left - ZeroPage
+void opcode_0x36() {  Double_WriteBack(Calculate_ROL(Fetch_ZeroPage_X()));   Begin_Fetch_Next_Opcode();  return;  }  // 0x36 - ROL - Rotate Left - ZeroPage , X
+void opcode_0x2E() {  Double_WriteBack(Calculate_ROL(Fetch_Absolute()));     Begin_Fetch_Next_Opcode();  return;  }  // 0x2E - ROL - Rotate Left - Absolute
+void opcode_0x3E() {  Double_WriteBack(Calculate_ROL(Fetch_Absolute_X(0)));  Begin_Fetch_Next_Opcode();  return;  }  // 0x3E - ROL - Rotate Left - Absolute , X
+
+
+// -------------------------------------------------
+// Branches
+// -------------------------------------------------
+void Branch_Taken()  {
+    
+    effective_address = Sign_Extend16(Fetch_Immediate()); 
+    effective_address = (register_pc+1) + effective_address;
+
+    if (SPEEDUP==0) {
+    if ( (0xFF00&register_pc) == (0xFF00&effective_address) )  {  Fetch_Immediate();                     }  // Page boundary not crossed
+    else                                                       {  Fetch_Immediate(); Fetch_Immediate();  }  // Page boundary crossed
+    }
+    register_pc = effective_address;
+    assert_sync=1;
+    start_read(register_pc);
+    return;
+}
+void opcode_0xB0() {  if ((flag_c)==1) Branch_Taken();  else { Fetch_Immediate(); Begin_Fetch_Next_Opcode();}  return;  }  // 0xB0 - BCS - Branch on Carry Set
+void opcode_0x90() {  if ((flag_c)==0) Branch_Taken();  else { Fetch_Immediate(); Begin_Fetch_Next_Opcode();}  return;  }  // 0x90 - BCC - Branch on Carry Clear
+void opcode_0xF0() {  if ((flag_z)==1) Branch_Taken();  else { Fetch_Immediate(); Begin_Fetch_Next_Opcode();}  return;  }  // 0xF0 - BEQ - Branch on Zero Set
+void opcode_0xD0() {  if ((flag_z)==0) Branch_Taken();  else { Fetch_Immediate(); Begin_Fetch_Next_Opcode();}  return;  }  // 0xD0 - BNE - Branch on Zero Clear
+void opcode_0x70() {  if ((flag_v)==1) Branch_Taken();  else { Fetch_Immediate(); Begin_Fetch_Next_Opcode();}  return;  }  // 0x70 - BVS - Branch on Overflow Set
+void opcode_0x50() {  if ((flag_v)==0) Branch_Taken();  else { Fetch_Immediate(); Begin_Fetch_Next_Opcode();}  return;  }  // 0x50 - BVC - Branch on Overflow Clear
+void opcode_0x30() {  if ((flag_n)==1) Branch_Taken();  else { Fetch_Immediate(); Begin_Fetch_Next_Opcode();}  return;  }  // 0x30 - BMI - Branch on Minus (N Flag Set)
+void opcode_0x10() {  if ((flag_n)==0) Branch_Taken();  else { Fetch_Immediate(); Begin_Fetch_Next_Opcode();}  return;  }  // 0x10 - BPL - Branch on Plus  (N Flag Clear)
+
+
+// -------------------------------------------------
+// Jumps and Returns
+// -------------------------------------------------
+void opcode_0x4C() { register_pc=Calculate_Absolute();  assert_sync=1; start_read(register_pc);  return;  }  // 0x4C - JMP - Jump Absolute
+
+
+// -------------------------------------------------
+// 0x6C - JMP - Jump Indirect
+// -------------------------------------------------
+void opcode_0x6C()  {
+    uint16_t lal, lah;
+    uint16_t adl, adh;
+    
+    lal = Fetch_Immediate();        
+    lah = Fetch_Immediate()<<8;     
+    adl = read_byte(lah + lal);     
+    adh = read_byte(lah + lal + 1)<<8;
+    effective_address = adh+adl;  
+    register_pc = (0xFF00&adh) + (0x00FF&effective_address) ;  // 6502 page wrapping bug 
+    assert_sync=1;
+    start_read(register_pc);
+    return ;
+}
+
+// -------------------------------------------------
+// 0x20 - JSR - Jump to Subroutine
+// -------------------------------------------------
+void opcode_0x20()  {
+    uint16_t adl, adh; 
+    
+    adl = Fetch_Immediate();
+    adh = Fetch_Immediate()<<8;
+    read_byte(register_sp_fixed);
+    push((0xFF00&register_pc)>>8);  
+
+    push(0x00FF&register_pc);
+    register_pc = adh+adl;  
+    assert_sync=1;
+    start_read(register_pc);
+    return ;
+}
+
+// -------------------------------------------------
+// 0x40 - RTI - Return from Interrupt
+// -------------------------------------------------
+void opcode_0x40()  {
+    uint16_t pcl, pch; 
+    
+    Fetch_Immediate();
+    read_byte(register_sp_fixed);
+    register_flags = pop();
+    pcl = pop();
+    pch = pop()<<8;
+    register_pc = pch+pcl;  
+    assert_sync=1;
+    start_read(register_pc);
+    return ;
+}
+
+// -------------------------------------------------
+// 0x60 - RTS - Return from Subroutine
+// -------------------------------------------------
+void opcode_0x60()  {
+    uint16_t pcl, pch; 
+    
+    Fetch_Immediate();
+    read_byte(register_sp_fixed);
+    pcl = pop();
+    pch = pop()<<8;
+    register_pc = pch+pcl+1;  
+    if (SPEEDUP==0) read_byte(register_pc);
+    assert_sync=1;
+    start_read(register_pc);
+    return ;
+}
+
+
+// -------------------------------------------------
+//
+// *** Undocumented 6502 Opcodes ***
+//
+// -------------------------------------------------
+
+// --------------------------------------------------------------------------------------------------
+// SLO - Shift left one bit in memory, then OR accumulator with memory.
+// --------------------------------------------------------------------------------------------------
+uint8_t Calculate_SLO(uint8_t local_data) {
+
+    if ((0x80&local_data)==0x80)   register_flags = register_flags | 0x01;              // Set the C flag
+    else                           register_flags = register_flags & 0xFE;              // Clear the C flag
+    
+    local_data = ((local_data << 1) & 0xFE);
+    
+    register_a = register_a | local_data;
+
+    Calc_Flags_NEGATIVE_ZERO(register_a);
+    return local_data;
+}
+void opcode_0x07() {  Double_WriteBack(Calculate_SLO(Fetch_ZeroPage()));              Begin_Fetch_Next_Opcode();  return;  }  // 0x07 - SLO - ZeroPage
+void opcode_0x17() {  Double_WriteBack(Calculate_SLO(Fetch_ZeroPage_X()));            Begin_Fetch_Next_Opcode();  return;  }  // 0x17 - SLO - ZeroPage , X
+void opcode_0x03() {  Double_WriteBack(Calculate_SLO(Fetch_Indexed_Indirect_X()));    Begin_Fetch_Next_Opcode();  return;  }  // 0x03 - SLO - Indexed Indirect X
+void opcode_0x13() {  Double_WriteBack(Calculate_SLO(Fetch_Indexed_Indirect_Y(1)));   Begin_Fetch_Next_Opcode();  return;  }  // 0x13 - SLO - Indirect Indexed  Y
+void opcode_0x0F() {  Double_WriteBack(Calculate_SLO(Fetch_Absolute()));              Begin_Fetch_Next_Opcode();  return;  }  // 0x0F - SLO - Absolute
+void opcode_0x1F() {  Double_WriteBack(Calculate_SLO(Fetch_Absolute_X(1)));           Begin_Fetch_Next_Opcode();  return;  }  // 0x1F - SLO - Absolute , X
+void opcode_0x1B() {  Double_WriteBack(Calculate_SLO(Fetch_Absolute_Y(1)));           Begin_Fetch_Next_Opcode();  return;  }  // 0x1B - SLO - Absolute , Y
+
+
+// --------------------------------------------------------------------------------------------------
+// RLA - Rotate one bit left in memory, then AND accumulator with memory.
+// --------------------------------------------------------------------------------------------------
+uint8_t Calculate_RLA(uint8_t local_data) {
+    uint8_t old_carry_flag=0;
+  
+    old_carry_flag = 0x1 & register_flags;                                      // Store the old carry flag to be rotated in
+    
+    
+    if (0x80&local_data)   register_flags = register_flags | 0x01;              // Set the C flag
+    else                   register_flags = register_flags & 0xFE;              // Clear the C flag
+    
+    local_data = (local_data<<1) | old_carry_flag;
+    
+    register_a = register_a & local_data;
+
+    Calc_Flags_NEGATIVE_ZERO(register_a);
+    return local_data;
+}
+void opcode_0x27() {  Double_WriteBack(Calculate_RLA(Fetch_ZeroPage()));              Begin_Fetch_Next_Opcode();  return;  }  // 0x27 - RLA - ZeroPage
+void opcode_0x37() {  Double_WriteBack(Calculate_RLA(Fetch_ZeroPage_X()));            Begin_Fetch_Next_Opcode();  return;  }  // 0x37 - RLA - ZeroPage , X
+void opcode_0x23() {  Double_WriteBack(Calculate_RLA(Fetch_Indexed_Indirect_X()));    Begin_Fetch_Next_Opcode();  return;  }  // 0x23 - RLA - Indexed Indirect X
+void opcode_0x33() {  Double_WriteBack(Calculate_RLA(Fetch_Indexed_Indirect_Y(1)));   Begin_Fetch_Next_Opcode();  return;  }  // 0x33 - RLA - Indirect Indexed  Y
+void opcode_0x2F() {  Double_WriteBack(Calculate_RLA(Fetch_Absolute()));              Begin_Fetch_Next_Opcode();  return;  }  // 0x2F - RLA - Absolute
+void opcode_0x3F() {  Double_WriteBack(Calculate_RLA(Fetch_Absolute_X(1)));           Begin_Fetch_Next_Opcode();  return;  }  // 0x3F - RLA - Absolute , X
+void opcode_0x3B() {  Double_WriteBack(Calculate_RLA(Fetch_Absolute_Y(1)));           Begin_Fetch_Next_Opcode();  return;  }  // 0x3B - RLA - Absolute , Y
+
+
+// --------------------------------------------------------------------------------------------------
+// SRE - Shift right one bit in memory, then EOR accumulator with memory.
+// --------------------------------------------------------------------------------------------------
+uint8_t Calculate_SRE(uint8_t local_data) {
+    
+    if ((0x01&local_data)==0x01)   register_flags = register_flags | 0x01;      // Set the C flag
+    else                           register_flags = register_flags & 0xFE;      // Clear the C flag
+      
+    local_data = (0x7F& (local_data >> 1));  
+    
+    register_a = register_a ^ local_data;
+
+    Calc_Flags_NEGATIVE_ZERO(register_a);
+    return local_data;
+}
+void opcode_0x47() {  Double_WriteBack(Calculate_SRE(Fetch_ZeroPage()));              Begin_Fetch_Next_Opcode();  return;  }  // 0x47 - SRE - ZeroPage
+void opcode_0x57() {  Double_WriteBack(Calculate_SRE(Fetch_ZeroPage_X()));            Begin_Fetch_Next_Opcode();  return;  }  // 0x57 - SRE - ZeroPage , X
+void opcode_0x43() {  Double_WriteBack(Calculate_SRE(Fetch_Indexed_Indirect_X()));    Begin_Fetch_Next_Opcode();  return;  }  // 0x43 - SRE - Indexed Indirect X
+void opcode_0x53() {  Double_WriteBack(Calculate_SRE(Fetch_Indexed_Indirect_Y(1)));   Begin_Fetch_Next_Opcode();  return;  }  // 0x53 - SRE - Indirect Indexed  Y
+void opcode_0x4F() {  Double_WriteBack(Calculate_SRE(Fetch_Absolute()));              Begin_Fetch_Next_Opcode();  return;  }  // 0x4F - SRE - Absolute
+void opcode_0x5F() {  Double_WriteBack(Calculate_SRE(Fetch_Absolute_X(1)));           Begin_Fetch_Next_Opcode();  return;  }  // 0x5F - SRE - Absolute , X
+void opcode_0x5B() {  Double_WriteBack(Calculate_SRE(Fetch_Absolute_Y(1)));           Begin_Fetch_Next_Opcode();  return;  }  // 0x5B - SRE - Absolute , Y
+
+
+// --------------------------------------------------------------------------------------------------
+// RRA - Rotate one bit right in memory, then add memory to accumulator (with carry).
+// --------------------------------------------------------------------------------------------------
+uint8_t Calculate_RRA(uint8_t local_data) {
+    
+    if ((0x01&local_data)==0x01)   register_flags = register_flags | 0x01;      // Set the C flag
+    else                           register_flags = register_flags & 0xFE;      // Clear the C flag
+      
+    local_data = (0x7F& (local_data >> 1));  
+    
+    global_temp = local_data;
+    
+    return local_data;
+}
+void opcode_0x67() {  Double_WriteBack(Calculate_RRA(Fetch_ZeroPage()));              Calculate_ADC(global_temp);  return;  }  // 0x67 - RRA - ZeroPage
+void opcode_0x77() {  Double_WriteBack(Calculate_RRA(Fetch_ZeroPage_X()));            Calculate_ADC(global_temp);  return;  }  // 0x77 - RRA - ZeroPage , X
+void opcode_0x63() {  Double_WriteBack(Calculate_RRA(Fetch_Indexed_Indirect_X()));    Calculate_ADC(global_temp);  return;  }  // 0x63 - RRA - Indexed Indirect X
+void opcode_0x73() {  Double_WriteBack(Calculate_RRA(Fetch_Indexed_Indirect_Y(1)));   Calculate_ADC(global_temp);  return;  }  // 0x73 - RRA - Indirect Indexed  Y
+void opcode_0x6F() {  Double_WriteBack(Calculate_RRA(Fetch_Absolute()));              Calculate_ADC(global_temp);  return;  }  // 0x6F - RRA - Absolute
+void opcode_0x7F() {  Double_WriteBack(Calculate_RRA(Fetch_Absolute_X(1)));           Calculate_ADC(global_temp);  return;  }  // 0x7F - RRA - Absolute , X
+void opcode_0x7B() {  Double_WriteBack(Calculate_RRA(Fetch_Absolute_Y(1)));           Calculate_ADC(global_temp);  return;  }  // 0x7B - RRA - Absolute , Y
+
+
+// --------------------------------------------------------------------------------------------------
+// AND the contents of the A and X registers (without changing the contents of either register) and 
+// stores the result in memory.
+// --------------------------------------------------------------------------------------------------
+void opcode_0x87() {  Write_ZeroPage(register_a&register_x);            Begin_Fetch_Next_Opcode();  return;  }  // 0x87 - SAX - ZeroPage
+void opcode_0x97() {  Write_ZeroPage_Y(register_a&register_x);          Begin_Fetch_Next_Opcode();  return;  }  // 0x97 - SAX - ZeroPage , Y
+void opcode_0x83() {  Write_Indexed_Indirect_X(register_a&register_x);  Begin_Fetch_Next_Opcode();  return;  }  // 0x83 - SAX - Indexed Indirect X
+void opcode_0x8F() {  Write_Absolute(register_a&register_x);            Begin_Fetch_Next_Opcode();  return;  }  // 0x8F - SAX - Absolute
+
+
+// --------------------------------------------------------------------------------------------------
+// Load both the accumulator and the X register with the contents of a memory location.
+// --------------------------------------------------------------------------------------------------
+void opcode_0xA7() { register_a=Fetch_ZeroPage();             register_x=register_a;   Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0xA7 - LAX - ZeroPage
+void opcode_0xB7() { register_a=Fetch_ZeroPage_Y();           register_x=register_a;   Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0xB7 - LAX - ZeroPage , Y
+void opcode_0xA3() { register_a=Fetch_Indexed_Indirect_X();   register_x=register_a;   Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0xA3 - LAX - Indexed Indirect X
+void opcode_0xB3() { register_a=Fetch_Indexed_Indirect_Y(1);  register_x=register_a;   Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0xB3 - LAX - Indirect Indexed  Y
+void opcode_0xAF() { register_a=Fetch_Absolute();             register_x=register_a;   Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0xAF - LAX - Absolute
+void opcode_0xBF() { register_a=Fetch_Absolute_Y(1);          register_x=register_a;   Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0xBF - LAX - Absolute , Y
+
+
+// --------------------------------------------------------------------------------------------------
+// Decrement the contents of a memory location and then compare the result with the A register.
+// --------------------------------------------------------------------------------------------------
+void opcode_0xC7() {  Double_WriteBack(Calculate_DEC(Fetch_ZeroPage()));             Calculate_CMP(global_temp);  return;  }  // 0xC7 - DCP - ZeroPage
+void opcode_0xD7() {  Double_WriteBack(Calculate_DEC(Fetch_ZeroPage_X()));           Calculate_CMP(global_temp);  return;  }  // 0xD7 - DCP - ZeroPage , X
+void opcode_0xC3() {  Double_WriteBack(Calculate_DEC(Fetch_Indexed_Indirect_X()));   Calculate_CMP(global_temp);  return;  }  // 0xC3 - DCP - Indexed Indirect X
+void opcode_0xD3() {  Double_WriteBack(Calculate_DEC(Fetch_Indexed_Indirect_Y(0)));  Calculate_CMP(global_temp);  return;  }  // 0xD3 - DCP - Indirect Indexed  Y
+void opcode_0xCF() {  Double_WriteBack(Calculate_DEC(Fetch_Absolute()));             Calculate_CMP(global_temp);  return;  }  // 0xCF - DCP - Absolute
+void opcode_0xDF() {  Double_WriteBack(Calculate_DEC(Fetch_Absolute_X(0)));          Calculate_CMP(global_temp);  return;  }  // 0xDF - DCP - Absolute , X
+void opcode_0xDB() {  Double_WriteBack(Calculate_DEC(Fetch_Absolute_Y(0)));          Calculate_CMP(global_temp);  return;  }  // 0xDB - DCP - Absolute , Y
+
+
+
+// --------------------------------------------------------------------------------------------------
+// ISC - Increase memory by one, then subtract memory from accumulator (with borrow).
+// --------------------------------------------------------------------------------------------------
+void opcode_0xE7() {  Double_WriteBack(Calculate_INC(Fetch_ZeroPage()));             Calculate_SBC(global_temp);  return;  }  // 0xE7 - ISC - ZeroPage
+void opcode_0xF7() {  Double_WriteBack(Calculate_INC(Fetch_ZeroPage_X()));           Calculate_SBC(global_temp);  return;  }  // 0xF7 - ISC - ZeroPage , X
+void opcode_0xE3() {  Double_WriteBack(Calculate_INC(Fetch_Indexed_Indirect_X()));   Calculate_SBC(global_temp);  return;  }  // 0xE3 - ISC - Indexed Indirect X
+void opcode_0xF3() {  Double_WriteBack(Calculate_INC(Fetch_Indexed_Indirect_Y(0)));  Calculate_SBC(global_temp);  return;  }  // 0xF3 - ISC - Indirect Indexed  Y
+void opcode_0xEF() {  Double_WriteBack(Calculate_INC(Fetch_Absolute()));             Calculate_SBC(global_temp);  return;  }  // 0xEF - ISC - Absolute
+void opcode_0xFF() {  Double_WriteBack(Calculate_INC(Fetch_Absolute_X(0)));          Calculate_SBC(global_temp);  return;  }  // 0xFF - ISC - Absolute , X
+void opcode_0xFB() {  Double_WriteBack(Calculate_INC(Fetch_Absolute_Y(0)));          Calculate_SBC(global_temp);  return;  }  // 0xFB - ISC - Absolute , Y
+
+
+// --------------------------------------------------------------------------------------------------
+// ANC - ANDs the contents of the A register with an immediate value and then moves bit 7 of A
+// into the Carry flag.
+// --------------------------------------------------------------------------------------------------
+void Calculate_ANC(uint8_t local_data) {
+    
+    Begin_Fetch_Next_Opcode();
+
+    register_a = register_a & local_data;
+
+    if ((0x80&register_a)==0x80)   register_flags = register_flags | 0x01;              // Set the C flag
+    else                           register_flags = register_flags & 0xFE;              // Clear the C flag
+        
+    Calc_Flags_NEGATIVE_ZERO(register_a);
+    return;
+}
+void opcode_0x0B() {  Calculate_ANC(Fetch_Immediate());  return;  }  // 0x0B - ANC - Immediate
+void opcode_0x2B() {  Calculate_ANC(Fetch_Immediate());  return;  }  // 0x2B - ANC - Immediate
+
+
+// --------------------------------------------------------------------------------------------------
+// ALR - AND the contents of the A register with an immediate value and then LSRs the result.
+// --------------------------------------------------------------------------------------------------
+void Calculate_ALR(uint8_t local_data) {
+    
+    Begin_Fetch_Next_Opcode();
+
+    register_a = register_a & local_data;
+    
+    if ((0x01&register_a)==0x01)   register_flags = register_flags | 0x01;              // Set the C flag
+    else                           register_flags = register_flags & 0xFE;              // Clear the C flag
+      
+    register_a = (0x7F& (register_a >> 1));  
+    
+    Calc_Flags_NEGATIVE_ZERO(register_a);
+    return;
+}
+void opcode_0x4B() {  Calculate_ALR(Fetch_Immediate());  return;  }  // 0x4B - ALR - Immediate
+
+
+// --------------------------------------------------------------------------------------------------
+// ARR - ANDs the accumulator with an immediate value and then rotates the content right.
+// --------------------------------------------------------------------------------------------------
+void Calculate_ARR(uint8_t local_data) {
+    
+    Begin_Fetch_Next_Opcode();
+
+    register_a = register_a & local_data;
+    
+    register_a = (0x7F& (register_a >> 1));  
+
+    register_flags = register_flags & 0xBE;                                            // Pre-clear the C and V flags   
+    if ( (0xC0 & register_a) == 0x40) {  register_flags = register_flags | 0x40;  }    // Set the V flag 
+    if ( (0xC0 & register_a) == 0x80) {  register_flags = register_flags | 0x41;  }    // Set the C and V flags 
+    if ( (0xC0 & register_a) == 0xC0) {  register_flags = register_flags | 0x01;  }    // Set the C flag 
+    
+    Calc_Flags_NEGATIVE_ZERO(register_a);
+    return;
+}
+void opcode_0x6B() {  Calculate_ARR(Fetch_Immediate());  return;  }  // 0x6B - ARR - Immediate
+
+
+// --------------------------------------------------------------------------------------------------
+// SBX - ANDs the contents of the A and X registers (leaving the contents of A intact),
+// subtracts an immediate value, and then stores the result in X.
+// --------------------------------------------------------------------------------------------------
+void Calculate_SBX(uint16_t local_data)  { 
+    int16_t signed_total=0;
+
+ 
+    Begin_Fetch_Next_Opcode();
+    
+    register_x = register_a & register_x;
+
+
+    register_x =  register_x - local_data;
+    signed_total = (int16_t)register_x - (int16_t)(local_data );
+
+    
+    if (signed_total>=0)    register_flags = register_flags | 0x01;              // Set the C flag
+    else                    register_flags = register_flags & 0xFE;              // Clear the C flag  
+
+    register_x = (0xFF & register_x);
+    Calc_Flags_NEGATIVE_ZERO(register_x);
+    
+    return;
+    }
+void opcode_0xCB() {  Calculate_SBX(Fetch_Immediate());  return;  }  // 0xCB - SBX - Immediate
+    
+    
+// --------------------------------------------------------------------------------------------------
+// LAS - AND memory with stack pointer, transfer result to accumulator, X register and stack pointer.
+// --------------------------------------------------------------------------------------------------
+void opcode_0xBB() { register_sp=(register_sp&Fetch_Absolute_Y(1));  register_a=register_sp;  register_x=register_sp;  Begin_Fetch_Next_Opcode();  Calc_Flags_NEGATIVE_ZERO(register_a); return;  }  // 0xBB - LAS - Absolute , Y
+    
+
+// --------------------------------------------------------------------------------------------------
+// NOP - Fetch Immediate
+// --------------------------------------------------------------------------------------------------
+void opcode_0x80() {  Fetch_Immediate();  Begin_Fetch_Next_Opcode(); return;  }  // 0x80 - NOP - Immediate
+void opcode_0x82() {  Fetch_Immediate();  Begin_Fetch_Next_Opcode(); return;  }  // 0x82 - NOP - Immediate
+void opcode_0xC2() {  Fetch_Immediate();  Begin_Fetch_Next_Opcode(); return;  }  // 0xC2 - NOP - Immediate
+void opcode_0xE2() {  Fetch_Immediate();  Begin_Fetch_Next_Opcode(); return;  }  // 0xE2 - NOP - Immediate
+void opcode_0x89() {  Fetch_Immediate();  Begin_Fetch_Next_Opcode(); return;  }  // 0x89 - NOP - Immediate
+
+
+// --------------------------------------------------------------------------------------------------
+// NOP - Fetch ZeroPage
+// --------------------------------------------------------------------------------------------------
+void opcode_0x04() {  Fetch_ZeroPage();  Begin_Fetch_Next_Opcode(); return;  }  // 0x04 - NOP - ZeroPage
+void opcode_0x44() {  Fetch_ZeroPage();  Begin_Fetch_Next_Opcode(); return;  }  // 0x44 - NOP - ZeroPage
+void opcode_0x64() {  Fetch_ZeroPage();  Begin_Fetch_Next_Opcode(); return;  }  // 0x64 - NOP - ZeroPage
+
+
+// --------------------------------------------------------------------------------------------------
+// NOP - Fetch ZeroPage , X
+// --------------------------------------------------------------------------------------------------
+void opcode_0x14() {  Fetch_ZeroPage_X();  Begin_Fetch_Next_Opcode(); return;  }  // 0x14 - NOP - ZeroPage , X
+void opcode_0x34() {  Fetch_ZeroPage_X();  Begin_Fetch_Next_Opcode(); return;  }  // 0x34 - NOP - ZeroPage , X
+void opcode_0x54() {  Fetch_ZeroPage_X();  Begin_Fetch_Next_Opcode(); return;  }  // 0x54 - NOP - ZeroPage , X
+void opcode_0x74() {  Fetch_ZeroPage_X();  Begin_Fetch_Next_Opcode(); return;  }  // 0x74 - NOP - ZeroPage , X
+void opcode_0xD4() {  Fetch_ZeroPage_X();  Begin_Fetch_Next_Opcode(); return;  }  // 0xD4 - NOP - ZeroPage , X
+void opcode_0xF4() {  Fetch_ZeroPage_X();  Begin_Fetch_Next_Opcode(); return;  }  // 0xF4 - NOP - ZeroPage , X
+
+
+// --------------------------------------------------------------------------------------------------
+// NOP - Fetch Absolute
+// --------------------------------------------------------------------------------------------------
+void opcode_0x0C() {  Fetch_Absolute();  Begin_Fetch_Next_Opcode(); return;  }  // 0x0C - NOP - Absolute
+
+
+// --------------------------------------------------------------------------------------------------
+// NOP - Fetch Absolute , X
+// --------------------------------------------------------------------------------------------------
+void opcode_0x1C() {  Fetch_Absolute_X(1);  Begin_Fetch_Next_Opcode(); return;  }  // 0x1C - NOP - Absolute , X
+void opcode_0x3C() {  Fetch_Absolute_X(1);  Begin_Fetch_Next_Opcode(); return;  }  // 0x3C - NOP - Absolute , X
+void opcode_0x5C() {  Fetch_Absolute_X(1);  Begin_Fetch_Next_Opcode(); return;  }  // 0x5C - NOP - Absolute , X
+void opcode_0x7C() {  Fetch_Absolute_X(1);  Begin_Fetch_Next_Opcode(); return;  }  // 0x7C - NOP - Absolute , X
+void opcode_0xDC() {  Fetch_Absolute_X(1);  Begin_Fetch_Next_Opcode(); return;  }  // 0xDC - NOP - Absolute , X
+void opcode_0xFC() {  Fetch_Absolute_X(1);  Begin_Fetch_Next_Opcode(); return;  }  // 0xFC - NOP - Absolute , X
+
+
+// --------------------------------------------------------------------------------------------------
+// JAM - Lock up the processor
+// --------------------------------------------------------------------------------------------------
+void opcode_0x02() {  Fetch_Immediate();   while (1) {}    return;  }  // 0x02 - JAM
+void opcode_0x12() {  Fetch_Immediate();   while (1) {}    return;  }  // 0x12 - JAM
+void opcode_0x22() {  Fetch_Immediate();   while (1) {}    return;  }  // 0x22 - JAM
+void opcode_0x32() {  Fetch_Immediate();   while (1) {}    return;  }  // 0x32 - JAM
+void opcode_0x42() {  Fetch_Immediate();   while (1) {}    return;  }  // 0x42 - JAM
+void opcode_0x52() {  Fetch_Immediate();   while (1) {}    return;  }  // 0x52 - JAM
+void opcode_0x62() {  Fetch_Immediate();   while (1) {}    return;  }  // 0x62 - JAM
+void opcode_0x72() {  Fetch_Immediate();   while (1) {}    return;  }  // 0x72 - JAM
+void opcode_0x92() {  Fetch_Immediate();   while (1) {}    return;  }  // 0x92 - JAM
+void opcode_0xB2() {  Fetch_Immediate();   while (1) {}    return;  }  // 0xB2 - JAM
+void opcode_0xD2() {  Fetch_Immediate();   while (1) {}    return;  }  // 0xD2 - JAM
+void opcode_0xF2() {  Fetch_Immediate();   while (1) {}    return;  }  // 0xF2 - JAM
+
+
+// --------------------------------------------------------------------------------------------------
+// Unstable 6502 opcodes
+// --------------------------------------------------------------------------------------------------
+void opcode_0x93() {  Fetch_ZeroPage_Y();   Begin_Fetch_Next_Opcode(); return;  }  // 0x93 - SHA - ZeroPage , Y - Implelented here as a size 2 NOP
+void opcode_0x9F() {  Fetch_Absolute_Y(0);  Begin_Fetch_Next_Opcode(); return;  }  // 0x9F - SHA - Absolute , Y - Implelented here as a size 3 NOP
+void opcode_0x9E() {  Fetch_Absolute_Y(0);  Begin_Fetch_Next_Opcode(); return;  }  // 0x9E - SHX - Absolute , Y - Implelented here as a size 3 NOP
+void opcode_0x9C() {  Fetch_Absolute_X(0);  Begin_Fetch_Next_Opcode(); return;  }  // 0x9C - SHY - Absolute , X - Implelented here as a size 3 NOP
+void opcode_0x9B() {  Fetch_Absolute_Y(0);  Begin_Fetch_Next_Opcode(); return;  }  // 0x9B - TAS - Absolute , Y - Implelented here as a size 3 NOP
+void opcode_0x8B() {  Fetch_Immediate();    Begin_Fetch_Next_Opcode(); return;  }  // 0x8B - ANE - Immediate    - Implelented here as a size 2 NOP
+void opcode_0xAB() {  Fetch_Immediate();    Begin_Fetch_Next_Opcode(); return;  }  // 0xAB - LAX - Immediate    - Implelented here as a size 2 NOP
+
+
+// --------------------------------------------------------------------------------------------------
+// --------------------------------------------------------------------------------------------------
+
+
+// -------------------------------------------------
+//
+// Main loop
+//
+// -------------------------------------------------
+ void loop() {
+  
+  //setup();
+  
+  // Give Teensy 4.1 a moment
+  delay (50);
+  wait_for_CLK_rising_edge();
+  wait_for_CLK_rising_edge();
+  wait_for_CLK_rising_edge();
+
+  reset_sequence();
+
+
+  while (1) {
+      
+      if (direct_reset==1) reset_sequence();
+    
+    
+      // Poll for NMI and IRQ
+      //
+      nmi_n_old = direct_nmi;                                        
+      if (nmi_n_old==0 && direct_nmi==1)        nmi_handler();          
+      if (direct_irq==0x1  && (flag_i)==0x0)    irq_handler(0x0);   
+
+    
+      next_instruction = finish_read_byte();  
+      assert_sync=0;
+      
+      switch (next_instruction){
+          
+        case 0x00:   irq_handler(0x1); break;  // BRK - Break
+        case 0x01:   opcode_0x01();    break;  // OR - Indexed Indirect X
+        case 0x02:   opcode_0x02();    break;  // JAM
+        case 0x03:   opcode_0x03();    break;  // SLO - Indexed Indirect X
+        case 0x04:   opcode_0x04();    break;  // NOP - ZeroPage
+        case 0x05:   opcode_0x05();    break;  // OR ZeroPage
+        case 0x06:   opcode_0x06();    break;  // ASL A - Arithmetic Shift Left - ZeroPage
+        case 0x07:   opcode_0x07();    break;  // SLO - ZeroPage
+        case 0x08:   opcode_0x08();    break;  // PHP - Push processor status to the stack
+        case 0x09:   opcode_0x09();    break;  // OR - Immediate
+        case 0x0A:   opcode_0x0A();    break;  // ASL A
+        case 0x0B:   opcode_0x0B();    break;  // ANC - Immediate
+        case 0x0C:   opcode_0x0C();    break;  // NOP - Absolute
+        case 0x0D:   opcode_0x0D();    break;  // OR - Absolute
+        case 0x0E:   opcode_0x0E();    break;  // ASL A - Arithmetic Shift Left - Absolute
+        case 0x0F:   opcode_0x0F();    break;  // SLO - Absolute
+        case 0x10:   opcode_0x10();    break;  // BNE - Branch on Zero Clear
+        case 0x11:   opcode_0x11();    break;  // OR Indirect Indexed  Y
+        case 0x12:   opcode_0x12();    break;  // JAM
+        case 0x13:   opcode_0x13();    break;  // Indirect Indexed  Y
+        case 0x14:   opcode_0x14();    break;  // NOP - ZeroPage , X
+        case 0x15:   opcode_0x15();    break;  // OR - ZeroPage,X
+        case 0x16:   opcode_0x16();    break;  // ASL A - Arithmetic Shift Left - ZeroPage , X
+        case 0x17:   opcode_0x17();    break;  // SLO - ZeroPage , X
+        case 0x18:   opcode_0x18();    break;  // CLC
+        case 0x19:   opcode_0x19();    break;  // OR - Absolute,Y
+        case 0x1A:   opcode_0xEA();    break;  // NOP
+        case 0x1B:   opcode_0x1B();    break;  // SLO - Absolute , Y
+        case 0x1C:   opcode_0x1C();    break;  // NOP - Absolute , X
+        case 0x1D:   opcode_0x1D();    break;  // OR - Absolute,X
+        case 0x1E:   opcode_0x1E();    break;  // ASL A - Arithmetic Shift Left - Absolute , X
+        case 0x1F:   opcode_0x1F();    break;  // SLO - Absolute , X
+        case 0x20:   opcode_0x20();    break;  // JSR - Jump to Subroutine
+        case 0x21:   opcode_0x21();    break;  // AND - Indexed Indirect
+        case 0x22:   opcode_0x22();    break;  // JAM
+        case 0x23:   opcode_0x23();    break;  // RLA - Indexed Indirect X
+        case 0x24:   opcode_0x24();    break;  // BIT - ZeroPage
+        case 0x25:   opcode_0x25();    break;  // AND - ZeroPage
+        case 0x26:   opcode_0x26();    break;  // ROL - Rotate Left - ZeroPage
+        case 0x27:   opcode_0x27();    break;  // RLA - ZeroPage
+        case 0x28:   opcode_0x28();    break;  // PLP - Pop processor status from the stack
+        case 0x29:   opcode_0x29();    break;  // AND - Immediate
+        case 0x2A:   opcode_0x2A();    break;  // ROL A
+        case 0x2B:   opcode_0x2B();    break;  // ANC - Immediate
+        case 0x2C:   opcode_0x2C();    break;  // BIT - Absolute
+        case 0x2D:   opcode_0x2D();    break;  // AND - Absolute
+        case 0x2E:   opcode_0x2E();    break;  // ROL - Rotate Left - Absolute
+        case 0x2F:   opcode_0x2F();    break;  // RLA - Absolute
+        case 0x30:   opcode_0x30();    break;  // BMI - Branch on Minus (N Flag Set)
+        case 0x31:   opcode_0x31();    break;  // AND - Indirect Indexed
+        case 0x32:   opcode_0x32();    break;  // JAM
+        case 0x33:   opcode_0x33();    break;  // RLA - Indirect Indexed  Y
+        case 0x34:   opcode_0x34();    break;  // NOP - ZeroPage , X
+        case 0x35:   opcode_0x35();    break;  // AND - ZeroPage,X
+        case 0x36:   opcode_0x36();    break;  // ROL - Rotate Left - ZeroPage , X
+        case 0x37:   opcode_0x37();    break;  // RLA - ZeroPage , X
+        case 0x38:   opcode_0x38();    break;  // SEC
+        case 0x39:   opcode_0x39();    break;  // AND - Absolute,Y
+        case 0x3A:   opcode_0xEA();    break;  // NOP
+        case 0x3B:   opcode_0x3B();    break;  // RLA - Absolute , Y
+        case 0x3C:   opcode_0x3C();    break;  // NOP - Absolute , X
+        case 0x3D:   opcode_0x3D();    break;  // AND - Absolute,X
+        case 0x3E:   opcode_0x3E();    break;  // ROL - Rotate Left - Absolute , X
+        case 0x3F:   opcode_0x3F();    break;  // RLA - Absolute , X
+        case 0x40:   opcode_0x40();    break;  // RTI - Return from Interrupt
+        case 0x41:   opcode_0x41();    break;  // EOR - Indexed Indirect X
+        case 0x42:   opcode_0x42();    break;  // JAM
+        case 0x43:   opcode_0x43();    break;  // SRE - Indexed Indirect X
+        case 0x44:   opcode_0x44();    break;  // NOP - ZeroPage
+        case 0x45:   opcode_0x45();    break;  // EOR - ZeroPage
+        case 0x46:   opcode_0x46();    break;  // LSR - Logical Shift Right - ZeroPage
+        case 0x47:   opcode_0x47();    break;  // SRE - ZeroPage
+        case 0x48:   opcode_0x48();    break;  // PHA - Push Accumulator to the stack
+        case 0x49:   opcode_0x49();    break;  // EOR - Immediate
+        case 0x4A:   opcode_0x4A();    break;  // LSR A
+        case 0x4B:   opcode_0x4B();    break;  // ALR - Immediate
+        case 0x4C:   opcode_0x4C();    break;  // JMP - Jump Absolute
+        case 0x4D:   opcode_0x4D();    break;  // EOR - Absolute
+        case 0x4E:   opcode_0x4E();    break;  // LSR - Logical Shift Right - Absolute
+        case 0x4F:   opcode_0x4F();    break;  // SRE - Absolute
+        case 0x50:   opcode_0x50();    break;  // BVC - Branch on Overflow Clear
+        case 0x51:   opcode_0x51();    break;  // EOR - Indirect Indexed  Y
+        case 0x52:   opcode_0x52();    break;  // JAM
+        case 0x53:   opcode_0x53();    break;  // SRE - Indirect Indexed  Y
+        case 0x54:   opcode_0x54();    break;  // NOP - ZeroPage , X
+        case 0x55:   opcode_0x55();    break;  // EOR - ZeroPage,X
+        case 0x56:   opcode_0x56();    break;  // LSR - Logical Shift Right - ZeroPage , X
+        case 0x57:   opcode_0x57();    break;  // SRE - ZeroPage , X
+        case 0x58:   opcode_0x58();    break;  // CLI
+        case 0x59:   opcode_0x59();    break;  // EOR - Absolute,Y
+        case 0x5A:   opcode_0xEA();    break;  // NOP
+        case 0x5B:   opcode_0x5B();    break;  // RE - Absolute , Y
+        case 0x5C:   opcode_0x5C();    break;  // NOP - Absolute , X
+        case 0x5D:   opcode_0x5D();    break;  // EOR - Absolute,X
+        case 0x5E:   opcode_0x5E();    break;  // LSR - Logical Shift Right - Absolute , X
+        case 0x5F:   opcode_0x5F();    break;  // SRE - Absolute , X
+        case 0x60:   opcode_0x60();    break;  // RTS - Return from Subroutine
+        case 0x61:   opcode_0x61();    break;  // ADC - Indexed Indirect X
+        case 0x62:   opcode_0x62();    break;  // JAM
+        case 0x63:   opcode_0x63();    break;  // RRA - Indexed Indirect X
+        case 0x64:   opcode_0x64();    break;  // NOP - ZeroPage
+        case 0x65:   opcode_0x65();    break;  // ADC - ZeroPage
+        case 0x66:   opcode_0x66();    break;  // ROR - Rotate Right - ZeroPage
+        case 0x67:   opcode_0x67();    break;  // RRA - ZeroPage
+        case 0x68:   opcode_0x68();    break;  // PLA - Pop Accumulator from the stack
+        case 0x69:   opcode_0x69();    break;  // ADC - Immediate
+        case 0x6A:   opcode_0x6A();    break;  // ROR A
+        case 0x6B:   opcode_0x6B();    break;  // ARR - Immediate
+        case 0x6C:   opcode_0x6C();    break;  // JMP - Jump Indirect
+        case 0x6D:   opcode_0x6D();    break;  // ADC - Absolute
+        case 0x6E:   opcode_0x6E();    break;  // ROR - Rotate Right - Absolute
+        case 0x6F:   opcode_0x6F();    break;  // RRA - Absolute
+        case 0x70:   opcode_0x70();    break;  // BVS - Branch on Overflow Set
+        case 0x71:   opcode_0x71();    break;  // ADC - Indirect Indexed  Y
+        case 0x72:   opcode_0x72();    break;  // JAM
+        case 0x73:   opcode_0x73();    break;  // RRA - Indirect Indexed  Y
+        case 0x74:   opcode_0x74();    break;  // NOP - ZeroPage , X
+        case 0x75:   opcode_0x75();    break;  // ADC - ZeroPage , X
+        case 0x76:   opcode_0x76();    break;  // ROR - Rotate Right - ZeroPage , X
+        case 0x77:   opcode_0x77();    break;  // RRA - ZeroPage , X
+        case 0x78:   opcode_0x78();    break;  // SEI
+        case 0x79:   opcode_0x79();    break;  // ADC - Absolute , Y
+        case 0x7A:   opcode_0xEA();    break;  // NOP
+        case 0x7B:   opcode_0x7B();    break;  // RRA - Absolute , Y
+        case 0x7C:   opcode_0x7C();    break;  // NOP - Absolute , X
+        case 0x7D:   opcode_0x7D();    break;  // ADC - Absolute , X
+        case 0x7E:   opcode_0x7E();    break;  // ROR - Rotate Right - Absolute , X
+        case 0x7F:   opcode_0x7F();    break;  // RRA - Absolute , X
+        case 0x80:   opcode_0x80();    break;  // NOP - Immediate
+        case 0x81:   opcode_0x81();    break;  // STA - Indexed Indirect X
+        case 0x82:   opcode_0x82();    break;  // NOP - Immediate
+        case 0x83:   opcode_0x83();    break;  // SAX - Indexed Indirect X
+        case 0x84:   opcode_0x84();    break;  // STY - ZeroPage
+        case 0x85:   opcode_0x85();    break;  // STA - ZeroPage
+        case 0x86:   opcode_0x86();    break;  // STX - ZeroPage
+        case 0x87:   opcode_0x87();    break;  // SAX - ZeroPage
+        case 0x88:   opcode_0x88();    break;  // DEY
+        case 0x89:   opcode_0x89();    break;  // NOP - Immediate
+        case 0x8A:   opcode_0x8A();    break;  // TXA
+        case 0x8B:   opcode_0x8B();    break;  // ANE - Immediate
+        case 0x8C:   opcode_0x8C();    break;  // STY - Absolute
+        case 0x8D:   opcode_0x8D();    break;  // STA - Absolute
+        case 0x8E:   opcode_0x8E();    break;  // STX - Absolute
+        case 0x8F:   opcode_0x8F();    break;  // SAX - Absolute
+        case 0x90:   opcode_0x90();    break;  // BCC - Branch on Carry Clear
+        case 0x91:   opcode_0x91();    break;  // STA - Indirect Indexed  Y
+        case 0x92:   opcode_0x92();    break;  // JAM
+        case 0x93:   opcode_0x93();    break;  // SHA - ZeroPage , Y
+        case 0x94:   opcode_0x94();    break;  // STY - ZeroPage , X
+        case 0x95:   opcode_0x95();    break;  // STA - ZeroPage , X
+        case 0x96:   opcode_0x96();    break;  // STX - ZeroPage , Y
+        case 0x97:   opcode_0x97();    break;  // SAX - ZeroPage , Y
+        case 0x98:   opcode_0x98();    break;  // TYA
+        case 0x99:   opcode_0x99();    break;  // STA - Absolute , Y
+        case 0x9A:   opcode_0x9A();    break;  // TXS
+        case 0x9B:   opcode_0x9B();    break;  // TAS - Absolute , Y 
+        case 0x9C:   opcode_0x9C();    break;  // SHY - Absolute , X
+        case 0x9D:   opcode_0x9D();    break;  // STA - Absolute , X
+        case 0x9E:   opcode_0x9E();    break;  // SHX - Absolute , Y
+        case 0x9F:   opcode_0x9F();    break;  // SHA - Absolute , Y
+        case 0xA0:   opcode_0xA0();    break;  // LDY - Immediate
+        case 0xA1:   opcode_0xA1();    break;  // LDA - Indexed Indirect X
+        case 0xA2:   opcode_0xA2();    break;  // LDX - Immediate
+        case 0xA3:   opcode_0xA3();    break;  // LAX - Indexed Indirect X
+        case 0xA4:   opcode_0xA4();    break;  // LDY - ZeroPage
+        case 0xA5:   opcode_0xA5();    break;  // LDA - ZeroPage
+        case 0xA6:   opcode_0xA6();    break;  // LDX - ZeroPage
+        case 0xA7:   opcode_0xA7();    break;  // LAX - ZeroPage
+        case 0xA8:   opcode_0xA8();    break;  // TAY
+        case 0xA9:   opcode_0xA9();    break;  // LDA - Immediate
+        case 0xAA:   opcode_0xAA();    break;  // TAX
+        case 0xAB:   opcode_0xAB();    break;  // LAX - Immediate
+        case 0xAC:   opcode_0xAC();    break;  // LDY - Absolute
+        case 0xAD:   opcode_0xAD();    break;  // LDA - Absolute
+        case 0xAE:   opcode_0xAE();    break;  // LDX - Absolute
+        case 0xAF:   opcode_0xAF();    break;  // LAX - Absolute
+        case 0xB0:   opcode_0xB0();    break;  // BCS - Branch on Carry Set
+        case 0xB1:   opcode_0xB1();    break;  // LDA - Indirect Indexed  Y
+        case 0xB2:   opcode_0xB2();    break;  // JAM
+        case 0xB3:   opcode_0xB3();    break;  // LAX - Indirect Indexed  Y
+        case 0xB4:   opcode_0xB4();    break;  // LDY - ZeroPage , X
+        case 0xB5:   opcode_0xB5();    break;  // LDA - ZeroPage , X
+        case 0xB6:   opcode_0xB6();    break;  // LDX - ZeroPage , Y
+        case 0xB7:   opcode_0xB7();    break;  // LAX - ZeroPage , Y
+        case 0xB8:   opcode_0xB8();    break;  // CLV
+        case 0xB9:   opcode_0xB9();    break;  // LDA - Absolute , Y
+        case 0xBA:   opcode_0xBA();    break;  // TSX
+        case 0xBB:   opcode_0xBB();    break;  // LAS - Absolute , Y
+        case 0xBC:   opcode_0xBC();    break;  // LDY - Absolute , X
+        case 0xBD:   opcode_0xBD();    break;  // LDA - Absolute , X
+        case 0xBE:   opcode_0xBE();    break;  // LDX - Absolute , Y
+        case 0xBF:   opcode_0xBF();    break;  // LAX - Absolute , Y
+        case 0xC0:   opcode_0xC0();    break;  // CPY - Immediate
+        case 0xC1:   opcode_0xC1();    break;  // CMP - Indexed Indirect X
+        case 0xC2:   opcode_0xC2();    break;  // NOP - Immediate
+        case 0xC3:   opcode_0xC3();    break;  // DCP - Indexed Indirect X
+        case 0xC4:   opcode_0xC4();    break;  // CPY - ZeroPage
+        case 0xC5:   opcode_0xC5();    break;  // CMP - ZeroPage
+        case 0xC6:   opcode_0xC6();    break;  // DEC - ZeroPage
+        case 0xC7:   opcode_0xC7();    break;  // DCP - ZeroPage
+        case 0xC8:   opcode_0xC8();    break;  // INY
+        case 0xC9:   opcode_0xC9();    break;  // CMP - Immediate
+        case 0xCA:   opcode_0xCA();    break;  // DEX
+        case 0xCB:   opcode_0xCB();    break;  // SBX - Immediate
+        case 0xCC:   opcode_0xCC();    break;  // CPY - Absolute
+        case 0xCD:   opcode_0xCD();    break;  // CMP - Absolute
+        case 0xCE:   opcode_0xCE();    break;  // DEC - Absolute
+        case 0xCF:   opcode_0xCF();    break;  // DCP - Absolute
+        case 0xD0:   opcode_0xD0();    break;  // BNE - Branch on Zero Clear
+        case 0xD1:   opcode_0xD1();    break;  // CMP - Indirect Indexed  Y
+        case 0xD2:   opcode_0xD2();    break;  // JAM
+        case 0xD3:   opcode_0xD3();    break;  // DCP - Indirect Indexed  Y
+        case 0xD4:   opcode_0xD4();    break;  // NOP - ZeroPage , X
+        case 0xD5:   opcode_0xD5();    break;  // CMP - ZeroPage , X
+        case 0xD6:   opcode_0xD6();    break;  // DEC - ZeroPage , X
+        case 0xD7:   opcode_0xD7();    break;  // DCP - ZeroPage , X
+        case 0xD8:   opcode_0xD8();    break;  // CLD
+        case 0xD9:   opcode_0xD9();    break;  // CMP - Absolute , Y
+        case 0xDA:   opcode_0xEA();    break;  // NOP
+        case 0xDB:   opcode_0xDB();    break;  // DCP - Absolute , Y
+        case 0xDC:   opcode_0xDC();    break;  // NOP - Absolute , X
+        case 0xDD:   opcode_0xDD();    break;  // CMP - Absolute , X
+        case 0xDE:   opcode_0xDE();    break;  // DEC - Absolute , X
+        case 0xDF:   opcode_0xDF();    break;  // DCP - Absolute , X
+        case 0xE0:   opcode_0xE0();    break;  // CPX - Immediate
+        case 0xE1:   opcode_0xE1();    break;  // SBC - Indexed Indirect X
+        case 0xE2:   opcode_0xE2();    break;  // NOP - Immediate
+        case 0xE3:   opcode_0xE3();    break;  // ISC - Indexed Indirect X
+        case 0xE4:   opcode_0xE4();    break;  // CPX - ZeroPage
+        case 0xE5:   opcode_0xE5();    break;  // SBC - ZeroPage
+        case 0xE6:   opcode_0xE6();    break;  // INC - ZeroPage
+        case 0xE7:   opcode_0xE7();    break;  // ISC - ZeroPage
+        case 0xE8:   opcode_0xE8();    break;  // INX
+        case 0xE9:   opcode_0xE9();    break;  // SBC - Immediate
+        case 0xEA:   opcode_0xEA();    break;  // NOP
+        case 0xEB:   opcode_0xE9();    break;  // SBC - Immediate
+        case 0xEC:   opcode_0xEC();    break;  // CPX - Absolute
+        case 0xED:   opcode_0xED();    break;  // SBC - Absolute
+        case 0xEE:   opcode_0xEE();    break;  // INC - Absolute
+        case 0xEF:   opcode_0xEF();    break;  // ISC - Absolute
+        case 0xF0:   opcode_0xF0();    break;  // BEQ - Branch on Zero Set
+        case 0xF1:   opcode_0xF1();    break;  // SBC - Indirect Indexed  Y
+        case 0xF2:   opcode_0xF2();    break;  // JAM
+        case 0xF3:   opcode_0xF3();    break;  // ISC - Indirect Indexed  Y
+        case 0xF4:   opcode_0xF4();    break;  // NOP - ZeroPage , X
+        case 0xF5:   opcode_0xF5();    break;  // SBC - ZeroPage , X
+        case 0xF6:   opcode_0xF6();    break;  // INC - ZeroPage , X
+        case 0xF7:   opcode_0xF7();    break;  // ISC - ZeroPage , X
+        case 0xF8:   opcode_0xF8();    break;  // SED
+        case 0xF9:   opcode_0xF9();    break;  // SBC - Absolute , Y
+        case 0xFA:   opcode_0xEA();    break;  // NOP
+        case 0xFB:   opcode_0xFB();    break;  // ISC - Absolute , Y
+        case 0xFC:   opcode_0xFC();    break;  // NOP - Absolute , X
+        case 0xFD:   opcode_0xFD();    break;  // SBC - Absolute , X
+        case 0xFE:   opcode_0xFE();    break;  // INC - Absolute , X
+        case 0xFF:   opcode_0xFF();    break;  // ISC - Absolute , X
+      }
+
+    } 
+}
diff --git a/README.md b/README.md
index 68fbb56..83534df 100644
--- a/README.md
+++ b/README.md
@@ -8,13 +8,16 @@ My YouTube Channel with some videos of the stuff in action: www.youtube.com/chan
 Boards:
 
 	MCL86jr -  IBMPCjr Accelerator which boosts performance to IBM PC/AT speed
+    MCL65+ - MOS 6502 emulator which runs on a Teensy 4.1 and can be used as a 6502 drop-in replacment
+	MCL64  - MOS 6510 emulator which runs on a Teensy 4.1 and can be used as a drop-in replacment in the Commodore 64
+
 	
 Emulated Processors:
 
 	MCL68  - Motorola 68000 Emulator written in C
     RISCV  - Simple and compact RISC-V RS32I implementation written in C
-    MCL65  - MOS 6502  written in C
-    MCL65+ - MOS 6502  emulator which runs on a Teensy 4.1 and can be used as a 6502 drop-in replacment
+    MCL65  - MOS 6502 written in C
+
 
 Microsequencer-based processors: