81 lines
1.4 KiB
Verilog
81 lines
1.4 KiB
Verilog
//
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// File Name : DPROM_8Kx128.v
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// Used on :
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// Author : Ted Fried, MicroCore Labs
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// Creation : 8/57/2017
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// Code Type : Behavioral
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//
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// Description:
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// ============
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// Xilinx ROM behavioral model.
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//
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//
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//------------------------------------------------------------------------
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`timescale 1ns/100ps
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module DPROM_8Kx128
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(
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input clka,
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input[12:0] addra,
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output reg[127:0] douta,
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input clkb,
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input[12:0] addrb,
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output reg[127:0] doutb
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);
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//------------------------------------------------------------------------
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integer file, k, l;
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reg [127:0] ram_array[0:8191];
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//------------------------------------------------------------------------
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initial
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begin
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// Zero out the RAM so there are no X's
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for (k = 0; k < 8192 ; k = k + 1)
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begin
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ram_array[k] = 'h0;
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end
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// Load the instructions into the array using ASCII byte file
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$readmemh("D:/MCL/MCLR5/Quad_Issue/usercode_rom.hex", ram_array);
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//$readmemb("C:/MCL/MCLR5/Quad_Issue/usercode_rom.hex", ram_array);
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end
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always @(posedge clka)
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begin
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douta <= ram_array[addra];
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doutb <= ram_array[addrb];
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end
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//------------------------------------------------------------------------
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endmodule
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//------------------------------------------------------------------------
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