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Polygonus-Universal
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Update design rules for JLC 4 layer

This commit is contained in:
Matthew Kennedy 2023-10-23 01:30:41 -07:00
parent b81e668230
commit 755683426e
1 changed files with 10 additions and 7 deletions
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17
Polygonus-Universal-Base.kicad_pro
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@ -114,8 +114,8 @@
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.19999999999999998,
"min_connection": 0.0,
"min_clearance": 0.127,
"min_connection": 0.127,
"min_copper_edge_clearance": 0.0,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
@ -125,9 +125,9 @@
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.25,
"min_via_annular_width": 0.049999999999999996,
"min_through_hole_diameter": 0.19999999999999998,
"min_track_width": 0.127,
"min_via_annular_width": 0.09999999999999999,
"min_via_diameter": 0.39999999999999997,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
@ -178,7 +178,10 @@
0.0,
0.25,
0.3,
0.4,
0.45,
0.5,
0.65,
0.8
],
"via_dimensions": [
@ -431,8 +434,8 @@
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"via_diameter": 0.5,
"via_drill": 0.3,
"wire_width": 6
}
],