diff --git a/README.md b/README.md index e52c131..fc1406b 100644 --- a/README.md +++ b/README.md @@ -1,16 +1,24 @@ -# Polygonus -Polygonus - PNP Proteus rusEFI +# Polygonus +Polygonus - PNP Proteus rusEFI -Proteus based brain board to enable modular PNP +Proteus based brain board to enable modular PNP -In scope - -- Critical systems on the majority of PNP targets -- up to 8 cylinder capability built into the brainn board -- Full feature set of the protues broken out to pins meaning vheicle board can add the additional circuits if required +In scope - +- Critical systems on the majority of PNP targets +- up to 8 cylinder capability built into the brainn board +- Full feature set of the protues broken out to pins meaning vheicle board can add the additional circuits if required -Out of scope - -- Race cars and tuned cars with large ammounts of additinal equipment (that's for a wire in proteus or atlas) -- Non-standard engines in chassis -- Additional equipment beyond common mods to the chassis +Out of scope - +- Race cars and tuned cars with large ammounts of additinal equipment (that's for a wire in proteus or atlas) +- Non-standard engines in chassis +- Additional equipment beyond common mods to the chassis + +Intended form factor - 80mm x 80mm up to 85mm x 85mm to suit the majority of cases but ideally as small as practical + +Current list of parts dropped from Proteus: +- 4x lowsides (remove two VNLD5090) +- Both ETB (TLE9201 only added if vehicle needs ) +- Both VR (board configured for hall and MAX added if vehicle needs VR, also larger MAX chip can be used) +- 4x High/low (TC4427) +- Knock signal headphone jack -Intended form factor - 80mm x 80mm up to 85mm x 85mm to suit the majority of cases but ideally as small as practical \ No newline at end of file diff --git a/proteus-backups/proteus-2022-07-31_233659.zip b/proteus-backups/proteus-2022-07-31_233659.zip new file mode 100644 index 0000000..7047ceb Binary files /dev/null and b/proteus-backups/proteus-2022-07-31_233659.zip differ diff --git a/proteus-backups/proteus-2022-07-31_234654.zip b/proteus-backups/proteus-2022-07-31_234654.zip new file mode 100644 index 0000000..5922e13 Binary files /dev/null and b/proteus-backups/proteus-2022-07-31_234654.zip differ diff --git a/proteus.kicad_prl b/proteus.kicad_prl new file mode 100644 index 0000000..0c9c3b3 --- /dev/null +++ b/proteus.kicad_prl @@ -0,0 +1,75 @@ +{ + "board": { + "active_layer": 0, + "active_layer_preset": "", + "auto_track_width": true, + "hidden_nets": [], + "high_contrast_mode": 0, + "net_color_mode": 1, + "opacity": { + "pads": 1.0, + "tracks": 1.0, + "vias": 1.0, + "zones": 0.6 + }, + "ratsnest_display_mode": 0, + "selection_filter": { + "dimensions": true, + "footprints": true, + "graphics": true, + "keepouts": true, + "lockedItems": true, + "otherItems": true, + "pads": true, + "text": true, + "tracks": true, + "vias": true, + "zones": true + }, + "visible_items": [ + 0, + 1, + 2, + 3, + 4, + 5, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 32, + 33, + 34, + 35, + 36 + ], + "visible_layers": "fffffff_ffffffff", + "zone_display_mode": 0 + }, + "meta": { + "filename": "proteus.kicad_prl", + "version": 3 + }, + "project": { + "files": [] + } +} diff --git a/proteus.kicad_pro b/proteus.kicad_pro new file mode 100644 index 0000000..a060ffd --- /dev/null +++ b/proteus.kicad_pro @@ -0,0 +1,381 @@ +{ + "board": { + "design_settings": { + "defaults": { + "board_outline_line_width": 0.05, + "copper_line_width": 0.2, + "copper_text_italic": false, + "copper_text_size_h": 1.5, + "copper_text_size_v": 1.5, + "copper_text_thickness": 0.3, + "copper_text_upright": true, + "courtyard_line_width": 0.05, + "other_line_width": 0.15, + "other_text_italic": false, + "other_text_size_h": 1.0, + "other_text_size_v": 1.0, + "other_text_thickness": 0.15, + "other_text_upright": true, + "silk_line_width": 0.12, + "silk_text_italic": false, + "silk_text_size_h": 1.0, + "silk_text_size_v": 1.0, + "silk_text_thickness": 0.15, + "silk_text_upright": true + }, + "diff_pair_dimensions": [ + { + "gap": 0.254, + "via_gap": 0.25, + "width": 0.254 + } + ], + "drc_exclusions": [], + "rule_severitieslegacy_courtyards_overlap": true, + "rule_severitieslegacy_no_courtyard_defined": false, + "rules": { + "allow_blind_buried_vias": false, + "allow_microvias": false, + "min_hole_to_hole": 0.25, + "min_microvia_diameter": 0.2, + "min_microvia_drill": 0.09999999999999999, + "min_through_hole_diameter": 0.2, + "min_track_width": 0.127, + "min_via_diameter": 0.45, + "solder_mask_clearance": 0.048, + "solder_mask_min_width": 0.09999999999999999, + "solder_paste_clearance": 0.0, + "solder_paste_margin_ratio": -0.0 + }, + "track_widths": [ + 0.254, + 0.254, + 0.3048, + 0.4064, + 0.6096, + 0.762, + 0.9144, + 1.016, + 1.27, + 1.524, + 2.032 + ], + "via_dimensions": [ + { + "diameter": 0.59944, + "drill": 0.29972 + }, + { + "diameter": 0.6, + "drill": 0.3 + }, + { + "diameter": 0.8, + "drill": 0.4 + }, + { + "diameter": 1.2, + "drill": 0.9 + }, + { + "diameter": 2.0, + "drill": 1.4 + } + ] + }, + "layer_presets": [] + }, + "boards": [], + "cvpcb": { + "equivalence_files": [] + }, + "erc": { + "erc_exclusions": [], + "meta": { + "version": 0 + }, + "pin_map": [ + [ + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 2, + 0, + 1, + 0, + 0, + 1, + 0, + 2, + 2, + 2, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 1, + 2 + ], + [ + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 2, + 1, + 1, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2 + ], + [ + 1, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 1, + 2 + ], + [ + 0, + 0, + 0, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 2, + 1, + 2, + 0, + 0, + 1, + 0, + 2, + 2, + 2, + 2 + ], + [ + 0, + 2, + 0, + 1, + 0, + 0, + 1, + 0, + 2, + 0, + 0, + 2 + ], + [ + 0, + 2, + 1, + 1, + 0, + 0, + 1, + 0, + 2, + 0, + 0, + 2 + ], + [ + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2 + ] + ], + "rule_severities": { + "bus_definition_conflict": "error", + "bus_entry_needed": "error", + "bus_label_syntax": "error", + "bus_to_bus_conflict": "error", + "bus_to_net_conflict": "error", + "different_unit_footprint": "error", + "different_unit_net": "error", + "duplicate_reference": "error", + "duplicate_sheet_names": "error", + "extra_units": "error", + "global_label_dangling": "warning", + "hier_label_mismatch": "error", + "label_dangling": "error", + "lib_symbol_issues": "warning", + "multiple_net_names": "warning", + "net_not_bus_member": "warning", + "no_connect_connected": "warning", + "no_connect_dangling": "warning", + "pin_not_connected": "error", + "pin_not_driven": "error", + "pin_to_pin": "warning", + "power_pin_not_driven": "error", + "similar_labels": "warning", + "unannotated": "error", + "unit_value_mismatch": "error", + "unresolved_variable": "error", + "wire_dangling": "error" + } + }, + "libraries": { + "pinned_footprint_libs": [], + "pinned_symbol_libs": [] + }, + "meta": { + "filename": "proteus.kicad_pro", + "version": 1 + }, + "net_settings": { + "classes": [ + { + "bus_width": 12.0, + "clearance": 0.2, + "diff_pair_gap": 0.25, + "diff_pair_via_gap": 0.25, + "diff_pair_width": 0.2, + "line_style": 0, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "Default", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 0.25, + "via_diameter": 0.8, + "via_drill": 0.4, + "wire_width": 6.0 + } + ], + "meta": { + "version": 2 + }, + "net_colors": null + }, + "pcbnew": { + "last_paths": { + "gencad": "", + "idf": "", + "netlist": "", + "specctra_dsn": "", + "step": "", + "vrml": "" + }, + "page_layout_descr_file": "" + }, + "schematic": { + "annotate_start_num": 0, + "drawing": { + "default_line_thickness": 6.0, + "default_text_size": 50.0, + "field_names": [], + "intersheets_ref_own_page": false, + "intersheets_ref_prefix": "", + "intersheets_ref_short": false, + "intersheets_ref_show": false, + "intersheets_ref_suffix": "", + "junction_size_choice": 3, + "label_size_ratio": 0.25, + "pin_symbol_size": 0.0, + "text_offset_ratio": 0.08 + }, + "legacy_lib_dir": "", + "legacy_lib_list": [], + "meta": { + "version": 1 + }, + "net_format_name": "Pcbnew", + "ngspice": { + "fix_include_paths": true, + "fix_passive_vals": false, + "meta": { + "version": 0 + }, + "model_mode": 0, + "workbook_filename": "" + }, + "page_layout_descr_file": "", + "plot_directory": "export/v0.7/", + "spice_adjust_passive_values": false, + "spice_external_command": "spice \"%I\"", + "subpart_first_id": 65, + "subpart_id_separator": 0 + }, + "sheets": [], + "text_variables": {} +}